KR20140039772A - Nitride baced semiconductor device and manufacturing method thereof - Google Patents

Nitride baced semiconductor device and manufacturing method thereof Download PDF

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KR20140039772A
KR20140039772A KR1020120106436A KR20120106436A KR20140039772A KR 20140039772 A KR20140039772 A KR 20140039772A KR 1020120106436 A KR1020120106436 A KR 1020120106436A KR 20120106436 A KR20120106436 A KR 20120106436A KR 20140039772 A KR20140039772 A KR 20140039772A
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layer
semiconductor
type gan
region
semiconductor layer
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KR1020120106436A
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Korean (ko)
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이재훈
김기원
이정희
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삼성전자주식회사
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Publication of KR20140039772A publication Critical patent/KR20140039772A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A nitride semiconductor device and a method of manufacturing the same are disclosed. The nitride-based semiconductor device according to the embodiment is a first n + type GaN layer, laminated in turn on the first n + type GaN layer, except for the first region a first semiconductor layer, a second semiconductor layer, and a third formed on the substrate A semiconductor laminate having a mesa structure comprising a semiconductor layer and having a topmost flat layer and sidewalls connected to the top layer, a gate insulating layer formed on an outer surface of the semiconductor laminate except for a second region of the top layer, and a gate formed on a gate insulating layer An electrode, a drain electrode formed in the first region on the first n + type GaN layer, and a source electrode formed on the third semiconductor layer exposed through the second region.

Description

Nitride-based semiconductor device and its manufacturing method {NITRIDE BACED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF}

Embodiments of the present invention relate to a nitride based semiconductor device having a structure capable of suppressing leakage current and a method of manufacturing the same.

Recently, with the rapid development of the information and communication industry, the demand for personal mobile communication, satellite communication, broadcasting communication, communication repeater, military radar, etc. related to wireless communication technology is gradually increasing. Therefore, there is a need for a high-speed, high-power electronic device required for an ultrahigh-speed information communication system in the microwave (μm) or millimeter wave (mm) band. In addition, high power power devices, and research and development to reduce the energy loss of the power device is required.

Gallium nitride (GaN) -based semiconductor materials have a wide energy gap, high thermal / chemical stability, and excellent physical properties such as high electron saturation rate (~ 3 × 10 7 cm / sec). Applicable to the device. In addition, an electronic device using a gallium nitride (GaN) -based semiconductor material has advantages such as high breakdown electric field (˜3 × 10 6 V / cm), high current density, stable operation at high temperature, and high thermal conductivity.

Heterostructure Field Effect Transistors (HFETs) using heterojunction structures of aluminum gallium nitride (AlGaN) / gallium nitride (GaN) generate band discontinuities at the junction interface. Can be. Thus, HFETs can have high electron mobility. This feature makes it possible to apply HFETs as high-power devices.

In general, power devices require large current densities. However, since the HFET has high electron mobility, current flow occurs even in a signal unapplied state, which consumes power. In particular, a normally on type power device has a disadvantage in that power loss is large due to this current flow. To compensate for this, a part of the aluminum gallium nitride (AlGaN) layer corresponding to the gate region is removed to develop a normally off power device.

However, it is difficult to accurately control the thickness of the aluminum gallium nitride (AlGaN) layer to about 30 nm or less in a normally off type power device. In addition, since the power element operates in a horizontal structure, the area of the power element must be increased to improve the current density.

The present embodiments provide a nitride based semiconductor device in which a current channel is formed along an outer surface of the semiconductor laminate by including a semiconductor laminate having a mesa structure, and a method of manufacturing the same.

The nitride-based semiconductor device according to an embodiment for achieving the above object is a first n + type GaN layer, the said second turn, laminated on the first n + type GaN layer, except for the first region a first semiconductor layer formed on a substrate A semiconductor layer having a mesa structure including a second uppermost layer and a third semiconductor layer and having a flat uppermost layer and sidewalls connected to the uppermost layer, and a gate formed on an outer surface of the semiconductor laminate except for the second region of the uppermost layer An insulating layer, a gate electrode formed on the gate insulating layer, a drain electrode formed on a first region on the first n + type GaN layer, and a source electrode formed on the third semiconductor layer exposed through the second region. do.

According to one side, the gate insulating layer may extend from the uppermost layer of the semiconductor laminate except for the second region to a portion of the first region along the sidewall to cover the outer surface of the semiconductor laminate.

According to one side, the drain electrode may be formed on the first region exposed to the outside of the gate insulating layer.

According to one side, the semiconductor laminate may have the sidewall of the inclined structure that is wider from the third semiconductor layer to the first semiconductor layer.

According to one side, the semiconductor laminate may have the sidewalls stepped stepwise.

In example embodiments, the first semiconductor layer may be an n-type GaN layer, the second semiconductor layer may be a p-type GaN layer, and the third semiconductor layer may be a second n + type GaN layer.

In example embodiments, the first semiconductor layer may be a p-type GaN layer, the second semiconductor layer may be an AlGaN layer, and the third semiconductor layer may be an n-type GaN layer.

Method of manufacturing a nitride-based semiconductor device according to the embodiment includes the steps of depositing a first n + type GaN layer on a substrate, a first semiconductor layer on the first n + type GaN layer, the second semiconductor layer and third semiconductor Stacking layers sequentially to form a mesa-structured semiconductor laminate comprising a flat top layer and sidewalls leading to the top layer, and etching the semiconductor laminate to expose a first region of the first n + type GaN layer. Forming a gate insulating layer on an outer surface of the semiconductor laminate except for the second region of the uppermost layer, forming a gate electrode on the gate insulating layer, a first layer on the first n + type GaN layer Forming a drain electrode in a region and forming a source electrode on the third semiconductor layer exposed through the second region.

The forming of the gate insulating layer may include depositing a gate insulating material extending from a top layer of the semiconductor laminate to a portion of the first region along the sidewall to cover an outer surface of the semiconductor laminate; And etching the gate insulating material deposited on the second region to expose the third semiconductor layer.

In example embodiments, the etching of the semiconductor laminate may include etching the semiconductor laminate to have the sidewalls having an inclined structure that becomes wider from the third semiconductor layer to the first semiconductor layer.

In example embodiments, the etching of the semiconductor laminate may include etching the semiconductor laminate to have the sidewalls having the step difference formed in a stepped manner.

According to one side, the step of forming the semiconductor laminate comprises depositing the first semiconductor layer by depositing n-type GaN on the first n + type GaN layer, depositing p-type GaN on the first semiconductor layer Stacking the second semiconductor layer, and depositing n + type GaN on the second semiconductor layer to stack the third semiconductor layer.

According to one side, the step of forming the semiconductor laminate comprises depositing the first semiconductor layer by depositing p-type GaN on the first n + type GaN layer, by depositing AlGaN on the first semiconductor layer Stacking a second semiconductor layer, and depositing n-type GaN on the second semiconductor layer to stack the third semiconductor layer.

The nitride-based semiconductor device and the method of manufacturing the same according to the present embodiments may include a semiconductor laminate having a mesa structure, so that a current channel may be formed along the outer surface of the semiconductor laminate.

1A and 1B are views illustrating a structure of a nitride based semiconductor device according to an embodiment.
2 illustrates a structure of a nitride based semiconductor device according to another exemplary embodiment.
3A to 3E are views illustrating a method of manufacturing a nitride based semiconductor device according to an embodiment.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A and 1B are views illustrating a structure of a nitride based semiconductor device according to an embodiment. FIG. 1A is a perspective view of a nitride semiconductor device, and FIG. 1B is a cross-sectional view of the nitride semiconductor device shown in FIG. 1A.

1A and 1B, the nitride semiconductor device 100 may include a substrate 110, a first n + type GaN layer 120, a semiconductor laminate 130, a gate insulating layer 140, and a gate electrode ( 150, a drain electrode 160, and a source electrode 170.

The substrate 110 may be a substrate for growing a nitride semiconductor single crystal. For example, a silicon substrate, a sapphire substrate, a silicon carbide substrate, or the like may be used as the substrate 110.

The first n + type GaN layer 120 is formed on the substrate 110. Although not shown in FIGS. 1A and 1B, a buffer layer is provided between the substrate 110 and the first n + type GaN layer 120 to reduce the difference in lattice constant between the substrate 110 and the first n + type GaN layer 120. This may be further included. The buffer layer may be made of GaN, but the present invention is not limited thereto, and the buffer layer may be applied to any semiconductor material capable of reducing the difference in lattice constant between the substrate 110 and the first n + type GaN layer 120.

The semiconductor laminate 130 includes a first semiconductor layer 131, a second semiconductor layer 132, and a third semiconductor layer 133 that are sequentially stacked on the first n + type GaN layer 120. The first semiconductor layer 131, the second semiconductor layer 132, and the third semiconductor layer 133 may be made of a GaN-based semiconductor material, and materials constituting each layer may vary according to the type of device.

According to an embodiment, when the nitride based semiconductor device 100 is a metal oxide semiconductor field effect transistor (MOSFET), the first semiconductor layer 131 is an n-type GaN layer, and the second semiconductor layer 132 is a p-type GaN. Layer, and the third semiconductor layer 133 may be a second n + type GaN layer.

According to another embodiment, when the nitride semiconductor device 100 is a heterojunction field effect transistor (HHET), the first semiconductor layer 131 is a p-type GaN layer, and the second semiconductor layer 132 is an AlGaN layer. The third semiconductor layer 133 may be an n-type GaN layer.

The semiconductor laminate 130 may be formed on the first n + type GaN layer 120 except for the first region. The first region may be an outer edge region of the first n + type GaN layer 120, but is not limited thereto, and may be part of an outer region of the semiconductor laminate 130.

The semiconductor laminate 130 may have a mesa structure including a flat top layer and sidewalls leading to the top layer. Here, the uppermost layer of the semiconductor laminate 130 may be an upper surface of the third semiconductor layer 133, and the sidewalls may include all side surfaces of the first to third semiconductor layers 131, 132, and 133. . The sidewall of the semiconductor laminate 130 may have a structure perpendicular to the uppermost layer, but may have an inclined structure that becomes wider from the third semiconductor layer 133 to the first semiconductor layer 131.

The gate insulating layer 140 is formed on the outer surface of the semiconductor laminate 130. In detail, the gate insulating layer 140 may be formed to exclude the second region of the uppermost layer of the semiconductor laminate 130, and the third semiconductor layer 133 may be exposed through the second region. In addition, the gate insulating layer 140 may cover the outer surface of the semiconductor stack 130 in a structure extending from the uppermost layer of the semiconductor stack 130 to a part of the first region along the sidewall.

The gate electrode 150 is formed on the gate insulating layer 140. Preferably, the gate electrode 150 may be formed to partially expose the gate insulating layer 140 without partially covering the gate insulating layer 140. This is to prevent contact between the gate electrode 150, the drain electrode 160, and the source electrode 170.

The drain electrode 160 is formed in the first region on the first n + type GaN layer 120. In detail, the drain electrode 160 may be formed on the first region exposed to the outside of the gate insulating layer 140.

The source electrode 170 may be formed on the third semiconductor layer 133 exposed through the second region.

On the other hand, the conventional nitride semiconductor device includes a trench dug in the direction of the substrate from the uppermost layer of the semiconductor laminate, the gate insulating layer and the gate electrode is formed inside the trench. In order to form this trench, an etching process is necessary, but damage may be caused by plasma in the etching process. In addition, it is difficult to precisely control the etch rate, and the process is complicated, resulting in defects or dislocations in the trenches. When a voltage is applied to each of the electrodes, a current channel is formed along the trench, and the breakdown voltage is lowered due to a defect or a potential generated in the trench. In addition, the electric field is concentrated in the trench, which increases the leakage current in the gate region.

1A and 1B, the semiconductor stack 130 has a mesa structure, the source electrode 170 is formed on the top layer of the semiconductor stack 130, and the gate electrode 150 is formed. It is formed on the outer surface of the semiconductor laminate 130, and the drain electrode 160 is at the outer edge on the first n + type GaN layer 120. Therefore, when a voltage is applied to each of the electrodes, a current channel (the arrow direction of the dotted line) may be formed in the direction in which the drain electrode 160 is formed along the sidewall from the top layer of the semiconductor stack 130. Since the current channel is formed along the outer surface of the semiconductor laminate 130, the nitride-based semiconductor device 100 has a high breakdown voltage because it is not affected by defects or dislocations or because the current channel is small. It can have a low leakage current.

2 illustrates a structure of a nitride based semiconductor device according to another exemplary embodiment. Referring to FIG. 2, the nitride-based semiconductor device 200 may include a substrate 210, a first n + type GaN layer 220, a semiconductor laminate 230, a gate insulating layer 240, a gate electrode 250, The drain electrode 260 and the source electrode 270 are included.

The substrate 210 may be a substrate for growing a nitride semiconductor single crystal.

The first n + type GaN layer 220 is formed on the substrate 210.

The semiconductor laminate 230 includes a first semiconductor layer 231, a second semiconductor layer 232, and a third semiconductor layer 233 that are sequentially stacked on the first n + type GaN layer 220.

When the nitride-based semiconductor device 200 is a metal oxide semiconductor field effect transistor (MOSFET), the first semiconductor layer 231 is an n-type GaN layer, the second semiconductor layer 232 is a p-type GaN layer, and the third The semiconductor layer 233 may be a second n + type GaN layer.

According to another embodiment, when the nitride semiconductor device 200 is a heterojunction field effect transistor (HHET), the first semiconductor layer 231 is a p-type GaN layer, and the second semiconductor layer 232 is an AlGaN layer. The third semiconductor layer 233 may be an n-type GaN layer.

The first to third semiconductor layers 231, 232, and 233 are not limited to the material layers described in the above embodiments, and other semiconductor materials may be applied.

The semiconductor laminate 230 may be formed on the first n + type GaN layer 220 except for the first region. The first region may be an outer edge region of the first n + type GaN layer 120.

The semiconductor laminate 230 may have a mesa structure including a flat top layer and a sidewall connected to the top layer. Here, the uppermost layer of the semiconductor laminate 230 may be an upper surface of the third semiconductor layer 233, and the sidewalls may include all side surfaces of the first to third semiconductor layers 231, 232, and 233. . In this embodiment, the semiconductor laminate 230 may have sidewalls having stepped steps. Through the sidewalls of the stepped structure, the nitride-based semiconductor device 200 may increase the breakdown voltage by distributing current.

The gate insulating layer 240 may be formed to exclude the second region of the uppermost layer of the semiconductor laminate 230, and the third semiconductor layer 233 may be exposed through the second region. In addition, the gate insulating layer 240 may cover the outer surface of the semiconductor stack 230 in a structure extending from the uppermost layer of the semiconductor stack 230 to a part of the first region along the sidewall.

The gate electrode 250 is formed on the gate insulating layer 240.

The drain electrode 260 may be formed on the first region exposed to the outside of the gate insulating layer 140.

The source electrode 270 may be formed on the third semiconductor layer 233 exposed through the second region.

When a voltage is applied to each of the electrodes, a current channel (dotted arrow) is formed in the direction in which the drain electrode 260 is formed along the sidewall of the step structure from the uppermost layer of the semiconductor stack 230 included in the nitride-based semiconductor device 200. Direction) can be formed. Since the current channel is formed along the outer surface of the semiconductor laminate 230, the nitride-based semiconductor device 200 may have a high breakdown voltage and a low leakage current.

3A to 3E are views illustrating a method of manufacturing a nitride based semiconductor device according to an embodiment. Referring to FIG. 3A, the manufacturing method includes depositing a first n + type GaN layer 320 on a substrate 310. The first n + type GaN layer 320 may be deposited using a metal organic chemical vapor deposition method.

Referring to FIG. 3B, the manufacturing method includes sequentially stacking a first semiconductor layer 331, a second semiconductor layer 332, and a third semiconductor layer 333 on the first n + type GaN layer 320. It includes. The first to third semiconductor layers 331, 332, and 333 may also be deposited using an organometallic chemical vapor deposition method. However, the deposition method of the first to third semiconductor layers 331, 332, and 333 is not limited to the above-described method, and other deposition methods used in the semiconductor process may be used.

First to third semiconductor layers (331, 332, 332) a first n + type GaN layer 320, the a, but the GaN-based semiconductor material may be deposited, the first n + type depending on the type of the device to form The material deposited on the GaN layer 320 may vary.

According to the embodiment, when fabricating a nitride based semiconductor device of a metal oxide semiconductor field effect transistor (MOSFET), the first semiconductor layer 331 is deposited by depositing n-type GaN on the first n + type GaN layer 320. The second semiconductor layer 332 by laminating p-type GaN on the first semiconductor layer 331, and depositing n + type GaN on the second semiconductor layer 332. 333) can be stacked.

According to another embodiment, when manufacturing a nitride-based semiconductor device of a heterojunction field effect transistor (HHET), by depositing p-type GaN on the first n + type GaN layer 320, the first semiconductor layer 331 The second semiconductor layer 332 is deposited by depositing AlGaN on the first semiconductor layer 331, and the third semiconductor layer 333 is deposited by depositing n-type GaN on the second semiconductor layer 332. Can be laminated.

Referring to FIG. 3C, the manufacturing method exposes a first region of the first n + type GaN layer 320 and etches the semiconductor laminate 330 to form a mesa structure having a planar top layer and a sidewall connected to the top layer. Steps. In this embodiment, the semiconductor laminate 330 is anisotropically etched to form a mesa structure, and the semiconductor laminate 330 is inclined to become wider from the third semiconductor layer 330 to the first semiconductor layer 310. It can have sidewalls of the structure.

In another embodiment, the semiconductor laminate 330 may be anisotropically etched to form a mesa structure, and may have sidewalls having a stepped step. In another embodiment, the semiconductor stack 330 may be isotropically etched to form a mesa structure, and the sidewall may be perpendicular to the top layer of the semiconductor stack 330.

Referring to FIG. 3D, the manufacturing method includes forming a gate insulating layer 340 on an outer surface of the semiconductor laminate 330 except for the second region of the uppermost layer. In detail, the forming of the gate insulating layer 340 may extend from the uppermost layer of the semiconductor laminate 330 shown in FIG. 3C to a part of the first region along the sidewall to cover the outer surface of the semiconductor laminate 330. Depositing a gate insulating material and etching the gate insulating material deposited in the second region to expose the third semiconductor layer 333. In this embodiment, the gate insulating material is Al 2 O. 3 or an insulating material such as SiO 2 .

Referring to FIG. 3E, the manufacturing method includes forming a gate electrode 350, a drain electrode 360, and a source electrode 370. Specifically, the gate electrode 350 is formed on the gate insulating layer 340, the drain electrode 360 is formed in the first region on the first n + type GaN layer 320, and exposed through the second region. The source electrode 370 may be formed on the third semiconductor layer 330. The gate electrode 350, the drain electrode 360, and the gate electrode 350 may be formed by depositing an electrode material in a region where each electrode is to be located.

In the nitride-based semiconductor device 300 manufactured by the method illustrated in FIGS. 3A to 3E, when a voltage is applied to each of the electrodes, a drain electrode 360 is formed along the sidewalls from the top layer of the semiconductor laminate 330. The current channel can be formed in the direction. That is, since the current channel is formed along the outer surface of the semiconductor laminate 330, the nitride based semiconductor device 300 may have a high breakdown voltage and a low leakage current.

As described above, although the present invention has been described with reference to the limited embodiments and the drawings, the present invention is not limited to the above-described embodiments, and various modifications and variations may be made by those skilled in the art. Therefore, the scope should not be limited to the described embodiments, but should be defined not only by the claims below, but also by those equivalent to the claims.

100: nitride semiconductor element
110 substrate 120 first n + type GaN layer
130: semiconductor laminate 140: gate insulating layer
150: gate electrode 160: drain electrode
170: source electrode

Claims (13)

A first n + type GaN layer formed on the substrate;
A mesa-structured semiconductor including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer sequentially stacked on the first n + type GaN layer except for the first region, and having a flat top layer and a sidewall connected to the top layer. Laminate;
A gate insulating layer formed on an outer surface of the semiconductor laminate except for the second region of the uppermost layer;
A gate electrode formed on the gate insulating layer;
A drain electrode formed in a first region on the first n + type GaN layer; And
A source electrode formed on the third semiconductor layer exposed through the second region
Nitride-based semiconductor device comprising a.
The method of claim 1,
Wherein the gate insulating layer
A nitride-based semiconductor device extending from the uppermost layer of the semiconductor laminate except for the second region to a part of the first region along the sidewall to cover the outer surface of the semiconductor laminate.
3. The method of claim 2,
The drain electrode
A nitride-based semiconductor device formed on the first region exposed to the outside of the gate insulating layer.
The method of claim 1,
The semiconductor laminate,
And the sidewalls of the inclined structure that are wider from the third semiconductor layer to the first semiconductor layer.
The method of claim 1,
The semiconductor laminate,
A nitride-based semiconductor device having the sidewalls stepped stepwise.
The method of claim 1,
The first semiconductor layer is an n-type GaN layer,
The second semiconductor layer is a p-type GaN layer,
And the third semiconductor layer is a second n + type GaN layer.
The method of claim 1,
The first semiconductor layer is a p-type GaN layer,
The second semiconductor layer is an AlGaN layer,
The third semiconductor layer is an n-type GaN layer, nitride-based semiconductor device.
Depositing a first n + type GaN layer on the substrate;
Forming a semiconductor laminate by sequentially stacking a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer on the first n + type GaN layer;
Exposing a first region of the first n + type GaN layer and etching the semiconductor laminate to form a mesa structure having a planar top layer and sidewalls leading to the top layer;
Forming a gate insulating layer on an outer surface of the semiconductor laminate except for the second region of the uppermost layer;
Forming a gate electrode on the gate insulating layer;
Forming a drain electrode in a first region on the first n + type GaN layer; And
Forming a source electrode on the third semiconductor layer exposed through the second region
Method of manufacturing a nitride-based semiconductor device comprising a.
9. The method of claim 8,
Forming the gate insulating layer,
Depositing a gate insulating material extending from an uppermost layer of the semiconductor laminate to a portion of the first region along the sidewalls and covering an outer surface of the semiconductor laminate; And
Etching the gate insulating material deposited in the second region to expose the third semiconductor layer.
Method of manufacturing a nitride-based semiconductor device.
9. The method of claim 8,
Etching the semiconductor laminate,
And etching the semiconductor laminate to have the sidewalls having an inclined structure that is wider from the third semiconductor layer to the first semiconductor layer.
9. The method of claim 8,
Etching the semiconductor laminate,
The semiconductor laminate is etched to have the sidewalls formed stepped stepwise.
9. The method of claim 8,
Forming the semiconductor laminate,
Depositing n-type GaN on the first n + type GaN layer to deposit the first semiconductor layer;
Depositing p-type GaN on the first semiconductor layer to stack the second semiconductor layer;
Depositing n + type GaN on the second semiconductor layer to stack the third semiconductor layer
Method of manufacturing a nitride-based semiconductor device comprising a.
9. The method of claim 8,
Forming the semiconductor laminate,
Depositing p-type GaN on the first n + type GaN layer to deposit the first semiconductor layer;
Depositing AlGaN on the first semiconductor layer to stack the second semiconductor layer;
Depositing n-type GaN on the second semiconductor layer to deposit the third semiconductor layer
Method of manufacturing a nitride-based semiconductor device comprising a.
KR1020120106436A 2012-09-25 2012-09-25 Nitride baced semiconductor device and manufacturing method thereof KR20140039772A (en)

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