KR20140034579A - Apparatus for channel decoding - Google Patents

Abstract

The present invention relates to a channel decoding device. A channel decoding device according to an embodiment of the present invention is a channel decoding device which performs low density parity check and includes: a variable node memory for storing a variable node value; a check node memory; a first calculation unit for calculating a log likelihood ratio for the variable node using the variable node value and check node value; a second calculation unit for calculating the size and sign of the check node based on the log likelihood ratio; a third calculation unit for calculating a check node update value based on the size and symbol of the check node; and a fourth calculation unit for calculating a variable node update value based on the check node update value and log likelihood ratio. The calculation for the log likelihood ratio calculation, the size and sign of the check node are performed for a second row which is the next row of a first row among the low density parity check matrix while the calculation for the check node update value and variable node update value for the first row among the low density parity check matrix. Therefore, the decoding time can be reduced. [Reference numerals] (340) Second calculation unit

Description

Apparatus for channel decoding

The present invention relates to a channel decoding apparatus, and more particularly, to a channel decoding apparatus capable of shortening a decoding time.

Almost all forms of electronic and communication devices use error-correcting codes. Error correction codes compensate for the inherent information transmission reliability in such devices by introducing redundancy into the data stream.

On the other hand, the mathematical error correction basis was set by Shannon. Shannon developed the mathematical concept of a channel in which signal distortion in communication systems is modeled as a random process. The most basic Shannon's result is the Noisy channel principle, which defines a quantity for a channel, that is, a quantity that defines the maximum rate at which information can be reliably delivered over that channel.

Reliable transmission at speeds near capacity requires the use of error correction codes. Thus, the error-correcting codes are designed to achieve as close as possible while attaining sufficient reliability. The complexity in implementing the error correction code is an additional factor that affects the practical application of the error correction codes.

Low-density partiy-check (LDPC) codes are a type of error correcting code that can not guarantee complete transmission, but can reduce the probability of information loss as much as desired. The LDPC code is the error correcting code closest to the Shannon limit, and is reevaluated as a very good error correcting code that can be used in a communication system.

It is an object of the present invention to provide a channel decoding apparatus capable of shortening a decoding time.

A channel decoding apparatus according to an embodiment of the present invention for achieving the above object is a channel decoding apparatus for performing a low density parity check, a variable node memory for storing a variable node value, a check node memory, a variable node value and a check A first calculation unit for calculating a log likelihood ratio for a variable node using the node value, a second calculation unit for calculating a magnitude value and a sign of the check node based on the log likelihood ratio, and a magnitude value of the check node And a third calculating unit for calculating the check node update value based on the symbols and, and a fourth calculating unit for calculating the variable node update value based on the check node update value and the log likelihood ratio, and the low density parity check. For the first row of the matrix, while the operation of the check node update value and the operation of the variable node update value are performed, for the second row which is the next row of the first row of the low density parity check matrix. The log likelihood ratio operation, the check node size value, and the sign operation are performed.

According to an embodiment of the present invention, the channel decoding apparatus may further include performing a check node update value and a variable node update value on a first row of a low density parity check matrix, while performing a first check of the low density parity check matrix. A log likelihood ratio operation, a magnitude value of a check node, and a sign operation may be performed on the second row, which is the next row of the row. As a result, the decoding time of channel decoding can be shortened.

On the other hand, when the magnitude value and the sign operation of the check node for the second row are processed, the decoding time of the channel decoding can be further shortened by processing the column having no data dependency on the first row before other columns.

On the other hand, by processing the barrel shift and the inverse barrel shift at once, the decoding time of the channel decoding can be further shortened.

On the other hand, since the updated variable node value can be directly used for the log likelihood ratio calculation without storing it in the variable node memory, the decoding time of channel decoding can be further shortened. In addition, access to the variable node memory becomes unnecessary, thereby reducing power consumption in the channel decoding apparatus.

1 is a diagram illustrating a Tanner graph.
2 illustrates an example of an LDPC code corresponding to the graph of FIG. 1.
3 shows a channel decoding apparatus according to an embodiment of the present invention.
4 to 6 are views referred to for describing the channel decoding apparatus of FIG. 3.
7 illustrates a channel decoding apparatus according to another embodiment of the present invention.
8 to 10 are diagrams referred to for describing the channel decoding apparatus of FIG. 7.
11 illustrates a channel decoding apparatus according to another embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the drawings.

The suffix "module" and " part "for components used in the following description are given merely for convenience of description, and do not give special significance or role in themselves. Accordingly, the terms "module" and "part" may be used interchangeably.

In the present specification, a low density parity check is performed using an LDPC matrix for channel decoding.

1 is a diagram illustrating a Tanner graph, and FIG. 2 illustrates an example of an LDPC code corresponding to the graph of FIG. 1.

Low Density Parity Check (LDPC) codes may be shown by bipartite graphs, often referred to as Tanner graphs, such as graph 100 shown in FIG. 1.

In Tanner graphs, variable nodes 102 correspond to a bit of a codeword, and in other sets of nodes, check nodes 106 may correspond to a set of parity-check constraints that define a code.

Edges 104 in the graph can connect variable nodes to check nodes. Variable nodes and check nodes are referred to as neighbors if they are connected by edges in the graph. It is typically assumed that node pairs are connected at most by one edge. LDPC codes may be represented equivalently using low density parity check matrix 202.

2 shows an example of a low density parity check matrix (H) 202. At this time, when the displayed vector (x) 208 has a relationship where Hx = 0, the vector (x) 208 corresponds to the case where there is no error.

For example, in the encoding apparatus, if a code word c in which a source message and a parity check bit are combined is transmitted, the relationship between the low density parity check matrix H and the code word c may be expressed by Equation 1 below.

Here, H may represent a low density parity check matrix, and c may represent a code word in which a source message and a parity check bit are combined.

On the other hand, if the code word (c) is transmitted in the encoding apparatus, the noise component (n) may be added through the channel, and in the decoding apparatus, the signal r to which the noise is added may be received.

On the other hand, the decoding apparatus performs a calculation using a low density parity check matrix to obtain a code word (c) and a source message (s) from the received signal (r). That is, since Hc = 0, the operation shown in Equation 3 can be established.

Meanwhile, the received signal r may be a digital signal of 0 and 1, and may be a fractional value between 0 and 1. FIG.

According to an embodiment of the present invention, when a fractional value between 0 and 1 is received using a low density parity check matrix, the channel decoding apparatus selects an appropriate value by using a probability of 0 or 1.

The received signal r can be used to represent an input probability at a variable node of a bipartite graph. The bit probability message is then passed from the variable node to the check node and summed at the variable node according to the parity check constraint. This data can generally be expressed as a log likelihood ratio defined as in equation (4).

Meanwhile, the LDPC code according to the embodiment of the present invention may be a macro matrix representing a block row and a block column of the low density parity check matrix. That is, the zero entry of the macro matrix may correspond to the partial matrix of ZxZ.

On the other hand, as an iterative decoding method for updating a probability value for an input node, in the embodiment of the present invention, layered decoding is performed. Equations 5 to 9 below are used at the time of layered decoding.

Equation 5 may represent a log likelihood ratio for each row for each column j of each row m of the checksum subset. That is, the log likelihood ratio L (q _mj ) for the variable node may be represented.

Where R _mj Denotes a check node value, and L (q _j ) denotes a variable node value.

Equation 6 may represent the size value A _mj of the check node to be calculated based on the log likelihood ratio L (q _mn ).

Equation 7 may represent the sign S _mj of the check node to be calculated based on the log likelihood ratio L (q _mn ).

Equation 8 may represent the check node update value R _{mj that} is calculated based on the size value A _mj of the check node and the sign S _mj .

Equation 9 may represent the variable node update value L (q _j ) calculated based on the check node update value R _mj and the log likelihood ratio L (q _mj ). At this time, for the row j, the variable node value may be updated.

On the other hand, when decoding is performed by the operation according to the equations (5) to (9), whether or not there is an error can be determined by the following equation (10).

That is, it may be determined whether Hr = 0, and if appropriate, it may be determined that proper decoding has been performed.

Hereinafter, a channel decoding apparatus according to an embodiment of the present invention will be described with reference to the drawings.

3 is a diagram illustrating a channel decoding apparatus according to an embodiment of the present invention, and FIGS. 4 to 6 are views referred to for describing the channel decoding apparatus of FIG. 3.

Referring to the drawing, the channel decoding apparatus 300 includes a variable node memory 310, a barrel shifter 315, a check node memory 320, a first recovery unit 323, a first calculation unit 330, and a first node. The second calculation unit 340, the third calculation unit 350, the second recovery unit 353, the fourth calculation unit 360, the inverse barrel shifter 365, and the buffer 370 may be provided.

As described above, it is assumed that layered decoding is performed. Equations 5 to 9 described above are used at the time of layered decoding.

The variable node memory 310 may store the variable node value L (q _j ) of Equation 5 or the variable node update value L (q _j ) of Equation 9.

The barrel shifter 315 performs a bit shift such that the variable node value L (q _j ) output from the variable node memory 310 is operable in the first calculation unit 330. To perform.

The check node memory 320 may store the size value A _mj of the check node of Equation 6, the sign S _mj of the check node of Equation 7, and position information about the size value and the sign. .

The first recovery unit 323 uses the size value A _mj of the check node, the sign S _mj of the check node of Equation 7, and the position information to determine the row m of the corresponding low density parity check matrix. For each column j, the check node value R _mj is output.

On the other hand, the check node memory 320 is not the check node value R _mj but the smallest value and the position of the check node size value A _mj , the next small value, and the sign of the check node ( By storing only S _mj ), the memory can be used efficiently.

The first calculation unit 330 may perform the calculation of Equation 5. That is, for each column j of the rows m of the low density parity check matrix, a log likelihood ratio for each row can be calculated.

In particular, the first calculation unit 330 includes the variable node value L (q _j ), which is bit shifted from the barrel shifter 315, and the check node value from the first recovery unit 323 ( R _mj ) can be used to calculate the log likelihood ratio L (q _mj ).

The second operation unit 340 may perform the operation of Equation 6 and the operation of Equation 7. That is, based on the log likelihood ratio L (q _mn ) calculated in the first calculation unit 330, the magnitude value A _{mj of the} check node and the sign S _mj of the check node can be calculated, respectively. have.

Meanwhile, the second operation unit 340 may perform an operation for searching for the xor bit operation and the minimum value min to perform the operation of Equation 6 and the operation of Equation 7.

In the second calculation unit 340, the magnitude value A _{mj of the} check node and the sign S _{mj of the} check node may be provided to the check node memory 320 and the third calculation unit 350, respectively. have.

Meanwhile, the first calculation unit 330 and the second calculation unit 340 may be configured as one unit as a check node processing unit (not shown).

The third calculation unit 350 may perform the calculation of Equation 8. That is, the check node update value R _mj can be calculated based on the magnitude value A _mj and the sign S _mj of the check node.

The third calculation unit 350 may include a normalization unit 353 and a second recovery unit 356.

The normalization unit 353 may perform normalization based on the magnitude value A _mj and the sign S _mj of the check node from the second calculation unit 340.

The second recovery unit 356 checks for each column j of the row m of the corresponding low density parity check matrix based on the size value A _mj and the sign S _mj of the normalized check node. Output the value R _mj .

The check node update value R _mj calculated in the third calculation unit 350 may be provided to the fourth calculation unit 360.

The fourth calculation unit 360 may perform the calculation of Equation 9. That is, the variable node update value L (q _j ) can be calculated based on the check node update value R _mj and the log likelihood ratio L (q _mj ).

The buffer 370 is disposed between the first calculation unit 330 and the fourth calculation unit 360, and logs for a predetermined row of the low density parity check matrix calculated at the first calculation unit 330. Can save the likelihood ratio.

In particular, the buffer 370 includes a log likelihood ratio L (q _mj ) operation for the second row of the low-density parity check matrix, and a check node in which the first calculation unit 330 and the second calculation unit 340 operate. The log likelihood ratio L (q _mj) for the first row of the low-density parity check matrix is transmitted to the fourth calculating unit 360 while performing the magnitude value A _mj and the sign node S _mj of the check node. ))

Accordingly, the fourth calculation unit 360 uses the log likelihood ratio L (q _mj ) for the first row received from the buffer 370, and the variable node update value L for the first row. (q _j )) can be calculated.

Meanwhile, the variable node update value L (q _j ) calculated by the fourth calculation unit 360 may be provided to an inverse barrel shifter 365.

Inverse barrel shifter 365 is a bit shifted in barrel shifter 315 to store variable node update value L (q _j ) in variable node memory 310. Consider, bit shift in reverse. The inverse barrel shifted variable node update value L (q _j ), which is output thereto, may be provided to the variable node memory 310. Accordingly, the variable node memory 310 may store the updated variable node update value L (q _j ).

Meanwhile, the third calculation unit 350 and the fourth calculation unit 360 may be configured as one unit as a variable node processing unit (not shown).

4 illustrates an example of a low density parity check matrix that can be used in a channel decoding apparatus according to an embodiment of the present invention.

The low density parity check matrix 400 of FIG. 4 may be a low density parity check matrix capable of hierarchical decoding according to an embodiment of the present invention.

Meanwhile, the codeword block length of the low density parity check matrix of FIG. 4 may be 1296 bits, and the subblock size may be 54 bits.

On the other hand, in the embodiment of the present invention, in order to shorten the decoding time of the channel decoding, after performing the operation on the first row of the conventional low density parity check matrix, performing the operation on the second row of the low density parity check matrix; By differentiating, while the operation of the check node update value and the operation of the variable node update value are performed on the first row 410 of the low density parity check matrix, the next row of the first row 410 of the low density parity check matrix is For the second row 420, log likelihood ratio operations, check node size values, and sign operations are performed.

That is, the check node update value and the variable node update value are performed on the first row 410 of the above-described low-density parity check matrix, and the first row 410 of the low-density parity check matrix is performed. A log likelihood ratio operation, a magnitude value of a check node, and a sign operation are performed on the second row 420 which is the next row.

5 is a view for briefly comparing a conventional calculation method with a calculation method according to an embodiment of the present invention.

Fig. 5 (a) shows a conventional calculation method, in which '1a' indicates the calculation of the equations (5) to (7) for the first row 410 of the low density parity check matrix, and '1b' indicates the first. The operations of equations (8) through (9) for row 410 are shown. Again, '2a' represents an operation of equations 5 to 7 for the second row 420, and '2b' represents an operation of equations 8 to 9 for the second row 420.

In FIG. 5A, after the operations of Equations 5 to 7 are performed on the first row 410 in time order, the operations of Equations 8 to 9 are performed on the first row 410. Then, it can be seen that the operations of Equations 5 to 7 are performed on the second row 420, and the operations of Equations 8 to 9 are performed again on the second row 420.

5B is a calculation method according to an embodiment of the present invention or a scheduling method of a channel decoding apparatus. After the calculations of Equations 5 to 7 are performed on the first row 410, the first row ( With respect to 410, the operations of Equations 8-9 are performed, and at the same time, the operations of Equations 5-7 are performed on the second row 420, and then, for the second row 420, While the operations of Equations 8 to 9 are performed, it can be seen that the operations of Equations 5 to 7 are performed on the third row at the same time.

According to this method, it is possible to shorten the decoding time of channel decoding of at least 25% or more as compared to the method of FIG. 5 (a).

On the other hand, according to another embodiment of the present invention, in order to shorten the decoding time of the channel decoding, when a data operation for each row of the low-density parity check matrix, for a predetermined column having no data dependency on the previous row, It is also possible to process before a column, or for a certain column with data dependencies on the next row, before other columns.

Referring to the second row 420 of the low-density parity check matrix 400 of FIG. 6, the entries of the first column, the fifth column, the ninth column, and the fourteenth column are '50', '48', and ' It can be seen that it has a value of 13 ',' 0 '.

In particular, the first column, the fifth column, the ninth column, and the fourteenth column of the second row 420 have predetermined values (the first column, the fifth column, the ninth column, and the fourteenth column, respectively). '40', '22', '43', and '0'), it can be seen that there is a data dependency.

Meanwhile, the second, sixth, eleventh, and fifteenth columns of the second row 420 each have a value of '1', '35', '30', and '0'. Since the first column, the fifth column, the ninth column, and the fourteenth column of the first row do not have corresponding values, it can be seen that there is no data dependency.

Meanwhile, as illustrated in FIG. 5B, the calculations of Equations 8 to 9 are performed on the first row 410, and at the same time, the calculations of Equations 5 to 7 are performed on the second row 420. , The first column, the fifth column, the ninth column, and the fourteenth column of the second row 420 have data dependency on the first row, and the second column and the sixth column of the second row 420. , Since the eleventh column and the fifteenth column have no data dependency on the first row, the calculations of Equations 5 to 7 for the second, sixth, eleventh, and fifteenth columns of the second row 420 are not performed. For example, the calculation may be performed earlier than the operations of Equations 5 to 7 on the first, fifth, ninth, and fourteenth columns of the second row 420. This makes it possible to prevent an error in data operation.

That is, the first calculation unit 330, when calculating the log likelihood ratio for the second row, has no data dependency on the first row, and the second, sixth, eleventh, and fifteenth columns of the second row. For columns, you can process them earlier than the other columns in the second row. That is, the log likelihood ratio may be calculated in the order of the second column, the sixth column, the eleventh column, the fifteenth column, and the first column, the fifth column, the ninth column, and the fourteenth column of the second row. .

In addition, the second calculation unit 340 includes the second column, the sixth column, and the eleventh column of the second row, in which there is no data dependency on the first row when the magnitude value and the sign calculation of the check node for the second row are performed. For the fifteenth column, we can process it earlier than the other columns in the second row. That is, in order of the second column, the sixth column, the eleventh column, the fifteenth column, and the first column, the fifth column, the ninth column, and the fourteenth column of the second row, Can be calculated.

Meanwhile, as illustrated in FIG. 5B, the calculations of Equations 8 to 9 are performed on the first row 410, and at the same time, the calculations of Equations 5 to 7 are performed on the second row 420. , The first column, the fifth column, the ninth column, and the fourteenth column of the first row 410 have data dependency on the second row 420, the seventh column of the first row 410, Since the eighth and thirteenth columns have no data dependency on the second row 420, Equations 8 to 9 of the first, fifth, ninth, and fourteenth columns of the first row 410 are shown. Is preferably performed earlier than the operations of Equations 8 to 9 for the seventh, eighth, and thirteenth columns of the first row 410. This makes it possible to prevent an error in data operation.

That is, the third calculation unit 350 may perform the first column, fifth column, and ninth column of the first row 410 having data dependency on the second row when calculating the check node update value for the first row. For the fourteenth column, processing may occur earlier than the other columns in the first row. That is, the check node update value may be calculated in the order of the first, fifth, ninth, and fourteenth columns, and the seventh, eighth, and thirteenth columns of the first row 410. .

In addition, the fourth calculation unit 360 may include the first column, the fifth column, and the ninth column of the first row 410 having data dependency on the second row when calculating the variable node update value for the first row. For the fourteenth column, processing may occur earlier than the other columns in the first row. That is, the variable node update value may be calculated in the order of the first, fifth, ninth, and fourteenth columns, and the seventh, eighth, and thirteenth columns of the first row 410. .

FIG. 7 illustrates a channel decoding apparatus according to another embodiment of the present invention, and FIGS. 8 to 10 are diagrams for explaining the channel decoding apparatus of FIG. 7.

Referring to the drawings, the channel decoding apparatus 700 of FIG. 7 is similar to the channel decoding apparatus 300 of FIG. 3, except that an inverse barrel shifter 365 is omitted. .

To this end, the barrel shifter 315 of FIG. 7 preferably has a shift value adjusted as in Equation 11 below.

Where BSa is the adjusted barrel shift value, BSc is the current barrel shift value, BSp is the previous barrel shift value,% represents the modulo operation, and Z represents the subblock size of the low density parity check matrix. Can be.

Looking at the first row fifth column and second row fifth column region 815 of the low density parity check matrix 400 illustrated in FIG. 8, if BSc is 48, BSp is 22, and Z is 54bit, BSa is It can be seen that 26. Accordingly, the adjusted barrel shift value can be 26.

Meanwhile, the first column region 805, the fifth column region 815, the ninth column region 825, and the fourteenth column region 845 of FIG. 8 have data dependency on each other between the first row and the second row. Example of having a.

On the other hand, the seventh column area 820, the eighth column area 830, and the thirteenth column area 840 of the first row and the second row of FIG. 8 are each other between the first row and the second row. Illustrates no dependencies.

Accordingly, as described above, when a data operation is performed on each row of the low density parity check matrix, a predetermined column having no data dependency on the previous row is processed before other columns, or the next row and data dependency For certain columns, it is also possible to process them earlier than the other columns.

On the other hand, Figure 9 is a unit-by-unit operation in the decoding apparatus, in the case of performing the operation of the equations (5) to (7) for each row, and then performing the operation of the equations (8) to (9) without using a buffer Illustrate scheduling.

The vertical axis represents the clock, the horizontal axis VNM.RE means read enable for the variable node memory, the VNM.RA means read address for the variable node memory, and B represents the operation of the barrel shifter. Cal L (q _mj ) denotes a log likelihood ratio L (q _mj ) calculation operation in the first calculation unit 330, and xor denotes a check node of the second calculation unit 340. A magnitude value A _mj and a sign S _mj arithmetic operation of the check node, and cal L (qj) is a variable node update value L (q _j ) operation in the fourth arithmetic unit 360. IB means operation of the inverse barrel shifter 365, VNM.WE means write enable state for the check node memory, and VNM.WA means write address state for the variable node memory. .

If the value of VNM.RE to VNM.WA is '-1', the corresponding unit does not operate. If the value has any other value, the corresponding unit operates.

From the first clock to the seventh clock, VNM.RE may have a value of '1', such that VNM.RA may have the first, fifth, seventh, and eighth columns for the first row. The ninth column, the thirteenth column, and the fourteenth column may be read. That is, the variable node memory 310 has the first column, the fifth column, the seventh column, the eighth column, the ninth column, the thirteenth column, for the first row, from the first clock to the seventh clock, respectively. A value for column 14 may be output.

The first region 910 of FIG. 9 is located in the first, fifth, seventh, eighth, ninth, thirteenth, and fourteenth columns of the first row in the first calculation unit 330. To perform a log likelihood ratio (L (q _mj )) operation.

The second region 920 of FIG. 9 is located in the first, fifth, seventh, eighth, ninth, thirteenth, and fourteenth columns of the first row in the fourth calculation unit 360. For a variable node update value L (q _j ).

Looking at the third region 925 of FIG. 9 during the time corresponding to the second region 920 of FIG. 9, it can be seen that the first calculation unit 330 does not operate.

In addition, during the time corresponding to the fourth region 930 of FIG. 9, the first calculation unit 330 may include the first column, the second column, the fifth column, the sixth column, the ninth column, A log likelihood ratio L (q _mj ) operation is performed on the eleventh, fourteenth, and fifteenth columns.

That is, FIG. 9 shows Equation 8 for the first row 410 after the operations of Equations 5 to 7 are performed on the first row 410 in the order of time, as shown in FIG. 5 (a). To 9 are performed, and then the operations of Equations 5 to 7 are performed on the second row 420, and again the operations of Equations 8 to 9 are performed on the second row 420. It can be seen that.

FIG. 10 exemplifies operation scheduling for each unit in the decoding apparatus of FIG.

Looking at it, it can be seen that, unlike FIG. 9, BUF.WE to BUF.RA are further added to the horizontal axis.

BUF.WE stands for write enable for buffer memory, BUF.WA stands for write address for buffer memory, BUF.RE stands for read enable for buffer memory, and BUF.RA stands for buffer memory. It means read address.

From the first clock to the seventh clock, VNM.RE may have a value of '1', such that VNM.RA may have the first, fifth, seventh, and eighth columns for the first row. The ninth column, the thirteenth column, and the fourteenth column may be read.

In this case, as described above, the order of outputting from the variable node memory 310 may be changed in order to perform an operation on a column having no data dependency on the second row.

The eighth, seventh, and fourteenth columns of the first row are outputted first because there is no data dependency with the twelfth row corresponding to the previous row of the first row, and thereafter, the data dependency with the twelfth row. It is possible that the first column, the fifth column, the ninth column, and the thirteenth column of the first row are present.

That is, the variable node memory 310 has the eighth, seventh, and fourteenth columns, and the first, fifth, and ninth columns, for the first row, from the first clock to the seventh clock, respectively. The values for the column and the thirteenth column can be output in order.

On the other hand, the barrel shifter 315 is one clock after the variable node memory 310, that is, from the second clock to the eighth clock, for the first row, the eighth column, the seventh column, the fourteenth column, The entry values of the first, fifth, ninth, and thirteenth columns may be output.

At this time, it is possible to output the adjusted barrel shift value in consideration of the fact that the inverse barrel shifter is not arranged, as in the above equation (11). At this time, since the barrel shift value of the previous row does not exist, eventually, the eighth column, the seventh column, the fourteenth column, and the first, fifth, ninth, and thirteenth columns of the first row. Each entry value can be printed as it is.

Next, the first calculation unit 330 has a log likelihood ratio L (q _mj ) for each column of the first row two clocks later than the barrel shifter 315, that is, from the fourth clock to the tenth clock. You can perform the operation.

The first region 1010 of FIG. 10 is located in the first, fifth, seventh, eighth, ninth, thirteenth, and fourteenth columns of the first row in the first calculation unit 330. To perform a log likelihood ratio (L (q _mj )) operation.

At this time, as described above, for the region 1015 for the eighth, seventh, and fourteenth columns of the first row, which has no data dependency on the twelfth row (corresponding to the previous row of the first row), The log likelihood ratio (L (q _mj )) operation is performed earlier, and thereafter, for the first, fifth, ninth, and thirteenth columns of the first row, which has a data dependency on the twelfth row. , Log likelihood ratio L (q _mj ) may be performed.

Next, the second calculation unit 340 has a magnitude value A of the check node for each column of the first row one clock after the first calculation unit 330, that is, from the fifth clock to the eleventh clock. _mj ) and a sign S _mj can be performed.

Meanwhile, the buffer 370 may operate at the same time as the second calculation unit 340 to store the log likelihood ratio L (q _mj ) output from the first calculation unit 330. That is, from the fifth clock to the eleventh clock, BUF.WE can have a value of '1', whereby BUF.WA can be used for eighth, seventh, fourteenth, and The first column, the fifth column, the ninth column, and the thirteenth column can be written.

In this way, the operation for Equations 5 to 7 for the first row can be ended.

Next, VNM.RE may have a value of '1' from the ninth clock to the sixteenth clock in order to perform an operation on Equations 5 to 7 on the second row, and thus, VNM. The RA may read for the first row, the second column, the fifth column, the sixth column, the ninth column, the eleventh column, the fourteenth column, and the fifteenth column for the second row.

In this case, as described above, the order of outputting from the variable node memory 310 may be changed in order to perform an operation on a column having no data dependency on the first row.

The second column, the sixth column, the eleventh column, and the fifteenth column of the second row are outputted first because there is no data dependency with the first row, and thereafter, with a second data dependency with the first row. It is possible that the first, fifth, ninth, and fourteenth columns of a row are output.

That is, the variable node memory 310 stores the second column, the sixth column, the eleventh column, the fifteenth column, and the first column, the fifth column, in the second row from the ninth clock to the sixteenth clock, respectively. The values for the ninth column and the fourteenth column can be output in this order.

On the other hand, the barrel shifter 315 is one clock after the variable node memory 310, that is, from the tenth clock to the seventeenth clock, the second, sixth, eleventh, and fifteenth rows of the second row. The entry values of the columns and the first, fifth, ninth, and fourteenth columns can be output.

At this time, it is possible to output the adjusted barrel shift value in consideration of the fact that the inverse barrel shifter is not arranged, as in the above equation (11).

The second, sixth, eleventh, and fifteenth columns of the second row, where the barrel shift values of the previous row do not exist, are the respective entry values ("1", "35", "30", " 0 ') can be printed as is.

On the other hand, the first column, the fifth column, the ninth column, and the fourteenth column of the second row, in which the barrel shift values of the previous row exist, are adjusted by the above-described equation (11). '26', '24', and '0') can be output respectively.

Next, the first calculation unit 330 has a log likelihood ratio L (q _mj ) for each column of the second row two clocks after the barrel shifter 315, that is, from the twelfth clock to the nineteenth clock. You can perform the operation.

The second region 1015 of FIG. 10 includes the second, sixth, eleventh, and fifteenth columns, and the first, fifth, and fifth columns of the second row in the first calculation unit 330. The log likelihood ratio L (q _mj ) operation is performed on the 9th and 14th columns.

Next, the second calculation unit 340 has a magnitude value A of the check node for each column of the second row one clock after the first calculation unit 330, that is, from the thirteenth clock to the twentieth clock. _mj ) and a sign S _mj can be performed.

Meanwhile, the buffer 370 may operate at the same time as the second calculation unit 340 to store the log likelihood ratio L (q _mj ) output from the first calculation unit 330. That is, from the thirteenth clock to the nineteenth clock, the BUF.WE may have a value of '1', and accordingly, the BUF.WA may have the second, sixth, eleventh, and fifteenth columns of the second row. The first column, the fifth column, the ninth column, and the fourteenth column can be written.

Meanwhile, the log likelihood ratio L (q _mj ) for the first row previously stored from the buffer 370 may be output before the writing of the second row of the buffer 370, that is, one clock. .

That is, from the twelfth clock to the eighteenth clock, the BUF.RE may have a value of '1', and accordingly, the BUF.RA is the first column, the fifth column, the seventh column, and the eighth column of the first row. The ninth column, the thirteenth column, and the fourteenth column may be read.

At this time, the output order from the buffer 370 to the fourth operation unit 360 is a log for the first column, the fifth column, the ninth column, and the fourteenth column of the first row having the data dependency with the second row. likelihood ratio (L (q _mj)) the first output, and second there is no data dependency between the second row and the seventh column in the first row and the eighth column, the 13 log-likelihood ratio (L (q _mj)) for the columns Can be output later.

Accordingly, the fourth operation unit 360 may perform the first column, the fifth column, and the first row of the first row for each column of the first row after the buffer 370 output operation, that is, from the thirteenth clock to the nineteenth clock. The variable node update value L (q _j ) can be calculated for the seventh, eighth, ninth, thirteenth, and fourteenth columns.

The third region 1020 of FIG. 10 is connected to the first, fifth, seventh, eighth, ninth, thirteenth, and fourteenth columns of the first row in the fourth calculation unit 360. To compute the variable node update value L (q _j ).

In this way, as shown in FIG. 5 (b), while the operations on the equations 5 to 7 are performed on the second row, the operations on the equations 8 to 9 on the first row are performed at the same time. Can be.

Similarly, it can then be seen that the operations of Equations 8-9 on the second row 420 are performed, while at the same time the operations of Equations 5-7 on the third row are performed. According to this method, it is possible to shorten the decoding time of at least 25% or more of channel decoding as compared to the scheduling method of FIG.

11 illustrates a channel decoding apparatus according to another embodiment of the present invention.

Referring to FIG. 11, the channel decoding apparatus 1100 of FIG. 11 is similar to the channel decoding apparatus 700 of FIG. 7, except that a variable multiplexer is provided between the variable node memory 310 and the barrel shifter 315. The difference is that 312 is further placed.

The multiplexer 312 may receive the variable node update value calculated by the fourth operation unit 360 and immediately provide the variable node update value received by the barrel shifter 315. As described above, since the process of storing the variable node update value calculated by the fourth operation unit 360 in the variable node memory 310, reading out the data again, and outputting the same is omitted, the decoding time of channel decoding can be shortened.

On the other hand, the variable node update value calculated in the fourth calculation unit 360 may be stored in the variable node memory 310, and in this case, the multiplexer 312 may optionally be stored in the variable node memory 310. The stored variable node update value may be output, or the variable node update value received directly by the four calculation unit 360 may be output.

Meanwhile, since the inverse barrel shifter 365 is omitted in the decoding apparatus 1100 of FIG. 11, the shifter value of the barrel shifter 315 may be adjusted according to Equation 11 described above.

On the other hand, as described above, the decoding apparatus 1100 of FIG. 11, prior to the operation of data for each row of the low density parity check matrix, for a predetermined column having no data dependency on the previous row, is earlier than other columns. It is also possible to process, or for some column with data dependence on, the next row, before the other columns.

As described above, according to the channel decoding apparatus 1100 of FIG. 11, the number of clocks required for one iteration in Wi-Fi (IEEE Std 802.11) can be reduced to 88 to 110 clocks. This means that iterations can be made five to six times or more in a “latency constraint” of around 570 clocks, which allows the performance of LDPC code to be properly utilized.

In particular, the channel decoding apparatus 1100 of FIG. 11 can be applied to LDPC decoders of DVB-T2 and DVB-C2, and can obtain effects of securing LDPC decoding performance, reducing circuit size, and reducing power consumption.

In the channel decoding apparatus according to the embodiment of the present invention, the configuration and method of the embodiments described above may not be limitedly applied, but the embodiments may be modified in whole or in part to enable various modifications. It may alternatively be configured in combination.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

Claims (16)

A channel decoding apparatus for performing a low density parity check,
A variable node memory for storing a variable node value;
Check node memory;
A first calculating unit for calculating a log likelihood ratio for a variable node using the variable node value and the check node value;
A second calculating unit for calculating a magnitude value and a sign of a check node based on the log likelihood ratio;
A third calculating unit for calculating a check node update value based on a magnitude value of the check node and a sign; And
A fourth calculation unit configured to calculate a variable node update value based on the check node update value and the log likelihood ratio,
For the first row of the low density parity check matrix, for the second row that is the next row of the first row of the low density parity check matrix while the operation of the check node update value and the operation of the variable node update value are performed. And a log likelihood ratio operation, a magnitude value of the check node, and a sign operation. The method of claim 1,
And a buffer for storing the log likelihood ratio calculated in the first calculation unit. 3. The method of claim 2,
The buffer is
And while the first calculation unit calculates a log likelihood ratio for the second row, provides the log likelihood ratio for the first row to the fourth calculation unit. The method of claim 1,
While the third computing unit and the fourth computing unit respectively perform the operation of the check node update value and the variable node update value on the first row of the low density parity check matrix,
And the first operation unit and the second operation unit perform a log likelihood ratio operation, a size value operation of a check node, and a sign operation of a check node, on the second row, respectively. The method of claim 1,
The first calculation unit,
In calculating a log likelihood ratio for the second row, a predetermined column of the second row, which has no data dependency with the first row, is processed before other columns of the second row. A channel decoding apparatus. The method of claim 1,
The second calculation unit,
In the calculation of the magnitude and sign of the check node for the second row, processing of a predetermined column of the second row, which has no data dependency with the first row, is performed before other columns of the second row. Channel decoding apparatus characterized in that the. The method of claim 1,
The third calculation unit,
In calculating a check node update value for the first row, a predetermined column of the first row, which has a data dependency with the second row, is processed before other columns of the first row. Channel decoding apparatus. The method of claim 1,
The fourth calculation unit,
In calculating a variable node update value for the first row, a predetermined column of the first row, which has a data dependency with the second row, is processed before other columns of the first row. Channel decoding apparatus. The method of claim 1,
And a multiplexer configured to receive the variable node update value calculated in the fourth computing unit and provide the received variable node update value to the first computing unit. 10. The method of claim 9,
The multiplexer comprising:
Receiving a variable node update value stored in the variable node memory, and providing one of the variable node update value from the fourth computing unit and the variable node update value from the variable node memory to the first computing unit; Channel decoding apparatus, characterized in that. The method of claim 1,
And a barrel shifter disposed between the variable node memory and the first computing unit and performing a bit shift so that the variable node value, which is output from the variable node memory, is operable in the first computing unit. Channel decoding apparatus. 12. The method of claim 11,
And a reverse barrel shifter performing bit shifting in reverse in consideration of the bit shift in the barrel shifter, in order to store the variable node update value calculated in the fourth calculation unit in the variable node memory. A channel decoding apparatus. 12. The method of claim 11,
The barrel shifter,
Calculate an adjusted barrel shift value based on the current barrel shift value, the barrel shift value of the previous row, and the sub-block size of the low density parity check matrix, and perform a bit shift according to the adjusted barrel shift value. Channel decoding apparatus. The method of claim 1,
The check node memory,
And a smallest value among the magnitude values of the check nodes calculated in the second calculation unit, its position, and a next small value and a sign. 15. The method of claim 14,
And a first recovery unit which calculates a check node value using the size value and the sign of the check node stored in the check node memory and outputs the calculated check node value to the first calculation unit. A channel decoding apparatus. The method of claim 1,
The third calculation unit,
A normalization unit that performs normalization based on a magnitude value and a sign of a check node from the second calculation unit; And
And a second recovery unit for calculating a check node value using the normalized check node size and a sign, and outputting the calculated check node value to the fourth calculation unit. Device.

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