KR20140029977A - Semiconductor memory apparatus - Google Patents

Semiconductor memory apparatus Download PDF

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KR20140029977A
KR20140029977A KR1020120096737A KR20120096737A KR20140029977A KR 20140029977 A KR20140029977 A KR 20140029977A KR 1020120096737 A KR1020120096737 A KR 1020120096737A KR 20120096737 A KR20120096737 A KR 20120096737A KR 20140029977 A KR20140029977 A KR 20140029977A
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South Korea
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data
line
global
local
cell array
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KR1020120096737A
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Korean (ko)
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양선석
권기창
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에스케이하이닉스 주식회사
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Publication of KR20140029977A publication Critical patent/KR20140029977A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

According to another aspect of the present invention, a semiconductor memory device includes a first cell array region configured to output first data through a first local line, and a second cell array region configured to output second data through a second local line. A first local amplifier for detecting and amplifying the first data of the local line and delivering the first data to the first semi-global line;
A second local amplifier for sensing and amplifying the second data of the second local line and delivering the second data to the second semi-global line, and sequentially transmitting the first and second data of the first and second semi-global lines to one global line; And a transfer selector for transferring, wherein the first data movement path from the first cell array region to the first semi-global line and the second data movement path from the second cell array region to the second semi-global line are mutually different. It does not have a shared movement path.

Figure P1020120096737

Description

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a data transfer technology of semiconductor memory devices.

Semiconductor memory devices have increased data storage capacities, such as single data rate DRAM (SDR), double data rate DRAM (DDR), DDR2, and DDR3, as well as speeding up data processing and increasing output bandwidth. .

As technology advances, the number of bits of data that must be read from or written to a memory cell increases by almost two times with one column operation. As a means for increasing the output bandwidth, the concept of pre-fetch has been introduced. Prefetch is a concept of simultaneously reading data from a plurality of memory cells constituting a unit cell array area, latching the same, and sequentially outputting the data.

Although the number of data that can be read at the same time, that is, the prefetch rate increases, there is an advantage of increasing the data processing speed. However, the core area is sacrificed due to the increase in the number of local amplifiers and lines. That is, the column operation refers to an operation of reading or writing data by selecting a bit line that meets the activated word line. When the number of bits of the data increases by two times, the column as well as the signal line for inputting / outputting data The circuit configuration for controlling the operation also doubles.

A semiconductor memory device includes a memory cell array including a bit line and a transistor connected to a word line, and a bank having a predetermined size including a circuit for writing data to or reading data from the memory cell array. Bank) and peripheral circuitry for inputting data input from the outside of the semiconductor memory device into the bank or outputting data output from the bank to the outside of the semiconductor memory device.

1 is a conceptual diagram of a general semiconductor memory device.

Referring to FIG. 1, a semiconductor memory device having eight banks B0 to B7 is illustrated. One bank 10 includes an upper bank B0_U and a lower bank B0_L, and the upper bank B0_U and the lower bank B0_L each include first to eighth unit octets, which are eight cell array regions. OCTET0 to OCTET7).

FIG. 2 is a configuration diagram of unit octets in the semiconductor memory device shown in FIG. 1.

Each of the unit cell array 0 and the unit cell array 1 includes a plurality of memory cells connected between a bit line and a word line (not shown). In addition, bit line sense amplifiers SA0 to SA7 are connected to bit line pairs of memory cells constituting each unit cell array.

In the read operation, the bit line sense amplifiers SA0 to SA7 first amplify data of the selected memory cell and provide them to the local lines LIO_0 to LIO_7.

The data provided to the local lines LIO_0 to LIO_7 are transferred to the local amplifiers IOSA, which are input / output sense amplifiers, respectively, and are second amplified. When the sensing enable signal is enabled, the local amplification unit IOSA provides the second amplified data to the global lines GIO_0 to GIO_7.

In addition, the data provided on the global lines GIO_0 to GIO_7 are output to the output pads in the designated order. To this end, a component such as a multiplexer or a pipe latch is required, of course.

3A is a block diagram illustrating arrangement and input / output of unit octets of a general semiconductor memory device.

3B is a timing diagram of data control during a read operation of the general semiconductor memory device of FIG. 3A.

3A and 3B, the operation of a general semiconductor memory device will be described.

When the read command Read is input, the column selection control signal CASP_YA is activated to a high level after a predetermined time has elapsed, and the next input / output sense amplifier strobe signal IOSASTB is activated to a high level.

In response to the activation signal of the column selection control signal CASP_YA and the sense amplifier strobe signal IOSASTB, data recorded in the cell array region of the first to eighth unit octets OCTET0 to OCTET7 is stored in the first to eighth local area. First to eighth global lines GIO_0 <0: 7> to GIO_7 <through the lines LIO_0 <0: 7> to LIO_7 <0: 7> and the first to eighth local amplifiers IOSA0 to IOSA7. 0: 7>) at the same time.

Data of the first to eighth global lines GIO_0 <0: 7> to GIO_7 <0: 7> is output to the outside of the semiconductor memory device through the input / output pad PAD (not shown) according to the strobe signal DQS. . Here, if the input / output pads output 8-bit signals with 8, the data of the first to eighth global lines GIO_0 <0: 7> to GIO_7 <0: 7> are the first data bundle (GIO_0 <0: Data from 7> to the last data set (data of GIO_7 <0: 7>) in order from the strobe signal DQS one by one according to the strobe signal DQS.

As described above, in the current eight-bank structure semiconductor memory device, eight local amplifiers and eight global lines are disposed in one octet. Therefore, 64 local amplifiers and 64 global lines are required for the upper bank, and the same number of local amplifiers and global lines are required for the lower bank. As a result, one bank requires 128 local amplifiers and 128 global lines.

Here, since the global line refers to a line commonly connected to all banks of the semiconductor memory device, the global line is designed to have a length of several thousand μm, and the local amplifier must be designed to sufficiently drive such a global line. It is also advantageous to increase the width of the global line to achieve low impedance.

As such, as the prefetch rate increases to increase bandwidth, the area occupied by the local line, the local amplification unit, and the global line increases, thereby increasing the sacrifice area of the core. In order to prevent such an increase in the area of sacrifice, the sharing means of the local line, the local amplifier and the global input / output line can be considered. There is a problem of inhibiting the speed-up operation by requiring an operation clock. Therefore, the area reduction and the speed-up operation through the sharing means are in a trade-off relationship, and there is a great difficulty in reducing the area through the optimal sharing means while maintaining the speed-up operation because there are a great variety of sharing means.

The present invention has been made in an effort to provide an optimized semiconductor memory device capable of reducing an increase in area due to an increase in bandwidth while maintaining a high data rate without increasing an internal operating clock.

According to another aspect of the present invention, a semiconductor memory device includes a first cell array region configured to output first data through a first local line, and a second cell array region configured to output second data through a second local line. A first local amplifier configured to sense and amplify first data of a local line to a first semi-global line, and a second local amplifier to sense amplify and transmit second data of the second local line to a second semi-global line And a transfer selector for sequentially transferring the first and second data of the first and second semi-global lines to one global line, and moving the first data from the first cell array region to the first semi-global line. The path and the second data movement path from the second cell array region to the second semi-global line do not have a movement path shared with each other.

The semiconductor memory device according to the present invention adjusts positions according to the order of data output octets and is provided separately without sharing local lines and input / output sense amplifiers, thereby maintaining high data processing speed without further increasing an internal operating clock, and globally. The lines can be shared to reduce the increase in area with increasing bandwidth.

1 is a conceptual diagram of a general semiconductor memory device.
FIG. 2 is a block diagram illustrating a unit octet included in the semiconductor memory device shown in FIG. 1.
3A is a block diagram illustrating arrangement and input / output of octets of a general semiconductor memory device.
3B is a timing diagram illustrating data control during a read operation of the general semiconductor memory device of FIG. 3A.
4A is a block diagram illustrating a unit octet included in a semiconductor memory device according to an embodiment of the present invention.
4B is a block diagram illustrating arrangement and input / output of unit octets of a semiconductor memory device according to an embodiment of the present invention.
4C is a timing diagram illustrating data control during a read operation of a semiconductor memory device according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

4A is a block diagram illustrating a unit octet included in a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 4A, a configuration of a unit octet of a semiconductor memory device and a prefetch operation thereof will be described below.

The unit octet includes cell arrays 110 and 120 including a plurality of memory cells, word lines WL, internal input / output bit line pairs SIOT / SIOB, bit line sense amplifiers SA, and local line pairs LIOT / LIOB. ), Local amplifiers (IOSA), and quasi-global lines (BGIO_0 <0: 7>). Here, the global line refers to an input / output line commonly connected to all banks of the semiconductor memory device.

The plurality of memory cell pairs are connected to an internal input / output bit line pair (SIOT / SIOB), and the internal input / output bit line pair (SIOT / SIOB) is sensed and amplified through a bit line sense amplifier (SA) to be a local line pair (LIOT / LIOB). Is connected to. The local line pair LIOT / LIOB is amplified via a local amplifier IOSA and connected to one quasi-global line BGIO_0 <0>.

In the prefetch read operation, the bit line sense amplifiers SA use the selected memory cells and paired memory cells to read data of the selected memory cell from an internal input / output bit line pair (SIOT / SIOB, SIO_0 <0: 7>). It senses and amplifies the signal through a local line pair (LIOT / LIOB, LIO_0 <0: 7>).

The data of the selected memory cells provided to the local line pairs LIOT / LIOB and LIO_0 <0: 7> are respectively passed to the local amplification unit IOSA0 to be amplified secondly, and the data of the selected memory cells are quasi-global lines BGIO_0 < 0: 7>) at the same time.

4B is a block diagram illustrating arrangement and input / output of unit octets of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 4B, in a semiconductor memory device according to an embodiment of the present invention, one upper bank or lower bank may include first to eighth unit octets OCTET0 to OCTET7, which are eight cell array regions, and a global input / output. The transfer selection unit (GIODRV0 to GIODRV4) is included.

Two small regions, which are one pair of the eighth to eighth unit octets OCTET0 to OCTET7 that are eight cell array regions, are called unit octet pairs. Since the first to eighth unit octets (OCTET0 to OCTET7) are eight, they are arranged in order of OCTET0, OCTET4, OCTET1, OCTET5, OCTET2, OCTET6, OCTET3, and OCTET7.

The unit octet pair may be defined as first to fourth unit octet pairs OCTET0_4, OCTET1_5, OCTET2_6 and OCTET3_7 by binding two adjacent unit octets.

In order to bind two of the first to eighth unit octets OCTET0 to OCTET7 as a pair, a timing difference of two clocks CLK is required when reading or writing data between two unit octets. In the specification of the DDR3 DRAM, a timing difference of two clocks (CLK) exists when data is read or written between two unit octets of each of the first to fourth unit octet pairs OCTET0_4, OCTET1_5, OCTET2_6, and OCTET3_7.

The first to fourth unit octet pairs OCTET0_4, OCTET1_5, OCTET2_6, and OCTET3_7 receive the first to fourth global I / O transfer selection units GIODRV0 to GIODRV4 in response to the first and second global strobe signals GIOSTB03 and GIOSTB47. Through the first to fourth global lines GIO_04 <0: 7>, GIO_15 <0: 7>, GIO_26 <0: 7>, and GIO_37 <0: 7>.

In order to explain the operations of the first to fourth unit octet pairs OCTET0_4, OCTET1_5, OCTET2_6 and OCTET3_7 and the first to fourth global I / O transfer selection units GIODRV0 to GIODRV4, first, the first unit octet pair OCTET0_4 and The first global input / output transfer selection unit GIODRV0 will be representatively described.

First and fifth quasi-global lines BIO_0 <0: 7> and BIO_4 <0: 7> connected to the first and fifth unit octets OCTET0 and OCTET4 included in the first unit octet pair OCTET0_4. Is connected to the first global input / output transfer selection unit GIODRV0, and the first and second global strobe signals GIOSTB03 and GIOSTB47 and the first global line GIO_04 <0: 7> are respectively configured as the first global input / output transfer selection unit. It is connected to (GIODRV0).

When the first global strobe signal GIOSTB03 is activated to a high level, the first global input / output transfer selection unit GIODRV0 switches the quasi-global line BIO_0 <0: 7> of the first unit octet OCTET0 in a switching operation. Is output to the first global line GIO_04 <0: 7>. At this time, the second global strobe signal GIOSTB47 is not activated.

When the second global strobe signal GIOSTB47 is activated to the high level, the first global input / output transfer selection unit GIODRV0 switches to the data of the quasi-global line BIO_4 <0: 7> of the fourth unit octet 4 in the switching operation. Is output to the first global line GIO_04 <0: 7>. At this time, the first global strobe signal GIOSTB03 is not activated.

Now, the overall operation will be described again. When the first global strobe signal GIOSTB03 is activated to a high level, the first, second, third, and fourth global lines GIO_04 <0: 7>, GIO_15 <0: 7>, and GIO_26 are described. Each of <0: 7> and GIO_37 <0: 7> includes first, second, third and fourth semi-global lines BIO_0 <0: 7>, BIO_1 <0: 7>, BIO_2 <0: 7>, When the data of BIO_3 <0: 7> are output and the second global strobe signal GIOSTB47 is activated at a high level, the first, second, third, and fourth global lines GIO_04 <0: 7> and GIO_15 <0 : 7>, GIO_26 <0: 7>, and GIO_37 <0: 7> respectively include fifth, sixth, seventh and eighth semi-global lines BIO_4 <0: 7>, BIO_5 <0: 7>, and BIO_6 <. 0: 7> and BIO_7 <0: 7>) are output.

4C is a timing diagram of data control during a read operation of a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4C, timing of a read operation of the semiconductor memory device according to an exemplary embodiment will be described below.

When the read command Read is input, the column selection control signal CASP_YA is activated at the high level after a predetermined time has elapsed, and at the same time, the input / output sense amplifier strobe signal IOSASTB is activated at the high level.

In response to the activation signal of the column selection control signal CASP_YA and the sense amplifier strobe signal IOSASTB, the data written in the memory cell areas of the first to eighth unit octets OCTET0 to OCTET7 is stored in the local lines LIOT_0 < Semi-global line through 0: 7> ~ LIOT_7 <0: 7>, LIOB_0 <0: 7> ~ LIOB_7 <0: 7>) and local amplifiers (IOSA0 <0: 7> ~ IOSA7 <0: 7>) Are transmitted simultaneously to the fields BIO_0 <0: 7> to BIO_7 <0: 7>.

At this time, when the first global strobe signal GIOSTB03 is activated to a high level, the global lines GIO_04 <0: 7>, GIO_15 <0: 7>, GIO_26 <0: 7>, and GIO_37 <0: 7> Data of the first, second, third, and fourth semi-global lines BIO_0 <0: 7> to BIO_3 <0: 7> are output to the second global strobe signal GIOSTB47 to a high level. In the global lines GIO_04 <0: 7>, GIO_15 <0: 7>, GIO_26 <0: 7>, and GIO_37 <0: 7>, the fifth, sixth, seventh and eighth semi-global lines BIO_4 <0: 7> ~ BIO_7 <0: 7>) are output in order.

The data of the global lines GIO_04 <0: 7>, GIO_15 <0: 7>, GIO_26 <0: 7>, and GIO_37 <0: 7> are in order of activation of the first and second global strobe signals GIOSTB03 and GIOSTB47. Accordingly, data of the first to eighth semi-global lines BIO_0 <0: 7> to BIO_7 <0: 7> are latched, and the first data bundle (data of GIO_0 <0: 7>) to the last data bundle (GIO_7). Up to < 0: 7 &gt;) are output as output signals DQ one by one according to strobe signal DQS.

As described above, the semiconductor memory device according to the present invention does not have a transfer path sharing in the data transfer path from the memory cell region to the quasi-global line so that switching operation is unnecessary, and therefore, an internal operation clock is not required additionally, thereby speeding up the operation. It is possible. In addition, if the prefetch rate is increased to increase bandwidth, the global line, which occupies the largest core victim area, can be shared by switching to effectively reduce the chip area.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. .

10: Bank / Upper Bank, Lower Bank
110/120: memory cell array

Claims (4)

A bank including a first cell array region for outputting first data through a first local line and a second cell array region for outputting second data through a second local line;
A first local amplifier which senses and amplifies the first data of the first local line and transfers the first data to a first semi-global line;
A second local amplifier for sensing and amplifying the second data of the second local line and transferring the second data to a second semi-global line; And
And a transfer selector configured to sequentially transfer the first and second data of the first and second semi-global lines to one global line, from the first cell array region to the first semi-global line. And the second data movement path from the first data movement path and the second cell array region to the second semi-global line does not have a shared movement path.
The method of claim 1,
In the first data movement path from the first cell array region to the first semi-global line, connecting to a memory cell of the first cell array region through a first pair of bit lines and outputting to the first local line A first bit line sense amplifier; And
In the second data movement path from the second cell array region to the second semi-global line, connecting to a memory cell in the second cell array region via a second pair of bit lines and outputting to the second local line Second Bitline Sense Amplifier
Semiconductor memory device further comprising
The method according to claim 1 or 2,
And the first and second cell array regions are unit octets.
The method according to claim 1 or 2,
The first data and the second data is
Each having a same size of 1 bit or more
KR1020120096737A 2012-08-31 2012-08-31 Semiconductor memory apparatus KR20140029977A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190054624A (en) 2017-11-14 2019-05-22 박영경 Seed code transmission method and system for location-based password service using evolved multimedia broadcast multicast services system in a cellular iot network

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190054624A (en) 2017-11-14 2019-05-22 박영경 Seed code transmission method and system for location-based password service using evolved multimedia broadcast multicast services system in a cellular iot network

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