KR20140014709A - On-die termination circuit, semiconductor memory device and memory system including the same - Google Patents

Abstract

An on-die termination circuit which is activated in response to a latency control signal is disclosed. The on-die termination circuit comprises an on-die termination controlling circuit and an on-die termination unit. The on-die termination controlling circuit determines a status of the on-die termination based on a read latency and/or a write latency control signal, and generates an on-die termination control signal. The on-die termination unit is activated or inactivated in response to the on-die termination control signal. Therefore, the power consumption of a semiconductor device is low.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an on-die termination circuit, and a semiconductor memory device and a memory system including the on-

The present invention relates to a semiconductor memory device, and more particularly, to an on-die termination circuit of a semiconductor memory device and a memory system including the same.

A semiconductor memory device transmits and receives data and control signals to and from a memory controller via a bus. The higher the frequency of the signal transmitted between the memory controller and the semiconductor memory device, the more the signal distortion increases.

A termination process is performed using a resistor or the like in order to prevent distortion of a signal transmitted between the memory controller and the semiconductor memory device. When termination is performed, the termination resistance absorbs the reflection of the signal, thereby reducing the distortion of the signal.

It is an object of the present invention to provide an on-die termination circuit capable of reducing power consumption.

Another object of the present invention is to provide a semiconductor memory device including the on-die termination circuit.

It is still another object of the present invention to provide a memory system including the on-die termination circuit.

In order to achieve the above object, an on-die termination circuit according to an embodiment of the present invention includes an on-die termination control circuit and an on-die termination portion.

The on-die termination control circuit determines the on-die termination state based on the read latency control signal RL and generates an on-die termination control signal. The on-die termination portion is activated or deactivated in response to the on-die termination control signal.

According to one embodiment of the present invention, the on-die termination circuit can compensate the impedance of the data bus of the memory system.

According to one embodiment of the present invention, the on-die termination circuit can compensate the impedance of the command / address bus of the memory system.

According to one embodiment of the present invention, the on-die termination control circuit may generate the read latency control signal RL based on a CAS (Column Address Strobe) latency signal and an internal clock signal.

According to one embodiment of the present invention, the on-die termination circuit may further include a pad electrically connected to the external bus, the internal bus, and the on-die termination unit.

According to one embodiment of the present invention, the external bus may be a command / address (C / A) bus.

According to one embodiment of the present invention, the external bus may be a data (DQ) bus.

According to one embodiment of the present invention, the on-die termination portion may include a MOS transistor and a termination resistor.

The MOS transistor is turned on / off in response to the on-die termination control signal, and a termination resistor can be connected between the MOS transistor and the pad.

An on-die termination circuit according to another embodiment of the present invention includes an on-die termination control circuit and an on-die termination portion.

The on-die termination control circuit determines the on-die termination state based on the write latency control signal WL and generates an on-die termination control signal. The on-die termination portion is activated or deactivated in response to the on-die termination control signal.

According to one embodiment of the present invention, the on-die termination control circuit may generate the write latency control signal (WL) based on a CAS (Column Address Strobe) latency signal and an internal clock signal.

According to one embodiment of the present invention, the on-die termination control circuit may generate the on-die termination control signal based on the write latency control signal WL and the read latency control signal RL.

An on-die termination circuit according to another embodiment of the present invention includes an on-die termination control circuit and an on-die termination portion.

The on-die termination control circuit generates an on-die termination control signal based on the read latency control signal RL and the on-die termination status signal. The on-die termination portion is activated or deactivated in response to the on-die termination control signal.

According to one embodiment of the present invention, the on-die termination control circuit may receive the latency control signal and the on-die termination status signal from a mode register write (MRW) register.

According to one embodiment of the present invention, the values of the latency control signal and the on-termination state signal stored in the mode register write (MRW) register may be updated by the user.

According to one embodiment of the present invention, the on-die termination control circuit may generate the on-die termination control signal based on the read latency control signal, the on-die termination status signal, and the write latency control signal (WL).

A semiconductor memory device according to one embodiment of the present invention includes a latency control circuit and an on-die termination circuit.

The latency control circuit generates a read latency control signal RL based on a CAS (Column Address Strobe) latency signal and an internal clock signal. The on-die termination circuit determines an on-die termination state based on the read latency control signal RL to generate an on-die termination control signal and is activated or deactivated in response to the on-die termination control signal.

According to one embodiment of the present invention, the latency control circuit generates a read information signal delayed by delaying a read information signal in response to the CAS latency signal and the internal clock signal, It is possible to generate a read latency control signal based on the information signal.

According to one embodiment of the present invention, the on-die termination circuit may generate the on-die termination control signal based on the read latency control signal RL and the write latency control signal WL.

According to one embodiment of the present invention, the semiconductor memory device may be a laminated memory device in which a plurality of semiconductor layers for transmitting and receiving data and control signals through a through-silicon-via (TSV) are stacked.

A memory system according to one embodiment of the present invention includes a memory controller and a memory module for generating a command / address signal (C / A) and a data signal. The memory module includes a plurality of semiconductor memory devices, each of the semiconductor memory devices operating in response to the command / address signal and the data signal, and including an on termination circuit. The on-die termination circuit includes an on-die termination control circuit and an on-die termination portion. The on-die termination control circuit determines an on-die termination state based on the read latency control signal RL and generates an on-die termination control signal. The on-die termination portion is activated or deactivated in response to the on-die termination control signal.

An on-die termination circuit according to embodiments of the present invention activates or deactivates a termination resistor based on a read latency control signal and / or a write latency control signal. Therefore, the semiconductor memory device and the system including the on-die termination circuit according to the embodiments of the present invention are low in power consumption.

1 is a circuit diagram showing an on-die termination circuit according to one embodiment of the present invention.
2 is a circuit diagram showing an on-die termination circuit according to another embodiment of the present invention.
3 is a circuit diagram showing an on-die termination circuit according to another embodiment of the present invention.
4 is a circuit diagram showing an on-die termination circuit according to another embodiment of the present invention.
FIG. 5 is a table showing a read latency control signal, a write latency control signal, and an on-die termination state used in the on-die termination circuit of FIG.
6 is a block diagram illustrating an example of a semiconductor memory device including on die termination circuitry in accordance with embodiments of the present invention.
7 is a block diagram showing another example of a semiconductor memory device including an on-die termination circuit according to embodiments of the present invention.
8 is a block diagram illustrating another example of a semiconductor memory device including an on-die termination circuit according to embodiments of the present invention.
9 is a block diagram illustrating another example of a semiconductor memory device including an on-die termination circuit according to embodiments of the present invention.
10 is a block diagram illustrating a memory system in accordance with one embodiment of the present invention.
11 is a block diagram illustrating a memory system in accordance with another embodiment of the present invention.
12 to 14 are views showing a memory module including a semiconductor memory device according to embodiments of the present invention.
15 is a simplified perspective view showing a semiconductor device of a stacked structure including a semiconductor memory device according to embodiments of the present invention.
16 is a block diagram showing an example of a memory system including a semiconductor memory device and an optical connection device according to an embodiment of the present invention.
17 is a block diagram showing another example of the information processing system including the semiconductor memory device according to the embodiments of the present invention.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, And should not be construed as limited to the embodiments described in the foregoing description.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprising ", or" having ", and the like, are intended to specify the presence of stated features, integers, But do not preclude the presence or addition of steps, operations, elements, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

On the other hand, if an embodiment is otherwise feasible, the functions or operations specified in a particular block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be performed at substantially the same time, and depending on the associated function or operation, the blocks may be performed backwards.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a circuit diagram showing an on-die termination circuit 100 according to one embodiment of the present invention.

Referring to FIG. 1, the on-die termination circuit 100 may include an on-die termination control circuit 110 and an on-termination section 120.

The on-die termination control circuit 110 determines the on-die termination state (ODT STATUS) based on the read latency control signal RL and generates the on-die termination control signal CON_ODT. The on-die termination part 120 is activated or deactivated in response to the on-die termination control signal CON_ODT. As will be described later, the read latency control signal RL may be generated based on a CAS (Column Address Strobe) latency signal and a read information signal.

The on die termination circuit 100 may further include a pad 130 electrically connected to the external bus BUS_EXT, the internal bus BUS_INT, and the on die termination portion 120. The external bus BUS_EXT may be a command / address (C / A) bus or a data (DQ) bus.

The on die termination part 120 may include a PMOS transistor MP1 and a termination resistor RTT. The PMOS transistor MP1 is turned on / off in response to the on-die termination control signal CON_ODT and the termination resistor RTT can be connected between the PMOS transistor MP1 and the pad 130.

The on-die termination circuit 100 can compensate the impedance of the data bus of the memory system including the semiconductor memory device. Also, the on-die termination circuit 100 can compensate the impedance of the command / address bus of the memory system including the semiconductor memory device.

2 is a circuit diagram showing an on-die termination circuit 200 according to another embodiment of the present invention.

2, the on-die termination circuit 200 may include an on-die termination control circuit 210 and an on-

The on-die termination control circuit 210 determines an on-die termination state (ODT STATUS) based on a write latency control signal WL and generates an on-termination control signal CON_ODT. The on-die termination part 120 is activated or deactivated in response to the on-die termination control signal CON_ODT. As will be described later, the write latency control signal WL can be generated based on the CAS latency signal and the write information signal.

The on-die termination circuit 200 can compensate the impedance of the data bus of the memory system including the semiconductor memory device. The on die termination circuit 200 may also compensate the impedance of the command / address bus of the memory system including the semiconductor memory device.

3 is a circuit diagram illustrating an on die termination circuit 3000 according to another embodiment of the present invention.

3, the on termination circuit 300 may include an on termination control circuit 310 and an on termination portion 120. [

The on-die termination control circuit 210 determines an on-die termination state (ODT STATUS) based on a read latency control signal RL and a write latency control signal WL and outputs an on-termination control signal CON_ODT Occurs. The on-die termination part 120 is activated or deactivated in response to the on-die termination control signal CON_ODT. As will be described later, the read latency control signal RL may be generated based on a CAS latency signal and a read information signal, the write latency control signal WL may be generated based on a CAS latency signal, May be generated based on the information signal.

The on-die termination circuit 300 can compensate the impedance of the data bus of the memory system including the semiconductor memory device. The on die termination circuit 300 may also compensate for the impedance of the command / address bus of the memory system including the semiconductor memory device.

4 is a circuit diagram showing an on die termination circuit 400 according to another embodiment of the present invention.

4, the on-die termination circuit 400 may include an on-die termination control circuit 410 and an on-termination section 120. [

The on-die termination control circuit 410 generates an on-die termination control signal CON_ODT based on the read latency control signal RL, the write latency control signal WL, and the on-die termination state signal ODT STATUS. The on-die termination part 120 is activated or deactivated in response to the on-die termination control signal CON_ODT. As will be described later, the read latency control signal RL may be generated based on a CAS latency signal and a read information signal, the write latency control signal WL may be generated based on a CAS latency signal, May be generated based on the information signal.

The on-die termination circuit 400 may compensate the impedance of the data bus of the memory system including the semiconductor memory device. Also, the on-die termination circuit 400 may compensate the impedance of the command / address bus of the memory system including the semiconductor memory device.

The on die termination control circuit 410 outputs a read latency control signal RL, a write latency control signal WL and an on-die termination state signal (" ODT STATUS). In addition, the values of the latency control signal and the on-termination state signal stored in the mode register write (MRW) register may be updated by the user.

FIG. 5 is a table showing a read latency control signal, a write latency control signal, and an on-die termination state that can be used in the on-die termination circuit of FIG.

Referring to FIG. 5, in one example, the on-die termination state signal OPX has a value of 1 when the values of RL and WL are 12 and 6, respectively. At this time, the on termination circuit 400 of FIG. . In another example, when the value of RL / WL is 12/6 or 11/6, the on-die termination state signal OPX has a value of 1, at which time the on termination circuit 400 of Fig. 4 can be activated .

Figure 6 is a block diagram illustrating one example of a semiconductor memory device 1000 including on die termination circuitry in accordance with embodiments of the present invention.

6, the semiconductor memory device 1000 includes a memory cell array 1110, a row decoder 1120, a column decoder 1130, an address buffer 1140, an output buffer 1150, a clock synchronization circuit 1160, A read command circuit 1170, a mode register 1180, a latency control circuit 1190, an on-die termination circuit 1010, and a pad 1020.

The clock synchronization circuit 1160 may include a variable delay circuit 1162, a phase detector 1164, and a replica output buffer 1166 as a delay-locked loop (DLL) circuit. The read command circuit 1170 may include an internal clock generator 1172 and a read command buffer 1174. The variable delay 1162 can be reset by the reset signal RESET.

Data (DATA) is written in the memory cell array 1110, read out from the memory cell array 1110, and output to the outside. When the read command (READ CMD) is applied to the semiconductor memory device 1000, the data (DATA) is read from the memory cell array 1110 in accordance with the address (ADD) received from the outside. The address buffer 1140 temporarily stores the address ADD received from the outside. The row decoder 1120 receives and decodes the address from the address buffer 1140 and generates a row address. The column decoder 1130 receives and decodes the address from the address buffer 1140 and generates the column address. The memory cell array 1110 outputs the data of the memory cell designated by the row address and the column address. The output buffer 1150 receives the data output from the memory cell array 1110 and outputs the received data in response to a read latency control signal RL and an output clock signal CLKDQ output from the latency control circuit 1190 do.

The clock synchronous circuit 1160 generates the output clock signal CLKDQ in response to the external clock signal ECLK. The external clock signal ECLK is used as a reference clock signal for most instructions of the semiconductor memory device 1000. [ That is, most of the commands are applied to the semiconductor memory device 1000 in synchronization with the external clock signal ECLK.

The clock synchronous circuit 1160 generates an output clock signal CLKDQ that is phase-ahead relative to the external clock signal ECLK. That is, although the output clock signal CLKDQ has the same frequency as the external clock signal ECLK, the pulses of the output clock signal CLKDQ are phase shifted by the data output time tSAC from the pulses of the external clock signal ECLK Ahead. Accordingly, the clock synchronization circuit 1160 causes the data DOUT output from the output buffer 1150 to be synchronized with the external clock signal ECLK.

The read command circuit 1170 generates the internal clock signal PCLK and the readout information signal PREAD based on the read command READ CMD and the external clock signal ECLK. The internal clock signal PCLK is generated based on the external clock signal ECLK and the read command buffer 1174 is read out based on the internal clock signal PCLK and the read command READ CMD And generates an information signal PREAD. The internal clock generator 1172 can be reset by the reset signal RESET.

The latency circuit 1190 receives the cache latency CL from the mode register 1180 and generates a read latency control signal RL that causes the output buffer 1150 to output the data at an appropriate time. The output buffer 1150 outputs the data in response to the output clock signal CLKDQ while the read latency control signal RL is enabled.

The latency circuit 1190 generates a read information signal delayed by delaying the read information signal in response to a CAS (Column Address Strobe) latency signal and an internal clock signal, and generates a read latency control signal RL).

The on-die termination circuit 1010 determines an on-die termination state based on the read-out latency control signal RL, generates an on-termination control signal, and activates or deactivates the on-termination section in response to the on-die termination control signal. The on termination circuit 1010 can be connected to the pad 1020 electrically connected to the external bus BUS_EXT and the internal bus BUS_INT.

The semiconductor memory device 1000 shown in FIG. 6 may be a volatile memory chip such as a dynamic random access memory (DRAM) and a static random access memory (SRAM), a flash memory, a phase change memory a non-volatile memory chip such as a phase change memory, a magnetic random access memory (MRAM), or a resistive random access memory (RRAM), or a combination thereof.

7 is a block diagram illustrating another example of a semiconductor memory device 2000 including an on die termination circuit according to embodiments of the present invention.

7, the semiconductor memory device 2000 includes a memory cell array 1110, a row decoder 1120, a column decoder 1130, an address buffer 1140, an input buffer 2150, a clock synchronization circuit 1160, A write command circuit 2170, a mode register 1180, a latency control circuit 2190, an on-die termination circuit 2010, and a pad 2020.

The clock synchronization circuit 1160 may include a variable delay circuit 1162, a phase detector 1164, and a replica output buffer 1166 as a delay-locked loop (DLL) circuit. The write command circuit 2170 may include an internal clock generator 2172 and a write command buffer 2174. The variable delay 1162 can be reset by the reset signal RESET.

Data (DATA) is written in the memory cell array 1110, read out from the memory cell array 1110, and output to the outside. When the write command WRITE CMD is applied to the semiconductor memory device 3000, the data DATA_IN is stored in the memory cell array 1110 according to the address ADD received from the outside. The address buffer 1140 temporarily stores the address ADD received from the outside. The row decoder 1120 receives and decodes the address from the address buffer 1140 and generates a row address. The column decoder 1130 receives and decodes the address from the address buffer 1140 and generates the column address. The memory cell array 1110 inputs data to the memory cell specified by the row address and the column address. The input buffer 2150 inputs data (DATA) received from the outside to the memory cell array 1110 in response to a write latency control signal (WL) output from the latency control circuit 2190.

The clock synchronous circuit 1160 generates the output clock signal CLKDQ in response to the external clock signal ECLK. The external clock signal ECLK is used as a reference clock signal for most instructions of the semiconductor memory device 1000. [ That is, most of the commands are applied to the semiconductor memory device 1000 in synchronization with the external clock signal ECLK.

The clock synchronous circuit 1160 generates an output clock signal CLKDQ that is phase-ahead relative to the external clock signal ECLK. That is, although the output clock signal CLKDQ has the same frequency as the external clock signal ECLK, the pulses of the output clock signal CLKDQ are phase shifted by the data output time tSAC from the pulses of the external clock signal ECLK Ahead.

The write command circuit 2170 generates the internal clock signal PCLK and the write information signal PWR based on the write command WRITE CMD and the external clock signal ECLK. The internal clock generator 2172 generates the internal clock signal PCLK based on the external clock signal ECLK and the write command buffer 2174 writes the internal clock signal PCLK based on the internal clock signal PCLK and the write command WRITE CMD And generates an information signal PWR. The internal clock generator 2172 can be reset by the reset signal RESET.

The latency circuit 2190 receives the cache latency CL from the mode register 1180 and generates a write latency control signal WL that causes the input buffer 2150 to output data at an appropriate time. The input buffer 2150 inputs data while the write latency control signal WL is enabled.

The on-die termination circuit 2010 determines an on-die termination state based on the write-latency control signal WL, generates an on-die termination control signal, and activates or deactivates the on-die termination section in response to the on-die termination control signal. The on die termination circuit 2010 may be connected to the pad 2020 electrically connected to the external bus BUS_EXT and the internal bus BUS_INT.

8 is a block diagram illustrating another example of a semiconductor memory device 3000 including an on-die termination circuit according to embodiments of the present invention.

8, the semiconductor memory device 3000 includes a memory cell array 1110, a row decoder 1120, a column decoder 1130, an address buffer 1140, an output buffer 1150, an input buffer 2150, A clock synchronous circuit 1160, a command circuit 3170, a mode register 1180, a latency control circuit 3190, an on-die termination circuit 3010 and a pad 3020.

The clock synchronization circuit 1160 may include a variable delay circuit 1162, a phase detector 1164, and a replica output buffer 1166 as a delay-locked loop (DLL) circuit. The write command circuit 2170 may include an internal clock generator 2172 and a write command buffer 2174. The variable delay 1162 can be reset by the reset signal RESET.

Data (DATA) is written in the memory cell array 1110, read out from the memory cell array 1110, and output to the outside. When the read command (READ CMD) is applied to the semiconductor memory device 1000, the data (DATA_OUT) is read from the memory cell array 1110 in accordance with the address (ADD) received from the outside. When the write command WRITE CMD is applied to the semiconductor memory device 3000, the data DATA_IN is stored in the memory cell array 1110 according to the address ADD received from the outside. The address buffer 1140 temporarily stores the address ADD received from the outside. The row decoder 1120 receives and decodes the address from the address buffer 1140 and generates a row address. The column decoder 1130 receives and decodes the address from the address buffer 1140 and generates the column address. The memory cell array 1110 outputs data of the memory cell specified by the row address and the column address, or inputs data into the memory cell specified by the row address and the column address. The output buffer 1150 receives the data output from the memory cell array 1110 and outputs the received data in response to the read latency control signal RL and the output clock signal CLKDQ output from the latency control circuit 3190 do. The input buffer 3030 inputs data (DATA_IN) received from the outside to the memory cell array 1110 in response to the write latency control signal (WL) output from the latency control circuit 3190.

The clock synchronous circuit 1160 generates the output clock signal CLKDQ in response to the external clock signal ECLK. The external clock signal ECLK is used as a reference clock signal for most instructions of the semiconductor memory device 1000. [ That is, most of the commands are applied to the semiconductor memory device 1000 in synchronization with the external clock signal ECLK.

The clock synchronous circuit 1160 generates an output clock signal CLKDQ that is phase-ahead relative to the external clock signal ECLK. That is, although the output clock signal CLKDQ has the same frequency as the external clock signal ECLK, the pulses of the output clock signal CLKDQ are phase shifted by the data output time tSAC from the pulses of the external clock signal ECLK Ahead. Accordingly, the clock synchronization circuit 1160 causes the data DOUT output from the output buffer 1150 to be synchronized with the external clock signal ECLK.

The command circuit 3170 outputs the internal clock signal PCLK, the read information signal PREAD and the write information signal PWR on the basis of the read command (READ CMD), the write command (WRITE CMD) and the external clock signal ECLK Occurs. The internal clock signal PCLK is generated based on the external clock signal ECLK and the read command buffer 3174 is read out based on the internal clock signal PCLK and the read command READ CMD And generates the information signal PREAD and the write command buffer 3176 generates the write information signal PWR based on the internal clock signal PCLK and the write command WRITE CMD. The internal clock generator 3172 can be reset by the reset signal RESET.

The latency circuit 3190 receives the cache latency CL from the mode register 1180 and generates the read latency control signal RL and the write latency control signal WL. The output buffer 1150 outputs the data in response to the output clock signal CLKDQ while the read latency control signal RL is enabled. The input buffer 3030 inputs data while the write latency control signal WL is enabled.

The latency circuit 3190 generates a read information signal delayed by delaying the read information signal in response to a CAS latency signal and an internal clock signal and generates a read latency control signal RL based on the delayed read information signal . The latency circuit 3190 generates a delayed write information signal by delaying the write information signal in response to the CAS latency signal and the internal clock signal and generates a write latency control signal WL based on the delayed write information signal. Lt; / RTI >

The on-die termination circuit 3010 determines an on-die termination state based on the write-latency control signal WL, generates an on-die termination control signal, and activates or deactivates the on-die termination portion in response to the on-die termination control signal. The on termination circuit 3010 may be connected to the pad 3020 electrically connected to the external bus BUS_EXT and the internal bus BUS_INT.

9 is a block diagram illustrating another example of a semiconductor memory device including an on die termination circuit 4000 according to embodiments of the present invention.

9, the semiconductor memory device 3000 includes a memory cell array 1110, a row decoder 1120, a column decoder 1130, an address buffer 1140, an output buffer 1150, an input buffer 2150, And includes a clock synchronous circuit 1160, a command circuit 3170, a mode register 1180, a latency control circuit 3190, an on-die termination circuit 4010, a mode register write (MRW) register 4040 and a pad 3020 can do.

The on-die termination circuit 4010 generates an on-die termination control signal CON_ODT based on the read latency control signal RL, the write latency control signal WL, and the on-die termination state signal ODT STATUS, Activates or deactivates the on-die termination in response to a signal. The on termination circuit 4010 may be connected to a pad 3020 electrically connected to the external bus BUS_EXT and the internal bus BUS_INT.

The on die termination circuit 4010 can receive the read latency control signal RL, the write latency control signal WL and the on-die termination status signal (ODT STATUS) from a register called a mode register write (MRW). The values of the read latency control signal RL, the write latency control signal WL and the on-termination status signal stored in the mode register write (MRW) register may be updated by the user.

10 is a block diagram illustrating a memory system 5100 in accordance with one embodiment of the present invention.

10, the memory system 5100 includes a memory controller 5110 and a memory module 5120.

The memory controller 5110 generates the command / address signal C / A and the data signal DQ. The memory module 5120 operates in response to the command / address signal C / A, the data signal DQ and the termination resistance control signal RTC. A plurality of semiconductor memory devices 5121, 5122, 5123, 5124, 5122, 5124, 5126, 5128, or 5129 for the command / address bus 1201 through which a command / address signal (C / A) 5122, 5123, and 5124 are mounted. The command / address signal C / A may be packet data in which the command signal and the address signal are combined in a packet form.

Although FIG. 10 illustrates a memory module 5120 having four semiconductor memory devices, the memory module 5120 may include two or more semiconductor memory devices. In addition, semiconductor memory devices may be mounted on both sides of the substrate of the memory module 5120.

The data signal DQ is transmitted and received between the memory controller 5110 and the semiconductor memory devices 5121, 5122, 5123 and 5124 constituting the memory module 5120 via the data bus 5103. [

The command / address bus 5101 has a fly-by structure and electrically connects the semiconductor memory devices 5121, 5122, 5123, and 5124 to each other. In addition, the termination circuits 5125, 5126, 5128, or 5129 included in each of the semiconductor memory devices 5121, 5122, 5123, and 5124 are coupled between the command / address bus 5101 and the termination voltage VTT , The terminal resistance value of the command / address bus 5101 is changed.

11 is a block diagram illustrating a memory system 5200 in accordance with another embodiment of the present invention.

11, the memory system 5200 includes a memory controller 5210 and a memory module 5220. [

The memory controller 5210 generates the command / address signal C / A, the data signal DQ and the terminal resistance control signal RTC. The memory module 5220 operates in response to the command / address signal C / A, the data signal DQ, and the termination resistance control signal RTC. A plurality of semiconductor memory devices 5221, 5221, 5221, 5221, 5231 having a termination circuit 5225, 5227, 5229, 5231 for a command / address bus 5201 through which a command / address signal (C / A) 5222, 5223 and 5224 are mounted. The command / address signal C / A may be packet data in which the command signal and the address signal are combined in a packet form. In addition, semiconductor memory devices 5221, 5222, 5223 and 5224 include termination circuits 5226, 5228, 5230 and 5232 for data bus 5203 to which data signals DQ are transferred.

Although FIG. 11 illustrates a memory module 5200 having four semiconductor memory devices, the memory module 5220 may include two or more semiconductor memory devices. In addition, semiconductor memory devices may be mounted on both sides of the substrate of the memory module 5220.

The data signal DQ is transmitted and received between the semiconductor memory devices 5221, 5222, 5223 and 5224 constituting the memory controller 5220 and the memory controller 5220 via the data bus 5203. [

The command / address bus 1201 has a fly-by structure and electrically connects the semiconductor memory devices 5221, 5222, 5223, and 5224 to each other. Termination circuits 5225, 5227, 5229 and 5231 included in each of the semiconductor memory devices 5221, 5222, 5223 and 5224 are coupled between the command / address bus 5201 and the first termination voltage VTT1 , The terminal resistance value of the command / address bus 1201 is changed. In addition, the termination circuits 5226, 5228, 5230, and 5232 included in each of the semiconductor memory devices 5221, 5222, 5223, and 5224 are coupled between the data bus 5203 and the second terminal voltage VTT2 , The terminal resistance value of the data bus 5203 is changed.

The first termination voltage VTT1 is provided to the termination circuits 5225, 5227, 5229 and 5231 and the second termination voltage VTT2 is provided to the termination circuits 5226, 5228, 5230 and 5232. [

12 to 15 are views showing a memory module including a semiconductor memory device according to embodiments of the present invention.

12, the memory module 5300 includes a printed circuit board 5310, a plurality of semiconductor memory devices 5320, and a connector 5330. The plurality of semiconductor memory devices 5320 can be coupled to the upper surface and the lower surface of the printed circuit board 5310. The connector 5330 is electrically connected to a plurality of semiconductor memory devices 5320 through conductive lines (not shown). Also, the connector 5330 may be connected to a slot of the external host.

13, memory module 5400 includes a printed circuit board 5410, a plurality of semiconductor memory devices 5420, a connector 5430, and a plurality of buffers 5440. A plurality of buffers 5440 may be disposed between semiconductor memory device 5420 and connector 5430, respectively.

A plurality of semiconductor memory devices 5420 and buffers 5440 may be provided on the upper and lower surfaces of the printed circuit board 5410. Semiconductor memory devices 5420 and buffers 5440 formed on the top and bottom surfaces of the printed circuit board 5410 may be connected through a plurality of via holes.

14, a memory module 5500 includes a printed circuit board 5510, a plurality of semiconductor memory devices 5520, a connector 5530, a plurality of buffers 5540, and a controller 5550.

Semiconductor memory devices 5420 and buffers 5540 may be provided on the top and bottom surfaces of the printed circuit board 5510. Semiconductor memory devices 5420 and buffers 5540 formed on the top and bottom surfaces of the printed circuit board 5510 may be connected through a plurality of via-holes.

15 is a schematic view showing a semiconductor device 5600 having a laminated structure including a plurality of semiconductor layers. Each of the semiconductor memory devices in the module structures of FIGS. 12 to 14 may have a plurality of semiconductor layers LA1 to LAn.

 A plurality of semiconductor layers LA1 to LAn in a stacked structure in the semiconductor device 5600 of a stacked structure can be interconnected through a through silicon via (TSV)

16 is a block diagram illustrating one example of a memory system 5700 including a magnetoresistive memory device and an optical coupling device in accordance with an embodiment of the present invention.

 16, a memory system 5700 includes a plurality of optical link devices (Optical Link) 5710a and 5710a interconnecting a controller 5720, a semiconductor memory device 5730 and a controller 5720 and a semiconductor memory device 5730, 5710b. The controller 5720 includes a control unit 5721. A first transmitting unit 5722, and a first receiving unit 5723. The control unit 5721 transmits the control signal SN1 to the first transmitting unit 5722. [

The first transmission unit 5722 may include a first optical modulator 5722_1 and the first optical modulator 5722-1 may convert the control signal SN1 as an electrical signal into a first tube transmission signal OTP1 And transmits it to the optical connection device 5710a.

The first receiver 5723 may include a first optical demodulator 5723_1 and the first optical demodulator 5723_1 may receive the second optical reception signal OPT2 'received from the optical coupler 5710b as an electrical signal Converts it into a data signal SN2 and transmits it to the control unit 5721. [

The semiconductor memory device 5730 includes a second receiving portion 5731, a memory cell array 5732, and a second transmitting portion 5733. The second receiver 5731 may include a second optical demodulator 5733_1 and the second optical demodulator 5731_1 may receive the first optical signal OPT 'from the optical coupler 5710A as a control signal (SN1) and transfers it to the memory cell array 4732.

The memory cell array 5732 writes data under control of the control signal SN1 or transfers the data signal SN2 output from the memory cell array 5732 to the second transmission unit 5733. [

The second transmission unit 5733 may include a second optical modulator 5733_1 and the second optical modulator 5733_1 may convert the data signal SN2 as an electrical signal into a second optical data signal OPT2, Device 5710b.

17 is a block diagram showing another example of the information processing system including the semiconductor memory device according to the embodiments of the present invention.

Referring to FIG. 17, a semiconductor memory device 5810 may be mounted in a computer system 5800 such as a mobile device or a desktop computer. The computer system 5800 may include a semiconductor memory device 5810, a central processing unit 5850 and a user interface 5830, which are electrically coupled to the system bus 5860.

The present invention is applicable to a semiconductor device and a system including the semiconductor device.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

100, 200, 300, 400; On-die termination circuit
1000, 2000, 3000, 4000: semiconductor memory device
5100, 5200: Memory system
5300, 5400, 5500: memory module
5600: Laminated semiconductor device
5700: Memory system
5800: Information processing system

Claims (20)

An on-die termination control circuit for determining an on-die termination state based on a read latency control signal RL and generating an on-die termination control signal; And
And an on-termination circuit that is activated or deactivated in response to the on-die termination control signal. The on-die termination circuit according to claim 1, wherein the on-
Wherein the impedance of the data bus of the memory system is compensated. The on-die termination circuit according to claim 1, wherein the on-
Wherein the impedance of the command / address bus of the memory system is compensated. The on-die termination control circuit according to claim 1,
Wherein the read latency control signal (RL) is generated based on a CAS (Column Address Strobe) latency signal and an internal clock signal. The on-die termination control circuit according to claim 1,
And the on-die termination control signal is generated based on the read latency control signal (RL) and the write latency control signal (WL). The on-die termination circuit according to claim 1, wherein the on-
Further comprising an external bus, an internal bus, and a pad electrically connected to the on termination portion. The method according to claim 6,
Wherein the external bus is a command / address (C / A) bus. The method according to claim 6,
Wherein the external bus is a data (DQ) bus. 7. The apparatus of claim 6, wherein the on-
A MOS transistor for on / off operation in response to the on-die termination control signal; And
And a termination resistor coupled between the MOS transistor and the pad. An on-die termination control circuit for determining an on-die termination state based on a write latency control signal (WL) and generating an on-die termination control signal; And
And an on-termination circuit that is activated or deactivated in response to the on-die termination control signal. 11. The method of claim 10, wherein the on die termination circuit
Wherein the impedance of the data bus of the memory system is compensated. 11. The method of claim 10, wherein the on die termination circuit
Wherein the impedance of the command / address bus of the memory system is compensated. 11. The on-die termination control circuit according to claim 10, wherein the on-
Wherein said write latency control signal (WL) is generated based on a CAS (Column Address Strobe) latency signal and an internal clock signal. 11. The on-die termination control circuit according to claim 10, wherein the on-
And the on-die termination control signal is generated based on the write latency control signal (WL) and the read latency control signal (RL). An on-die termination control circuit for generating an on-die termination control signal based on a read latency control signal RL and an on-die termination state signal; And
And an on-termination circuit that is activated or deactivated in response to the on-die termination control signal. 16. The on-die termination control circuit according to claim 15,
And receives the latency control signal and the on-die termination status signal from a mode register write (MRW) register. 17. The method of claim 16,
Wherein the value of the latency control signal and the on-termination status signal stored in the mode register write (MRW) register can be updated by a user. 16. The on-die termination control circuit according to claim 15,
And the on-die termination control signal is generated based on the read latency control signal (RL), the on-die termination status signal, and the write latency control signal (WL). A latency control circuit for generating a read latency control signal (RL) based on a column address strobe (CAS) latency signal and an internal clock signal; And
And an on termination circuit that determines an on-die termination state based on the read latency control signal (RL) to generate an on-die termination control signal and is activated or deactivated in response to the on-die termination control signal. A memory controller for generating a command / address signal (C / A) and a data signal; And
And a memory module having a plurality of semiconductor memory devices operating in response to the command / address signal and the data signal and having an on termination circuit,
The on-die termination circuit
An on-die termination control circuit for determining an on-die termination state based on the read latency control signal (RL) and generating an on-die termination control signal; And
And an on-termination unit that is activated or deactivated in response to the on-die termination control signal.

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