KR20140013160A - Integrated circuit - Google Patents

Integrated circuit Download PDF

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Publication number
KR20140013160A
KR20140013160A KR1020120078804A KR20120078804A KR20140013160A KR 20140013160 A KR20140013160 A KR 20140013160A KR 1020120078804 A KR1020120078804 A KR 1020120078804A KR 20120078804 A KR20120078804 A KR 20120078804A KR 20140013160 A KR20140013160 A KR 20140013160A
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KR
South Korea
Prior art keywords
data
data transmission
pattern
transmission lines
transmission line
Prior art date
Application number
KR1020120078804A
Other languages
Korean (ko)
Inventor
박낙규
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020120078804A priority Critical patent/KR20140013160A/en
Publication of KR20140013160A publication Critical patent/KR20140013160A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers

Abstract

The present invention relates to an integrated circuit which transmits data. The provided integrated circuit includes an even data transmission line group which is formed by grouping a plurality of odd data transmission lines with a preset number, an odd data transmission line group which is formed by grouping a plurality of even data transmission lines with a preset number, a pattern detecting unit which detects the data pattern of the data transmitted through the even data transmission lines and the odd even data transmission lines and outputs the data pattern as a detection signal, and a data converting unit which converts the data of one data transmission line among the data transmission lines to which the data of the data pattern is transmitted, in response to the detection signal.

Description

[0001] INTEGRATED CIRCUIT [0002]

TECHNICAL FIELD The present invention relates to semiconductor design technology, and more particularly, to an integrated circuit for transferring data.

In general, a plurality of data transmission lines for transferring data are provided in a semiconductor memory device including DDR SDRAM (Double Data Rate Synchronous DRAM). As semiconductor memory devices are increasingly integrated these days, the spacing between these data transmission lines is becoming narrower, thereby increasing the coupling between signals transmitted through the data transmission lines. The coupling phenomenon is a factor that hinders signal transmission characteristics. For example, a coupling phenomenon occurs when a logic level value is '010' or '101' in a plurality of data transmission lines.

FIG. 1 is a diagram for explaining a conventional data transmission line, and has an example of a semiconductor memory device having 16 data pads (not shown) and having a bus length of four.

1 shows 64 data transmission lines DQ0_EV0, DQ0_OD0, DQ0_EV1, DQ0_OD1, ..., DQ15_EV0, and DQ15_OD0 alternately corresponding to 16 data pads, each of which has two odd data transfer lines and two even data transfer lines. , DQ15_EV1, DQ15_OD1) are shown. 1 illustrates a case in which no shielding line is disposed, in which case a coupling phenomenon occurs severely according to data transmitted through a plurality of data transmission lines.

FIG. 2 is a diagram illustrating a case where a shielding line is inserted into the data transmission line of FIG. 1.

Referring to FIG. 2, 64 data transmission lines DQ0_EV0, DQ0_OD0, DQ0_EV1, DQ0_OD1, ..., DQ15_EV0, DQ15_OD0, DQ15_EV1, and DQ15_OD1 are grouped by two, and a shielding line (SHL) is interposed between the grouped data transmission lines. ) Is inserted. In this case, it is possible to fundamentally prevent the coupling phenomenon between the data transmission lines. However, as can be seen in the figure, the number of shielding lines SHL is so large that the net die loss is very large.

In recent years, in the situation where semiconductor memory devices have been integrated and miniaturized, a method for solving the above problems is required.

The present invention is to provide an integrated circuit that can prevent the coupling phenomenon without the addition of a shielding line.

According to an aspect of the present invention, an integrated circuit includes: an even data transmission line group in which a plurality of odd data transmission lines are grouped into a predetermined number; An odd data transmission line group in which a plurality of even data transmission lines are grouped into a predetermined number; A pattern detector for detecting a data pattern of data transmitted through the plurality of odd data transmission lines and the plurality of even data transmission lines and outputting the detected data pattern as a detection signal; And a data converter for converting data of one data transmission line from among the plurality of data transmission lines through which the data of the data pattern is transmitted in response to the detection signal.

According to another aspect of the invention, an integrated circuit comprises at least four data transfer lines for transferring data; A plurality of pattern detectors for detecting a data pattern of data transmitted through a data generation line for coupling occurrence among the data transmission lines and outputting a plurality of detection signals; And a plurality of data converters for converting data of one data transmission line of the coupling generation target data transmission line in response to the plurality of detection signals.

According to another aspect of the invention, the integrated circuit is disposed at regular intervals, the first to fourth data transmission line for transferring the first to fourth data respectively; A first pattern detector for detecting a data pattern of the first to third data and outputting the first pattern as a first detection signal; A second pattern detector for detecting a data pattern of the second to fourth data and outputting the second pattern as a second detection signal; A first data converter for converting the first data in response to the first detection signal and transferring the first data to the first data transmission line; And a second data converter for converting the fourth data in response to the second detection signal and transferring the fourth data to the fourth data transmission line.

In the integrated circuit according to the exemplary embodiment of the present invention, a minimum number of shielding lines are disposed, and a data pattern is detected to prevent a coupling phenomenon, thereby improving signal transmission characteristics without net die loss.

By arranging a minimum number of shielding lines and detecting data patterns, coupling can be prevented to improve signal transmission characteristics without net die loss.

1 is a view for explaining an existing data transmission line.
FIG. 2 is a diagram illustrating a case where a shielding line is inserted into the data transmission line of FIG. 1.
3 is a view for explaining a data transmission line according to a first embodiment of the present invention.
4 is a diagram for describing a data transmission line according to a second embodiment of the present invention.
FIG. 5 is a circuit diagram for describing the pattern detection unit 410 of FIG. 4.
FIG. 6 is a table for explaining the circuit operation of FIGS. 4 and 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

FIG. 3 is a diagram illustrating a data transmission line according to a first embodiment of the present invention. Similarly to FIG. 1, a semiconductor memory device having 16 data pads (not shown) and having a bus length of 4 is illustrated. As an example.

3 shows two odd data transfer lines and two even data transfer lines corresponding to 16 data pads, respectively. Here, the odd data transmission lines are grouped by four and the even data transmission lines are also grouped by four. The odd data transmission lines grouped by four will be referred to as 'odd data transmission line groups', and the even data transmission lines grouped by four will be referred to as 'even data transmission line groups' hereinafter. A shielding line SHL is disposed between the even data transfer line groups.

An integrated circuit according to an embodiment of the present invention groups and arranges odd data transfer lines and even data transfer lines. In addition, as will be described in detail later, it is possible to detect a data transmission line where coupling occurs and to convert data of one data transmission line among the data transmission lines.

Hereinafter, for convenience of description, four data transmission lines 'DQ0_EV0', 'DQ1_EV0', 'DQ2_EV0', and 'DQ3_EV0' data transmission lines will be described as representatives, and it is assumed that '1101' data is transmitted. .

As assumed above, when '101' data is transmitted to the 'DQ1_EV0', 'DQ2_EV0', and 'DQ3_EV0' data transmission lines, a coupling phenomenon occurs in the data transmitted through the data transmission lines. An integrated circuit according to an embodiment of the present invention senses '101' data and converts data of one data transmission line among 'DQ1_EV0', 'DQ2_EV0', and 'DQ3_EV0' data transmission lines according to the detection result. In other words, the data of the 'DQ2_EV0' data transfer line through which '0' data is transmitted among '1101' data is inverted and output. That is, the integrated circuit according to the embodiment of the present invention converts and transmits '1101' data transferred through 'DQ0_EV0', 'DQ1_EV0', 'DQ2_EV0', and 'DQ3_EV0' data transmission lines to '1111' data. Therefore, the coupling phenomenon disappears through this data conversion.

FIG. 4 is a diagram illustrating a data transmission line according to a second embodiment of the present invention, and includes four first to fourth data transmission lines DL1 corresponding to the even data line group or the odd data line group of FIG. 3. DL2, DL3, DL4) will be described as a representative.

Referring to FIG. 4, the second embodiment of the present invention detects data patterns of the first to fourth data transmission lines DL1, DL2, DL3, and DL4 and uses the first and second detection signals DET1 and DET2. A pattern detector 410 for outputting, a first data converter 420 for converting data of the first data transmission line DL1 in response to the first detection signal DET1, and a second detection signal DET2. A second data converter 430 for converting the data of the fourth data transfer line DL4 in response to. Here, the first data converter 420 is inserted and disposed on the first data transmission line DL1, and the second data converter 430 is inserted and disposed on the fourth data transmission line DL4.

FIG. 5 is a circuit diagram for describing the pattern detection unit 410 of FIG. 4.

Referring to FIG. 5, the pattern detector 410 combines data in which a coupling phenomenon occurs among data transmitted to the first to third data transmission lines DL1, DL2, and DL3 to the first detection signal DET1. The first pattern detector 510 outputs the data of the coupling shape among the data transmitted to the second through fourth data transmission lines DL2, DL3, and DL4, and outputs the detected data as the second detection signal DET2. The second pattern detection unit 520 is provided.

Referring back to FIG. 4, among the first to fourth data transmission lines DL1, DL2, DL3, and DL4, a data transmission line where coupling may occur, that is, a coupling generation target data transfer line may include first to third data. Transmission lines DL1, DL2, DL3 and second to fourth data transmission lines DL2, DL3, DL4. Therefore, the first pattern detection unit 510 of the pattern detection unit 410 according to an embodiment of the present invention detects a data pattern of data transmitted through the first to third data transmission lines DL1, DL2, DL3, The second pattern detector 520 detects a data pattern of data transmitted through the second to fourth data transmission lines DL2, DL3, and DL4.

Subsequently, data transmitted through the first data transmission line DL1 and the fourth data transmission line DL4 are converted in response to the detected first and second detection signals DET1 and DET2. To this end, in an embodiment of the present invention, a data converter is provided to correspond to the data generation line for coupling occurrence, and the first data converter 420 responds to the first detection signal DET1 in response to the first data transmission line ( The data transmitted through the DL1 is inverted, and the second data converter 430 inverts the data transmitted through the fourth data transmission line DL4 in response to the second detection signal DET2.

FIG. 6 is a table for explaining the circuit operation of FIGS. 4 and 5.

Table (A) of FIG. 6 shows data that can be transmitted through the first to fourth data transmission lines DL1, DL2, DL3, DL4. The shaded portion in Table (A) means a data pattern in which a coupling phenomenon occurs. On the other hand, Table (B) shows the data converted by the first and second data converters 420 and 430. The shaded portion in Table (B) means the data in which the coupling occurs and is modified. That is, when a data pattern generating a coupling phenomenon is input to the first to third data transmission lines DL1, DL2, and DL3, the data transmitted through the first data transmission line DL1 is inverted, and the second to third data transmission lines DL1, DL2, and DL3 are inverted. When a data pattern generating a coupling phenomenon is input to the fourth data transmission lines DL2, DL3, and DL4, the data transmitted through the fourth data transmission line DL4 is inverted. As shown in Table (B), the data pattern in which the coupling phenomenon occurs does not exist in the first to fourth data transmission lines DL1, DL2, DL3, DL4 through the above operation according to the embodiment of the present invention. Do not.

As described above, the integrated circuit according to the embodiment of the present invention can arrange the minimum number of shielding lines, and also, a plurality of grouped groups can detect the data of the data transmission line and prevent the coupling phenomenon.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

SHL: Shielding Line
DQ_EV: Even data transfer line
DQ_OD: Odd Data Transfer Line

Claims (10)

An even data transmission line group in which a plurality of odd data transmission lines are grouped into a predetermined number;
An odd data transmission line group in which a plurality of even data transmission lines are grouped into a predetermined number;
A pattern detector for detecting a data pattern of data transmitted through the plurality of odd data transmission lines and the plurality of even data transmission lines and outputting the detected data pattern as a detection signal; And
Data conversion unit for converting the data of one data transmission line of the plurality of data transmission line to which the data of the data pattern is transmitted in response to the detection signal
Integrated circuit comprising a.
The method of claim 1,
And a shielding line is disposed between the even data transmission line group and the odd data transmission line group.
Four or more data transfer lines for transferring data;
A plurality of pattern detectors for detecting a data pattern of data transmitted through a data generation line for coupling occurrence among the data transmission lines and outputting a plurality of detection signals; And
A plurality of data converters for converting data of one data transmission line of the coupling generation target data transmission line in response to the plurality of detection signals.
Integrated circuit comprising a.
The method of claim 3,
And the data generation line to which the coupling occurs comprises a predetermined number of data transmission lines disposed adjacent to each other among the four or more data transmission lines.
The method of claim 3,
And the number of the plurality of pattern detection units corresponds to the number of the data transmission lines for the coupling occurrence target.
In the third aspect,
And the number of the plurality of data converters corresponds to the number of the data transmission lines to which the coupling occurs.
First to fourth data transmission lines disposed at regular intervals and configured to transfer first to fourth data, respectively;
A first pattern detector for detecting a data pattern of the first to third data and outputting the first pattern as a first detection signal;
A second pattern detector for detecting a data pattern of the second to fourth data and outputting the second pattern as a second detection signal;
A first data converter for converting the first data in response to the first detection signal and transferring the first data to the first data transmission line; And
A second data converter for converting the fourth data in response to the second detection signal and transferring the fourth data to the fourth data transmission line
Integrated circuit comprising a.
8. The method of claim 7,
And a shielding line disposed at edges of the first to fourth data transmission lines.
8. The method of claim 7,
And the first data converter is inserted and disposed on the first data transmission line.
8. The method of claim 7,
And the second data converter is inserted and disposed on the second data transmission line.
KR1020120078804A 2012-07-19 2012-07-19 Integrated circuit KR20140013160A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020120078804A KR20140013160A (en) 2012-07-19 2012-07-19 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120078804A KR20140013160A (en) 2012-07-19 2012-07-19 Integrated circuit

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Publication Number Publication Date
KR20140013160A true KR20140013160A (en) 2014-02-05

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