KR20140002454A - Methods and apparatus of wafer level package for heterogeneous integration technology - Google Patents

Abstract

Disclosed are a method and apparatus for forming a WLP device packaged with a molding material sealing a first and a second chip. The first chip is fabricated by a first technique. The second chip is fabricated by a second technique different from the first technique. A post passivation interconnection line where the first chip is connected to a first contact pad by a first connection and the first chip is connected to a second contact pad by a second connection may be formed on the molding material. The first and the second connection may be a Cu ball, a Cu via, a Cu stud, or a different connection.

Description

[0001] METHODS AND APPARATUS OF WAFER LEVEL PACKAGE FOR HETEROGENEOUS INTEGRATION TECHNOLOGY [0002]

The present invention relates to the field of semiconductors.

Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic devices. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by the ever-decreasing minimum feature size that allows more components to be integrated within a given area . These smaller and smaller electronic components also require smaller packages that use less area than previous packages in some applications.

One type of small package for the developed semiconductor device is a wafer level package (WLP). Wafer level packages of integrated circuits (ICs) fabricated with heterogeneous technology, which may be referred to as heterogeneous integration, provide high performance and high density while reducing manufacturing costs. Early applications of heterogeneous integration, also referred to as hyper-integration, have occurred in microprocessors, application specific integrated circuits (ASICs) and memories. Other applications of heterogeneous integration are being developed for radio frequency (RF), analog, optical, and MEMS, and the integration of ICs fabricated with heterogeneous technologies such as digital CMOS, SiGe RF BiCMOS, Can be "packaged ".

Many conventional WLP techniques for heterogeneous integrated technologies are based on vertical stacking of ICs. These techniques may require higher heights, which may not be applicable in some situations. Thus, there is a need to develop other forms of WLP technology for heterogeneous integration technologies. Many conventional WLP techniques for heterogeneous integrated technologies are based on vertical stacking of ICs. These techniques may require higher heights, which may not be applicable in some situations. Thus, there is a need to develop other forms of WLP technology for heterogeneous integration technologies.

A first chip made of the first technique and a second chip made of the second technique different from the first technique and forming a WLP device packaged together by a molding material that encapsulates the first chip and the second chip A method and apparatus are disclosed. A post passivation interconnect (PPI) line may be formed on the molding material that is connected to the first contact pad of the first chip by a first connection and to a second contact pad of the second chip by a second connection, The first connection and the second connection may be Cu balls, Cu vias, Cu studs or other types of connections.

A method and apparatus for a wafer level package for heterogeneous integration techniques in accordance with the present invention can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present disclosure and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:
Figures 1A and 1B illustrate an embodiment of a wafer level package (WLP) for integrated circuits (ICs) made with disparate technologies.
Figures 2A-2H illustrate a method of an embodiment of a WLP process for ICs fabricated with disparate techniques.
Figures 3A-3F illustrate a method of another embodiment of a WLP process for ICs fabricated with disparate technologies.
Corresponding numerals and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The drawings are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.

The formation and use of embodiments of the present disclosure will be described in detail below. It should be understood, however, that the embodiments of the present disclosure provide a number of applicable concepts that can be implemented in a wide variety of specific contexts. The specific embodiments described are merely illustrative of specific ways of forming and using the present disclosure and are not intended to limit the scope of the present disclosure.

Wafer level packages (WLP) are commonly used in integrated circuits (ICs) that require high speed, high density and higher pin counts. A WLP-style semiconductor device involves mounting an active area of the die toward a chip carrier substrate or a printed circuit board (PCB). Electrical and mechanical interconnections are achieved through a plurality of connection devices, simply referred to as a connection, such as conductive solder bumps or balls. The solder bumps are formed on bump pads or interconnect points or contact pads disposed on the active area. The connections may be solder bumps, solder balls, Cu studs, Cu vias, or any other similar connecting device for achieving electrical connection between two objects. Any of these connection devices can be simply referred to as a connection. A contact pad is used to mean an interconnect point, a bump pad, or any other conductive object making up the connection.

A method for forming a WLP device comprising a first chip and a second chip packaged together by a molding material encapsulating a first chip made with the first technique and a second chip made with the second technique and The device is initiated. A post passivation interconnect (PPI) line connected to the first contact pad of the first chip by a first connection and connected to a second contact pad of the second chip by a second connection is formed on the molding material And the first and second connections may be Cu balls, Cu vias, Cu studs, or other types of connections.

As illustrated in the cross-sectional view in FIG. 1A, an exemplary WLP style semiconductor device 500 of heterogeneous integration technology includes a CMOS chip 101, a GaAs chip 201, a SiGe chip 301, and an integrated passive device (IPD) ( 401). The CMOS chip 101 may be a processor or a memory chip. The GaAs chip 201 may be a photoelectric device such as an image sensor or a power amplifier. The SiGe chip 301 may be a BiCMOS pipelined A / D converter. IPD 401 may be an integrated passive circuit that includes a resistor, an inductor, and a capacitor. The device 500 may be an intelligent wireless terminal integrated processor, a large memory, an image sensor, and an RF / microwave transceiver in a WLP device.

The number of chips using heterogeneous technology is for illustrative purposes only and is non-limiting. The WLP device 500 of heterogeneous integration technology may include a first chip made with a first technology, a second chip made with a second technology, or any other combination. For a chip, the term may refer to the size of the transistor of the chip, the size of the wafer used to fabricate the chip, the difference to the transistor, or any other term used in the art. Thus, CMOS chips, GaAs chips, SiGe chips, and IPDs are all manufactured with different technologies.

Although not shown in FIG. 1A, the CMOS chip 101 may include active and passive devices, conductive layers, and dielectric layers formed on a substrate, which may be a bulk silicon substrate or a silicon-on-insulator substrate. Can be. Other semiconductor materials including Group III, Group IV, and Group V elements may also be used in the substrate. GaAs chip 201 may include npn bipolar transistors on a semi-insulated GaAs substrate. The SiGe chip 301 may include a SiGe heterojunction bipolar transistor (HBT) including germanium (Ge) as a base. SiGe Bi-CMOS technology can be a suitable technology for manufacturing radio frequency (RF) / analog / digital systems among various wireless mobile communication components. IPD 401 may be an integrated passive circuit that includes a resistor, an inductor, and a capacitor.

1A illustrates a contact pad 102 on a chip 101, a contact pad 202 on a chip 201, a contact pad 302 on a chip 301, and a contact pad 402 on a chip 401. These are all connected to one or a plurality of solder balls / bumps 508. These contact pads 102, 202, 302, and 402 are also electrically connected to each other. Chips 101, 201, 301, and 401 may include a plurality of contact pads connected to a plurality of solder balls / bumps not shown in FIG. 1A. The conductive layer is formed as contact pads 102 on the surface of the CMOS chip 101. Other contact pads 202, 302, and 402 are likewise formed. Contact pads 102, 202, 302, and 402 may be referred to as conductive pads. Contact pads 102, 202, 302, and 402 are made of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other electrically conductive materials Can be. Deposition of contact pads 102, 202, 302, and 402 uses an electrolytic plating, sputtering, PVD, or electroless plating process. The size, shape, and location of the contact pads 102, 202, 302, and 402 are for illustrative purposes only and not limitation. In general, the first contact pad may be on a first chip fabricated in the first technique, and the second contact pad may be on a second chip fabricated in the second technique. These contact pads may also be electrically connected to each other. The plurality of contact pads not shown may be the same size or different sizes.

The passivation layer 103 may be formed on the surface of the CMOS chip 101 and on the top surface of the contact pad 102 for structural support and physical isolation. The passivation layer 103 may be formed of a material selected from the group consisting of un-doped silicate glass (USG), silicon nitride, silicon dioxide, silicon oxynitride (SiON), polyimide (PI), benzocyclobutene (BCB), polybenzoxazole And may be made of an insulating material. An opening in the passivation layer 103 is made by removing a portion of the passivation layer 103 using a mask defined photoresist etching process to expose the contact pad 102. The size, shape, and position of openings made are for illustration purposes only and are not limiting. Similarly, for structural support and physical isolation, a passivation layer having openings exposing contact pads 202, 302, and 402, respectively, with a material similar to passivation layer 103 on chips 201, 301, and 401, respectively. 203, 303, and 403 are formed. In general, the first passivation layer may be on a first contact pad on a first chip made with the first technique and the second passivation layer may be on a second contact pad on a second chip made with the second technique .

A high precision stencil machine can be used to deposit discrete blocks of solder paste 104 over contact pads 102. The solder paste 104 deposited on the contact pads 102 forms a small solder paste brick 104. Similar solder paste bricks 204, 304, and 404 may be formed on the contact pads 202, 302, and 402, respectively, in the same format. After forming the solder paste brick 104, and other solder paste bricks 204, 304, and 404 on the contact pads 102, the device 500 can be moved to a reflow oven to reflow the solder. May be heated in an oven (ie, vaporizing the flux from the solder paste brick to form solder balls). The reflow process creates both mechanical and electrical connections between solder balls 105 and corresponding contact pads 102 after the reflowed solder 105 has cooled and solidified. Similar solder balls 205, 305, and 405 may be formed for the chips 201, 301, and 401.

The chips 101, 201, 301, and 401 manufactured using the heterogeneous technology can be packed horizontally together using the molding material 503 by a molding process. Chips having their contact pads 102, 202, 302, and 402 connected to solder balls 105, 205, 305, and 405 together with their respective passivation layers 103, 203, 303, and 403, respectively. 101, 201, 301, and 401 are molded together horizontally using a molding resin such as, for example, an epoxy molding compound (EMC). The molding process may be referred to as an encapsulation process. The molding material 503 encapsulates the chips 101, 201, 301, and 401 together into one physical piece. The molding material 503 is in contact with a layer of a die attach film (DAF) A carrier substrate may have been used below the DAF 502 to support the molding operation, which is now removed from the structure shown in FIG. 1A.

Polymer layer 504 may be formed on molding material 503. The polymer layer 504 may be patterned to form openings to expose the solder balls 105, 205, 305, and 405. Patterning of the polymer layer 504 may include photolithography techniques. Polymer layer 504 may be formed of a polymer such as epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like, but other relatively soft, often organic dielectric materials may also be used. Preferred forming methods include spin coating or other commonly used methods. The thickness of the polymer layer 504 may be between about 5 μm and about 30 μm. The dimensions quoted throughout the specification are merely exemplary and will vary with the downscaling of the integrated circuit.

Following the contour of the polymer layer 504, a metal material is used to form a post passivation interconnect (PPI) line 505 on the polymer layer 504. PPI line 505 also fills the opening of polymer layer 504 and contacts solder balls 105, 205, 305, and 405. Thus, PPI line 505 forms an electrical connection between solder balls 105, 205, 305, and 405, and further contacts contact pads 102, 202, 302, and 402, respectively. The PPI line 505 has a thickness of less than about 30 microns, more preferably between about 2 microns and about 10 microns. The PPI line 505 may further include a nickel-containing layer (not shown) on the upper surface of the copper layer. The forming method includes plating, electroless plating, sputtering, chemical vapor deposition, and the like.

A second polymer layer 506 may be formed on the PPI line 505. The second polymer layer 506 may be patterned to form openings in which the solder balls 508 are to be placed. Patterning of the polymer layer 506 may include photolithography techniques. Polymer layer 506 may be formed of a polymer such as epoxy, polyimide, BCB, PBO, and the like, but other relatively soft, often organic dielectric materials may also be used. Preferred forming methods include spin coating or other commonly used methods.

A layer of UBM 507 may be formed around the opening of the second polymer layer 506. The UBM layer 507 may be formed of copper or a copper alloy, which may include silver, chromium, nickel, tin, gold, and combinations thereof. Additional layers such as a nickel layer, a lead-free pre-solder layer, or a combination thereof may be formed over the copper layer. The UBM layer 507 may have a thickness between about 1 [mu] m and about 20 [mu] m.

Solder balls 508 may be mounted on the UBM 507. As is generally known in the art, solder ball 508 may include alloys such as tin, lead, silver, copper, nickel, bismuth, and the like. Alternatively, instead of solder balls 508, copper bumps may be formed on UBM 507, for example by plating, printing, or the like.

The connection between the solder balls 508 and the contact pads 102 with respect to the first chip 101 is connected to the top surface of the first chip 101 through the UBM layer 507, the PPI line 505, and the solder balls 105. Contact pads 102 on the top. Connections between the solder balls 508 and the contact pads 202, 302, and 402 are likewise formed. Thus, the chips 101, 201, 301, and 401 of disparate technology are packaged together and electrically connected to each other and to the solder ball 508, which can also be mounted on a printed circuit board (PCB) not shown.

The chips 101, 201, 301 and 401 of heterogeneous technology can be packaged together and electrically connected to each other and connected to the solder ball by different means. The device 600 of FIG. 1B is another exemplary embodiment showing different connection mechanisms between the contact pads 102, 202, 302, and 402 and the solder balls 508. Except for differences in connection mechanisms, the other parts of FIG. 1B are essentially the same as those illustrated in FIG. 1A.

As illustrated in FIG. 1B, the connection of the first chip 101 to the solder ball 508 to the first contact pad 102 is performed through the PPI line 505 through the contact pad 102, Cu via 6061. It is further connected to the UBM layer 507 where solder balls 508 are located. Cu via 6061 is a connection or connection device for connecting contact pad 102 to PPI line 505. The PPI line 505 further contacts the UBM layer 507 where the solder ball 508 is located.

The connection to the solder ball 508 for the second contact pad 202 on the second chip 201 is done in a different manner. The second contact pad 202 is connected to a solder paste brick 6042 on which a solder ball 6052 is formed by a reflow process. Solder ball 6052 is further connected to PPI line 505 which is connected to UBM layer 507 where solder ball 508 is located. The solder ball 6602 is a connection or a connection device for connecting the contact pad 202 to the PPI line 505. The PPI line 505 further contacts the UBM layer 507 where the solder ball 508 is located.

Connection to the solder ball 508 for the third contact pad 302 on the third chip 301 is done in a third way. A Cu stud 6053 is connected to the third contact pad 302 on the third chip 301 which is further connected to the PPI line 505 which is connected to the UBM layer 507 where the solder ball 508 is located . Cu stud 6053 is a connection or connection device that connects contact pad 302 to PPI line 505. The PPI line 505 further contacts the UBM layer 507 where the solder ball 508 is located.

The example shown in Figure 1B illustrates a fourth contact pad 402 that is connected to the solder ball 508 using a Cu stud 6054 in a manner similar to the way that the third contact pad 302 is connected to the solder ball 508 .

Cu via 6051, solder ball 6052, and Cu stud 6053 are used to connect to the PPI line 505 in FIG. 1B. Generally, the PPI line 505 can be connected to the first contact pad on the first chip by a first connection and to the second contact pad on the second chip by a second connection, and the Cu via, Cu stud, And solder balls are examples of connections. The connection may be a via, a stud, a ball, or a bump made of any conductive material. The connections may be different for different chips made with different technologies. There may be many other connections used in the art or developed in the future. The connection may be of various types such as square, ball, diamond, or any other kind of shape. The connections may be made of other conductive materials such as copper, tin alloys, lead, silver, copper, nickel, bismuth, and the like.

The choice of using Cu vias, solder balls, or Cu studs as connecting devices or connections may depend on the number of IO pins for the chip. If the chip 101 has more than about 100 IP pins, a Cu via 6061 may be used as the connection for connecting to the contact pad 102. If the chip 201 has a number of IP pins in the range of about 50 to 100, solder balls 6602 can be used as a connection to connect to the contact pads 202. If the chip 301 has a number of IP pins less than about 50, a Cu stud may be used as the connection for connecting to the contact pad 302 as shown in FIG. 1B.

The connections may have different sizes or different shapes. Cu vias may have a height greater than about 10 microns and a width greater than about 30 microns. The solder ball or Cu ball may have a height greater than about 30 microns and a width greater than about 70 microns. The Cu stud may have a height of about 10 [mu] m to 20 [mu] m and a width of greater than about 50 [mu] m. The Cu via may have a square shape. The solder ball or the Cu ball may have a rounded shape. The Cu stud can also be formed in a round shape. Connections can also be made in other ways. For example, a solder ball or a Cu ball can be made by reflow followed by pre-solder pasting through a stencil, which will be a different process for Cu vias or Cu studs.

2A-2H illustrate a method of an embodiment of a WLP process for assembling the WLP device 500 as shown in FIG. 1A.

As illustrated in FIG. 2A, four chips are provided that include a CMOS chip 101, a GaAs chip 201, a SiGe chip 301, and an integrated passive device (IPD) 401. Contact pad 102 is on chip 101, contact pad 202 is on chip 201, contact pad 302 is on chip 301, and contact pad 402 is a chip ( 401). A passivation layer 103 may be formed on the surface of the CMOS chip 101 and on the top surface of the contact pad 102 for structural support and physical isolation. An opening in the passivation layer 103 is made by removing a portion of the passivation layer 103 using a mask defined photoresist etching process to expose the contact pad 102. Similarly, passivation layers 203, 303, and 403 are formed on chips 201, 301, and 401 for structural support and physical isolation, respectively, opening openings to expose contact pads 202, 302, and 402, respectively. Have

As illustrated in FIG. 2B, four chips 101, 201, 301, and 401 are disposed on a carrier 501 to which a DAF 502 is attached. The chips 101, 201, 301, and 401 are spaced apart and disposed on the surface of the DAF 502. Carrier 501 is a support carrier during the packaging process and will be removed once packaging is complete.

As illustrated in FIG. 2C, a high precision stencil machine may be used to deposit discrete blocks of solder paste 104 over contact pads 102. The solder paste 104 deposited on the contact pads 102 forms a small solder paste brick 104. Similar solder paste bricks 204, 304, and 404 may be formed in the same format for different chips 201, 301, and 401, respectively.

As illustrated in FIG. 2D, after forming the solder paste brick 104 and other solder paste bricks 204, 304, and 404 on the contact pad 102, the device 500 is moved to a reflow oven, The solder may be heated in an oven to reflow the solder (ie, vaporize the flux to form solder balls from the solder paste brick). The reflow process creates both mechanical and electrical connections between solder balls 105 and corresponding contact pads 102 after the reflowed solder 105 has cooled and solidified. Similar solder balls 205, 305, and 405 may be formed for the chips 201, 301, and 401, respectively.

As illustrated in FIG. 2E, the chips 101, 201, 301, and 401 manufactured with the heterogeneous technology can be packaged horizontally together using the molding material 503 by a molding process. The molding process may be referred to as a sealing process. The molding material 503 encapsulates the chips 101, 201, 301 and 401 together into one physical piece. The molding material 503 fills the space between pairs of chips and further covers the periphery of each chip.

As illustrated in FIG. 2F, the molding material 503 covering the solder balls 105, 205, 305, and 405 may be solder balls 105, 205, 305, and 405 to be used as a connection to another layer, such as a PPI layer. Thinning by grinding to expose a).

As illustrated in FIG. 2G, a polymer layer 504 may be formed on the molding material 503. The polymer layer 504 may be patterned to form openings to expose the solder balls 105, 205, 305, and 405. Following the contour of the polymer layer 504, a metal material is used to form the post passivation interconnect (PPI) line 505 on the polymer layer 504. PPI line 505 also fills an opening in polymer layer 504 and contacts solder balls 105, 205, 305, and 405. PPI line 505 thus forms an electrical connection between solder balls 105, 205, 305, and 405, which further contacts contact pads 102, 202, 302, and 402, respectively. A second polymer layer 506 may be further formed on the top surface of the PPI line 505. [

As illustrated in Figure 2h, the second polymer layer 506 may be patterned to form an opening in which the solder ball 508 will be placed. The opening of the second polymer layer 506 may not be directly above the opening of the first polymer layer 504. A UBM layer 507 may be formed around the opening of the second polymer layer 506. There may be multiple sublayers for the UBM layer 507. A solder ball 508 may be mounted on the UBM layer 507 at each opening in the second polymer layer 506. The carrier 501 is removed after four chips 101, 201, 301, and 401 are packaged and connected to the solder balls 508.

3A-3F illustrate a method of another embodiment of a WLP process for assembling the WLP device 500 as shown in FIG. 1B.

As illustrated in FIG. 3A, four chips are provided that include a CMOS chip 101, a GaAS chip 201, a SiGe chip 301, and an IPD 401. Contact pad 102 is on chip 101, contact pad 202 is on chip 201, contact pad 302 is on chip 301, and contact pad 402 is a chip ( 401). The passivation layer 103 may be formed on the surface of the CMOS chip 101 and on the top surface of the contact pad 102 for structural support and physical isolation. An opening in the passivation layer 103 is made by removing a portion of the passivation layer 103 to expose the contact pad 102. Similarly, passivation layers 203, 303, and 403 are formed on chips 201, 301, and 401 for structural support and physical isolation, respectively, opening openings to expose contact pads 202, 302, and 402, respectively. Have

As illustrated in FIG. 3B, four chips 101, 201, 301, and 401 are disposed on a carrier 501 to which a DAF 502 is attached. The chips 101, 201, 301, and 401 are spaced apart and disposed on the surface of the DAF 502. Carrier 501 is a support carrier during the packaging process and will be removed once packaging is complete.

As illustrated in Figure 3C, different connections are formed on the chip. Cu via 6061 is a connection or connection device formed on contact pad 102, which will connect contact pad 102 to a PPI line formed later. Cu studs 6053 and 6054 are another connection formed on contact pads 302 and 402, which will connect contact pads 302 and 402 to the PPI lines formed later. The contact pad 202 is connected to a solder paste brick 6062 on which solder balls 6062 are formed thereon by a reflow process. Cu vias, Cu studs, and solder balls are examples of connections. There may be many other connections used in the art or developed in the future. The connection may be of various types such as square, ball, diamond, or any other kind of shape. The connections may be made of different conductive materials such as copper, tin alloys, lead, silver, copper, nickel, bismuth, and the like.

As illustrated in FIG. 3D, the chips 101, 201, 301, and 401 manufactured with the heterogeneous technology can be packaged horizontally together using the molding material 503 by a molding process. The molding process may be referred to as a sealing process. The molding material 503 encapsulates the chips 101, 201, 301 and 401 together into one physical piece. The molding material 503 fills the space between pairs of chips and further covers the perimeter of each chip.

As illustrated in FIG. 3E, the molding material 503 covering the connections 6061, 6052, 6053, and 6054 provides connections 6051, 6052, 6053, and 6054 to be used as connections to other layers, such as PPI layers. It is thinned by grinding to expose.

As illustrated in FIG. 3F, a polymer layer 504 may be formed on the molding material 503. The polymer layer 504 may be patterned to form openings to expose the connections 6061, 6052, 6053, and 6054. Following the contour of the polymer layer 504, a metal material is used to form the post passivation interconnect (PPI) line 505 on the polymer layer 504. PPI line 505 also fills an opening in polymer layer 504 and contacts contacts 6061, 6052, 6053, and 6054. PPI line 505 thus forms an electrical connection between connections 6061, 6052, 6053, and 6054, which further connects contact pads 102, 202, 302, and 402, respectively.

A second polymer layer 506 may be further formed on the top surface of the PPI line 505. [ The second polymer layer 506 may be patterned to form openings in which the solder balls 508 are to be placed. The opening of the second polymer layer 506 may not be directly above the opening of the first polymer layer 504. A UBM layer 507 may be formed around the opening of the second polymer layer 506. There may be multiple sublayers for the UBM layer 507. A solder ball 508 may be mounted on the UBM layer 507 at each opening in the second polymer layer 506. After the four chips 101, 201, 301, and 401 are packaged and connected to the solder ball 508, the carrier 501 is removed.

While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the true spirit and scope of the present disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and material composition, means, methods, and steps described in the specification. Those skilled in the art will readily appreciate from the present disclosure that there is a need for a process or machine that will be presently or later developed to perform substantially the same function or achieve substantially the same result as the corresponding embodiment described herein , Manufacturing, material composition, means, method, or step can be used in accordance with the present disclosure. Accordingly, the appended claims intend to include within their scope such processes, machines, manufacturing, material compositions, means, methods or steps. Furthermore, each claim constitutes an individual embodiment, and the various claims and combinations of embodiments are within the scope of this disclosure.

101: CMOS chip
102, 202, 302, 402: contact pads
103, 203, 303, 403: passivation layer
104, 204, 304, 404: solder paste brick
105, 205, 305, 405: solder balls
201: GaAs chip 301: SiGe chip
401: IPD
500: WLP semiconductor device 502: die attach film (DAF)
503: molding material 504, 506: polymer layer
505: PPI line 507: UBM layer
508: solder ball and bump 6051: Cu via
6052: Solder ball 6053: Cu stud

Claims (10)

A first chip having a first contact pad and fabricated in a first technique;
A second chip having a second contact pad and manufactured by a second technology different from the first technology;
Molding material encapsulating the first chip and the second chip; And
A post passivation interconnect (PPI) line on the molding material, the post passivation interconnect line being connected to the first contact pad by a first connection and to the second contact pad by a second connection,
The first connection is of a first type and the second connection is of a second type different from the first type, both types being made up of conductive balls, conductive vias or conductive studs. Device selected from the group. The device of claim 1, wherein the first connection connecting the PPI line and the first contact pad is a Cu ball having a height greater than 30 microns and a width greater than 70 microns. The device of claim 1, wherein the first connection connecting the PPI line and the first contact pad is a Cu via having a height greater than 10 microns and a width greater than 30 microns. 2. The device of claim 1, wherein the first connection connecting the PPI line and the first contact pad is a Cu stud having a height of 10 [mu] m to 20 [mu] m and a width greater than 50 [mu] m. The device of claim 1, further comprising an under bump metal (UBM) layer in contact with the PPI line, formed on the opening of the polymer layer over the PPI line. The device of claim 1, further comprising a polymer layer between the molding material and the PPI line. The device of claim 1, further comprising a passivation layer encapsulated within the molding material and covering a portion of the first contact pad on a surface of the first chip. In a device forming method,
Providing a first chip having a first contact pad and made of a first technique;
Providing a second chip having a second contact pad and manufactured with a second technology different from the first technology;
Forming a first connection on the first contact pad and forming a second connection on the second contact pad, wherein the first connection is of a first type and the second connection is associated with the first type. Consisting of a second, different type, wherein both types are selected from the group consisting of conductive balls, conductive vias, or conductive studs;
Encapsulating the first chip and the second chip with a molding material; And
Forming a post passivation interconnect (PPI) line on the molding material that is connected to the first connection and the second connection. The method according to claim 8,
Forming a polymer layer between the molding material and the PPI line. A first chip having a first contact pad and made with a first technique, the first chip having a first passivation layer over the first contact pad, the first passivation layer having an opening exposing the first contact pad;
A second chip having a second contact pad and manufactured by a second technology different from the first technology, comprising: a second chip having a second passivation layer on the second contact pad, the second passivation layer having an opening to expose the second contact pad;
A first connection on the first contact pad and a second connection on the second contact pad, wherein the first connection is of a first type and the second connection is of a second type different from the first type, Both types of first and second connections are selected from the group consisting of conductive balls, conductive vias or conductive studs;
A molding material encapsulating the first chip and the second chip together while exposing the first connection and the second connection;
A polymer layer on the molding material having a first opening to expose the first connection and a second opening to expose the second connection; And
And a post passivation interconnect (PPI) line on the polymer layer, the post passivation interconnect (PPI) line being connected to the first connection at the first opening and to the second connection at the second opening.

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