KR20140001482A - Fuse array structure and semiconductor integrated circuit apparatus incuding the same - Google Patents

Fuse array structure and semiconductor integrated circuit apparatus incuding the same Download PDF

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Publication number
KR20140001482A
KR20140001482A KR1020120069158A KR20120069158A KR20140001482A KR 20140001482 A KR20140001482 A KR 20140001482A KR 1020120069158 A KR1020120069158 A KR 1020120069158A KR 20120069158 A KR20120069158 A KR 20120069158A KR 20140001482 A KR20140001482 A KR 20140001482A
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KR
South Korea
Prior art keywords
fuse
array
fuses
group
row
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Application number
KR1020120069158A
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Korean (ko)
Inventor
김승봉
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020120069158A priority Critical patent/KR20140001482A/en
Publication of KR20140001482A publication Critical patent/KR20140001482A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy

Abstract

A fuse array structure of an integrated semiconductor circuit device comprises a first fuse array, a second fuse array, and a third fuse array. The first fuse array comprises a first fuse group and a second fuse group having the number of asymmetric fuses. The second fuse array is adjacent to the first fuse array in a column direction and comprises a third fuse group and a fourth fuse group having the number of asymmetric fuses. The third fuse array is adjacent to the first fuse array in a row direction and comprises a fifth fuse group and a sixth fuse group having the number of asymmetric fuses. The first fuse array and the second fuse array are arranged in order that the number of asymmetric fuses is uniform in each column. The first fuse array and the third fuse array are arranged in response to the same number fuse.

Description

Fuse Array Structure and Semiconductor Integrated Circuit Apparatus Comprising the Same {Fuse Array Structure and Semiconductor Integrated Circuit Apparatus Incuding The Same}

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a fuse array structure and the like.

As the size of each element constituting the semiconductor integrated circuit device becomes smaller and the number of elements included in one semiconductor chip becomes larger, the level of defect density also increases. This increase in the defect density is a direct cause of lowering the yield of the semiconductor device, and in severe cases, the wafer on which the semiconductor element is formed must be disposed of.

In order to lower the defect density, a redundancy circuit has conventionally been proposed to replace defective cells with spare cells. In the case of a semiconductor memory device, a redundancy circuit (or a fuse circuit) may be provided for each of row-based wiring (eg, word lines) and column-based wiring (eg, bit lines). And a fuseset array for storing address information. The fuseset array consists of a plurality of fusesets comprising a plurality of fuse wires, and the programming of each fuseset may be done by selective laser blowing of the fuse wires.

However, compared to the speed at which the integration density and the process technology are developed, the speed at which the pitch between fuses is reduced due to the laser beam error tolerance is relatively slow, so that the area occupied by the fuses, that is, the fuseset array in the semiconductor chip is relatively low. The share can be increased rather. This is an obstacle to securing an effective net die of the semiconductor memory device.

The present invention provides a fuse array structure capable of reducing the area of a fuse array and a semiconductor integrated circuit device including the same.

A fuse array structure according to an embodiment of the present invention includes a plurality of fuse arrays arranged in a row direction and a column direction having an asymmetrical structure, and the plurality of fuse arrays adjacent in the row direction are disposed to be complementary to each other, The plurality of fuse arrays adjacent in the column direction are arranged to have folded symmetry.

In addition, a semiconductor integrated circuit device according to another exemplary embodiment of the present invention may include a first fuse array including a first fuse group and a second fuse group having an asymmetrical number of fuses, and adjacent to the first fuse array in a row direction. A second fuse array including a third fuse group and a fourth fuse group having an asymmetric fuse number and a fifth fuse group disposed adjacent to the first fuse array in a column direction and having an asymmetric fuse number And a third fuse array including a sixth fuse group, wherein the first fuse array and the second fuse array are complementarily arranged such that the number of asymmetrical fuses becomes uniform for every row, and the first fuse array and the third fuse. Arrays are folded so that fuses of the same order are matched.

In addition, the fuse array structure according to another embodiment of the present invention includes an upper fuse array, and a lower fuse array disposed in a column direction adjacent to the first fuse array, wherein the upper fuse array and the lower fuse array Are arranged in folded symmetrical form.

According to the present exemplary embodiment, the area of the fuse array may be reduced by removing the dummy fuse. At this time, due to the removal of the dummy fuse, the fuse rows constituting the fuse array may be symmetric, and thus may have a substantially stepped shape. At this time, since all the fuse arrays have a stepped shape by removing the dummy fuses, the complementary arrangement of the fuse arrays may take a square shape. Therefore, the area of the entire fuse array can be reduced.

Also, the fuse arrays located in the same mat row may be arranged in folded symmetry. Accordingly, the signal transmission path can be made uniform for each fuse array.

1A and 1B are circuit diagrams illustrating a fuse set circuit unit according to an exemplary embodiment of the present invention.
2 is a schematic plan view showing a mat and a fuse array according to an embodiment of the present invention.
3 is a plan view illustrating one fuse array according to an exemplary embodiment of the present invention.
4 is a plan view illustrating a pair of fuse arrays arranged in a column direction according to an embodiment of the present invention.
5 is a plan view illustrating a pair of fuse arrays arranged in a row direction according to an embodiment of the present invention.
6 is a plan view illustrating an arrangement relationship between a plurality of fuse arrays arranged in a row and a column direction and a mat according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout.

First, referring to FIGS. 1A and 1B, the fuse set 10 may include a fuse unit 15, a switch unit 20, and a connection unit 25.

The fuse part 15 includes a plurality of fuses, for example, 32 fuses F0-F31. The plurality of fuses F0-F31 may be divided into two groups, for example, and one end may be commonly connected to each group. For example, any one fuse unit 15 may have fuses F0-F15 formed in a first group, and one end thereof may be connected in common, and the remaining fuses F16-F31 may form a second group thereof. One end may be connected in common. In addition, the first group of the fuse unit 15 may be composed of the fuse (F0-F14), the second group may be composed of the fuse (F15-F31).

The switch unit 20 may include, for example, a plurality of NMOS transistors N0-N31. The plurality of NMOS transistors N0-N31 are connected to the respective fuses F0-F31 constituting the fuse unit 15, and are connected to the plurality of fuses in response to the block selection address BS_add <0:31>. Optionally connect (F0-F31) and ground terminal (Vss).

The connection part 25 includes a first connection fuse S1 and a fuse part 15 connecting the common node N1 of the first group of the fuse part 15 to the column repair circuit part 30 that provides the column repair address. And a second connection fuse S2 that connects the common node N2 of the second group of the second node to the column repair circuit unit 30.

Here, the fuse 15 of the fuse set 10 (hereinafter, the fuse array F_array A to F_array F) may be disposed outside the mat array MAT A-MAT D, as shown in FIG. 2. For example, when the fuses F0-F31 are column repair fuses, in the present embodiment, the fuse arrays may be disposed outside the mat array in the column direction. In addition, in the present embodiment, six fuse arrays F_array A to F_array F are arranged to correspond to four mats MAT A to MAT D, and each mat MAT A to MAT D is configured to have six fuse arrays ( F_array A- F_array F) Each of them receives a signal related to fuse cutting. Also, in the present embodiment, six fuse arrays corresponding to four mats are illustrated as corresponding arrangements. However, the present invention is not limited thereto, and more or smaller fuse arrays may be arranged on the mats. There will be.

3 is a layout diagram illustrating a fuse array according to an exemplary embodiment of the present invention. In FIG. 3, for example, the A-th fuse array F_array A will be described as an example.

Referring to FIG. 3, the fuse array F_array A includes a plurality of fuses F0-F31. The plurality of fuses F0-F31 are divided into a first group G1 and a second group G2. Each of the first group G1 and the second group G2 may include a plurality of fuses F0-F31, and each of the first and second groups G1 and G2 may include a plurality of fuses. A plurality of fuse rows FR may be included.

In addition, the first group G1 and the second group G2 of the present embodiment may include different numbers of fuses, and their arrangement may be different.

For example, the first group G1 of the A-th fuse array F_array A includes a first fuse row FR1 and a second fuse row FR2, and the second group G2A includes a third fuse row. FR3 and the fourth fuse row FR4. The plurality of fuse rows FR1 / FR2 and FR3 / FR4 constituting the same group G1A and G2A may include the same number of fuses, respectively. However, the number of fuses of the first group G1A and the number of fuses of the second group G2 may be different from each other, and the arrangement of the fuses constituting the first group G1 and the second group G2 may be different. The fuse arrangement may also be different.

In the present embodiment, the first group G1 is composed of a total of 17 fuses and connection fuses S1 from F0 to F16. The first fuse row FR1 of the first group G1 is composed of a total of nine fuses F0 to F8 extending in the row direction, and the second fuse row FR2 is arranged in the row direction. It consists of eight fuses and connecting fuses (S1) extending from F9 to F16, a total of nine fuses.

The second group G2 is composed of a total of 15 fuses F17 through F31 and a connection fuse S2. The third fuse row FR3 of the second group G2 consists of seven fuses F17 to F23 extending in the row direction and a connection fuse S2, and eight fuses in total, and the fourth fuse row FR4 consists of a total of eight fuses from F24 to F31 extending in a row.

In the conventional case, in order to equalize the number of the first and second groups G1A and G2A, it was common to provide dummy fuses. However, in this embodiment, the dummy fuse is removed, and the number of fuses of the groups constituting one fuse array is set asymmetrically.

In this case, although the connection fuse S1 of the first group G1 and the connection fuse S1 of the second group G2 may be located at arbitrary positions, the connection fuse p may be reduced so as to reduce the distance of the connection path p. It is preferable to face them.

Referring to FIG. 4, the A-th and C-th fuse arrays F_array A and F_array C located on the mat column are polled around the x-x 'line between the A-th and C-th fuse arrays F_array A and C. It is folded and symmetrical. That is, the sixth group G6 of the C-th fuse array F_array C is disposed to be adjacent to the second group G2 of the A-th fuse array F_array A in the column direction.

As the fuse arrays F_array A and C positioned on the same mat row are folded, the fuses of the same order of the fuse arrays F_array A and C face each other. Accordingly, a path of the signal S provided to the fuses of the same order for each fuse array F_array, for example, a block selection address BS_add <provided to the switch units N0-N31 connected to the fuses. 0:31>) the paths are substantially the same. Therefore, the signal transmission path for each fuse array can be made constant.

Referring to FIG. 5, the A and B fuse arrays F_array A and F_array B positioned on the same row based on one fuse array are arranged in a mutually complementary form.

A third group G3 of the B-th fuse array F_array B is disposed adjacent to the first group G1 of the A-th fuse array F_array A in a row direction, and the A-th fuse array F_array A The fourth group G4 of the B-th fuse array F_array B is disposed adjacent to the second group G2 of FIG.

In this case, the first group G1 of the A-th fuse array F_array A is more than the second group G2 so that the A-th and B-th fuse arrays F_array A and F_array B may be arranged in a mutually complementary form. In the case of a large number, the third group G3 of the B-th fuse array F_array B has a smaller number than the fourth group G4.

That is, the number of fuses of the first and second groups G1 and G2 of the A-th fuse array F_array A and the third and fourth groups G3 and G4 of the B-th fuse array F_array B are diagonal to each other. Groups located in will have the same number. Accordingly, the total sum of the fuses of the first groups G1A and G1B of the A and B th fuse arrays F_array A and B and the total sum of the fuses of the second groups G2A and G2B are the same, and are mutually complementary. Is arranged.

As shown in FIG. 6, the fuse arrays F_array A and C and F_array B and D adjacent in the column direction are arranged in folded symmetry with respect to the X-X 'line between them, and in the row direction. Adjacent fuse arrays F_array A and C and F_array B and D are respectively complementarily arranged.

Accordingly, the individual fuse arrays F_array A to D differ in the number of fuses in each group constituting them, and even if their arrangement is asymmetric with each other, they are viewed in terms of the overall bank BANK, for example in terms of four fuse arrays. In this case, all of the rows and columns may be arranged in a symmetrical form.

According to the present exemplary embodiment, the area of the fuse array may be reduced by removing the dummy fuse. At this time, due to the removal of the dummy fuse, the fuse rows constituting the fuse array may be symmetric, and thus may have a substantially stepped shape. At this time, since all the fuse arrays have a stepped shape by removing the dummy fuses, the complementary arrangement of the fuse arrays may take a square shape. Therefore, the area of the entire fuse array can be reduced.

Also, the fuse arrays located in the same mat row may be arranged in folded symmetry. Accordingly, the signal transmission path can be made uniform for each fuse array.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but variations and modifications may be made without departing from the scope of the present invention. Do.

G1-G6: Fuse group FR1-RR4: Fuse row

Claims (19)

A plurality of fuse arrays arranged in a row direction and a column direction having an asymmetric structure,
A plurality of fuse arrays adjacent to each other in the row direction are mutually disposed;
A plurality of fuse arrays adjacent in the column direction are arranged to have folded symmetry. The method of claim 1,
And the fuse array includes a plurality of fuse rows including a plurality of fuses extending along the row direction. 3. The method of claim 2,
And a plurality of fuses of the plurality of fuse rows constituting one fuse array such that the fuse arrays have an asymmetrical structure. 3. The method of claim 2,
The fuse array comprises a first group comprising first and second fuse rows, and
A second group comprising third and fourth fuse rows,
A fuse array structure in which the number of fuses in the second group and the number of fuses in the first group are different. 5. The method of claim 4,
The number of fuses constituting the first and second fuse rows is the same,
The number of fuses constituting the third and fourth fuse rows is the same,
And a fuse number of the third fuse row is different from a fuse number constituting the first fuse row. The method of claim 1,
And the plurality of fuse arrays are each configured to provide fuse cutting information to a plurality of mats. The method of claim 1,
And the fuse arrays arranged adjacent to each other in the column direction are arranged such that fuses of some of the fuses constituting them face each other with the same number of fuses receiving the same address. A first fuse array comprising a first fuse group and a second fuse group having an asymmetrical number of fuses;
A second fuse array disposed adjacent to the first fuse array in a row direction and including a third fuse group and a fourth fuse group having an asymmetrical number of fuses; And
A third fuse array disposed adjacent to the first fuse array in a column direction, the third fuse array including a fifth fuse group and a sixth fuse group having an asymmetrical number of fuses;
The first fuse array and the second fuse array are complementarily arranged such that the number of asymmetrical fuses is uniform across rows,
And the first fuse array and the third fuse array are folded so that the fuses of some of the fuses constituting them face each other with the same number of fuses receiving the same address. The method of claim 8,
The first fuse group of the first fuse array includes a first fuse row and a second fuse row in which n fuses are arranged in the row direction, respectively,
The second fuse group is disposed in parallel with the first fuse group in the row direction, and the second fuse group includes a third fuse row and a fourth fuse row in which n-1 fuses are arranged in the row direction, respectively. Semiconductor integrated circuit device configured to include. The method of claim 9,
The third fuse group of the second fuse array is disposed adjacent to the first fuse group in the row direction, and the first fuse row and the second fuse row in which the n-1 fuses are arranged in the row direction, respectively. Including,
The fourth fuse group is disposed in parallel with the third fuse group;
The fourth fuse group includes third and fourth fuse rows in which the n fuses are arranged in the row direction, respectively;
And the first fuse group and the third fuse group are disposed adjacent to each other in the row direction, and the second fuse group and the fourth fuse group are disposed adjacent to each other in the row direction. 11. The method of claim 10,
The fifth fuse group of the third fuse array includes a first fuse row and a second fuse row in which the n fuses are arranged in the row direction,
The sixth fuse group is disposed in parallel with the fifth fuse group in the row direction, and the sixth fuse group includes a third fuse row and a fourth fuse row in which the n-1 fuses are arranged in the row direction. Semiconductor integrated circuit device comprising a. The method of claim 11,
And a sixth fuse group of the third fuse array is disposed to face the second fuse group of the first fuse array. 12. The method according to any one of claims 9 to 11,
Each of the first to third fuse array structures
The second fuse row and the third fuse row are disposed to face each other,
Each of the second fuse row and the third fuse row includes a connection fuse,
And a connection fuse of the second fuse row and a connection fuse of the third fuse row are disposed to face each other. The method of claim 8,
And a plurality of mats disposed to correspond to the first to fourth fuse arrays. 15. The method of claim 14,
And the plurality of mats receive fuse cutting information from each of the first to fourth fuse arrays. Upper fuse array; And
A lower fuse array disposed adjacent to the upper fuse array in a column direction;
And the upper fuse array and the lower fuse array are arranged in folded symmetrical form. 17. The method of claim 16,
And the upper fuse array and the lower fuse array include fuses arranged in substantially the same shape. 17. The method of claim 16,
The upper fuse array and the lower fuse array include a plurality of fuse rows including a plurality of fuses;
Wherein the fuse rows comprise a partially different number of fuses. The method of claim 17,
An address line for providing an address signal to a corresponding fuse of the upper fuse array and the lower fuse array is further disposed between the upper fuse array and the lower fuse array;
And the upper fuse array and the lower fuse array are arranged such that fuses facing the same number of fuses face each other so that a common signal is provided by the same address line.
KR1020120069158A 2012-06-27 2012-06-27 Fuse array structure and semiconductor integrated circuit apparatus incuding the same KR20140001482A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9390812B2 (en) 2014-07-01 2016-07-12 Samsung Electronics Co., Ltd. E-fuse test device and semiconductor device including the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9390812B2 (en) 2014-07-01 2016-07-12 Samsung Electronics Co., Ltd. E-fuse test device and semiconductor device including the same

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