KR20130136792A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20130136792A
KR20130136792A KR1020120060477A KR20120060477A KR20130136792A KR 20130136792 A KR20130136792 A KR 20130136792A KR 1020120060477 A KR1020120060477 A KR 1020120060477A KR 20120060477 A KR20120060477 A KR 20120060477A KR 20130136792 A KR20130136792 A KR 20130136792A
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South Korea
Prior art keywords
pattern
semiconductor pattern
forming
dummy gate
gate pattern
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KR1020120060477A
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Korean (ko)
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김진범
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삼성전자주식회사
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Publication of KR20130136792A publication Critical patent/KR20130136792A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The present invention provides a method for manufacturing a semiconductor component capable of improving the reliability of a transistor by forming a selective epitaxial film comprising a SiC epitaxial layer on a source and/or a drain of the transistor. The method for manufacturing the semiconductor component comprises forming first and second dummy gate patterns on a first active area and a second active area of a substrate; forming a first semiconductor pattern comprising a first SiC epitaxial layer on the first active area of both sides of the first dummy gate pattern; forming a second semiconductor pattern comprising a second SiC epitaxial layer on the second active area of both sides of the second dummy gate pattern; and forming a first silicide film and a second silicide film by siliciding a first upper semiconductor pattern and a second upper semiconductor pattern. The first semiconductor pattern comprises the first upper semiconductor pattern and a first lower semiconductor pattern formed on an upper part and a lower part of the first SiC epitaxial layer. The second semiconductor pattern comprises a second upper semiconductor pattern and a second lower semiconductor pattern formed on an upper part and a lower part of the second SiC epitaxial layer.

Description

Method for fabricating semiconductor device

The present invention relates to a method of manufacturing a semiconductor device.

Due to the development of electronic technology, down-scaling of semiconductor devices is rapidly progressing in recent years. The downscaled semiconductor devices are increasingly required to operate at high speed. Various studies are underway to optimize the structure of a transistor capable of operating a semiconductor device at high speed and to ensure reliability.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device manufacturing method capable of improving the reliability of a transistor by forming a selective epitaxial film including a silicon carbide (SiC) epitaxial layer on the source and / or drain of the transistor.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

An aspect of the method of manufacturing a semiconductor device of the present invention for solving the above problems is to form first and second dummy gate patterns in the first and second active regions on the substrate, respectively, and both sides of the first dummy gate pattern. Forming a first semiconductor pattern including a first silicon carbide (SiC) epitaxial layer in a first active region of the first semiconductor pattern, wherein the first semiconductor pattern is formed above and below the first silicon carbide epitaxial layer, respectively; A second semiconductor pattern including a first upper semiconductor pattern and a first lower semiconductor pattern and including a second silicon carbide epitaxial layer in second active regions on both sides of the second dummy gate pattern, and forming the second semiconductor pattern And a second upper semiconductor pattern and a second lower semiconductor pattern respectively formed on the upper and lower portions of the second silicon carbide epitaxial layer. By silicidation of the second upper semiconductor pattern comprises forming each of the first silicide layer and a second silicide film.

In the present embodiment, the first silicide layer and the second silicide layer are in direct contact with the first silicon carbide epitaxial layer and the second silicon carbide epitaxial layer, respectively.

The forming of the first semiconductor pattern may include forming a first recess by etching first active regions on both sides of the first dummy gate pattern, and forming the first lower semiconductor pattern on the first recess. Forming a first silicon carbide epitaxial layer on the first lower semiconductor pattern, and at least partially overlapping a side surface of the first dummy gate pattern on the first silicon carbide epitaxial layer 1 forming an upper semiconductor pattern.

In example embodiments, the forming of the second semiconductor pattern may include etching second active regions on both sides of the second dummy gate pattern to form a second recess, and forming the second lower semiconductor pattern on the second recess. Forming a second silicon carbide epitaxial layer on the second lower semiconductor pattern, and at least partially overlapping a side surface of the second dummy gate pattern on the second silicon carbide epitaxial layer 2 forming the upper semiconductor pattern.

In the present exemplary embodiment, at least one of the first lower semiconductor pattern and the second lower semiconductor pattern is formed to be raised from an upper surface of the substrate.

In the present embodiment, the first gate pattern and the second gate pattern are formed between forming the first semiconductor pattern and the second semiconductor pattern and forming the first silicide film and the second silicide film. It includes more.

In example embodiments, the forming of the first gate pattern and the second gate pattern may include removing the first dummy gate pattern and the second dummy gate pattern to form a first trench and a second trench, respectively. And sequentially forming a gate insulating film and a gate electrode in the first trench and the second trench, respectively.

In this embodiment, the distance from the substrate to the upper surface of the first upper semiconductor pattern is equal to the distance from the substrate to the upper surface of the first gate pattern, and the distance from the substrate to the upper surface of the second upper semiconductor pattern is It is equal to the distance from the substrate to the upper surface of the second gate pattern.

In the present embodiment, forming the first silicide layer and the second silicide layer removes a portion of the first gate pattern and the second gate pattern to form a first recess and a second recess, respectively. Filling the first recess and the second recess to form first and second blocking insulating layers covering upper surfaces of the first gate pattern and the second gate pattern, respectively.

In an embodiment, a first blocking layer covering the second dummy gate pattern and the second region is formed, and the first semiconductor pattern is formed in first active regions on both sides of the first dummy gate pattern. And forming a second blocking film covering the first dummy gate pattern and the first semiconductor pattern, and forming the second blocking film, and then forming the first blocking film formed on the second active regions on both sides of the second dummy gate. The second semiconductor pattern is formed on both sides of the second dummy gate pattern from which the first blocking layer is removed.

Other specific details of the invention are included in the detailed description and drawings.

1 to 9 are intermediate steps for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
10 is a block diagram of a memory card including a semiconductor device according to an embodiment of the present invention.
11 is a block diagram of an information processing system using a semiconductor device according to an embodiment of the present invention.
12 is a block diagram of an electronic device including a semiconductor device according to an embodiment of the present invention.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout.

When an element is referred to as being "connected to" or "coupled to" with another element, it may be directly connected to or coupled with another element or through another element in between. This includes all cases. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout. "And / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, with reference to FIGS. 1 to 9, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described.

1 to 9 are intermediate steps for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, referring to FIG. 1, the first dummy gate pattern 100a is formed on the first active region I on the substrate 10, and the second dummy gate pattern 200a is formed on the second active region II. ) Can be formed. First spacers 150 may be further formed on both sides of the first dummy gate pattern 100a, and second spacers 250 may be further formed on both sides of the second dummy gate pattern 200a. The first blocking layer 30 may be formed to cover the second dummy gate pattern 200a and the second active region II. The first recesses 110t may be formed by etching the first active regions I on both sides of the first dummy gate pattern 100a where the first blocking layer 30 is not formed.

The first blocking layer 30 serves to prevent the second dummy gate pattern 200a and the second active region II from being etched in the etching process for forming the first recess 110t. The first blocking layer 30 is illustrated as being conformally formed on the second dummy gate pattern 200a and the second active region II, but is not limited thereto. For example, the first recess 110t may have a sigma shape in Greek. However, this is only for the purpose of explanation of the present invention, and therefore, it may have a box shape, for example. The first recess 110t may be formed by, for example, removing part of the first active region I through dry etching and performing wet etching.

The substrate 10 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 10 may be a silicon substrate or may include other materials such as silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonium It is not limited to this.

The first and second dummy gate patterns 100a and 200a may include a dummy insulating film, a dummy gate electrode, and a dummy mask. The dummy insulating layer may include, for example, one of a silicon oxide layer (SiO 2 ), a silicon oxynitride layer (SiON), and a combination thereof. The dummy insulating film may be formed using, for example, heat treatment, chemical treatment, atomic layer deposition (ALD) or chemical vapor deposition (CVD). For example, the dummy gate electrode may include polycrystalline silicon (poly Si), amorphous silicon (a-Si), polycrystalline silicon germanium (p-SiGe), amorphous silicon germanium (a-SiGe), and polycrystalline germanium (p-Ge). ), Amorphous germanium (a-Si), and combinations thereof. Polycrystalline silicon, silicon germanium and germanium may be formed using, for example, a CVD method, and amorphous silicon, silicon germanium and germanium may be formed using, for example, sputtering, CVD, plasma deposition, or the like. It may be formed by, but is not limited thereto. The dummy mask may include, for example, at least one of silicon nitride, silicon oxide, and silicon carbide (SiC). The hard mask film may be formed using, for example, chemical vapor deposition. In addition, the first spacer 150 and the second spacer 250 may include, for example, silicon oxide, silicon nitride, and silicon oxynitride. Although the spacers 140 and 150 are illustrated in a single layer in the drawings, the spacers 140 and 150 are not limited thereto, and may be formed of a plurality of layers.

The first blocking layer 30 may include, for example, at least one of silicon nitride and silicon oxide. The first blocking layer 30 may be formed by, for example, an ALD method, but is not limited thereto.

Referring to FIG. 2, the first semiconductor pattern 110 including the first silicon carbide (SiC) epitaxial layer 110b may be formed in the first active region I on both sides of the first dummy gate pattern 100a. Can be. That is, the first semiconductor pattern 110 may be formed in the first recess 110t. The first semiconductor pattern 110 includes a first lower semiconductor pattern 110a, a first silicon carbide epitaxial layer 110b, and a first upper semiconductor pattern 110c that are sequentially formed. Specifically, the first lower semiconductor pattern 110a is formed in the first recess 110t, and the first silicon carbide epitaxial layer 110b is successively formed on the first lower semiconductor pattern 110a. Thereafter, a first upper semiconductor pattern 110c is formed on the first silicon carbide epitaxial layer 110b to contact the side surface of the first dummy gate pattern 100a, that is, at least a portion of the first spacer 150. An upper surface of the first upper semiconductor pattern 110c may be coplanar with an upper surface of the first dummy gate pattern 100a, but is not limited thereto. That is, the distance from the top surface of the substrate 10 to the top surface of the first upper semiconductor pattern 110c may be smaller than the distance from the top surface of the substrate 10 to the top surface of the first dummy gate pattern 100a. Here, the contact of the first upper semiconductor pattern 110c at least in part with the side surface of the first dummy gate pattern 100a means that the first semiconductor pattern 110 is formed by being raised from the upper surface of the substrate 10. .

Referring to FIG. 3, a second blocking layer 40 is formed on the first active region I to cover the first dummy gate pattern 100a and the first semiconductor pattern 110. The second recesses 210t may be formed by etching the second active regions II on both sides of the second dummy gate pattern 200a where the second blocking layer 40 is not formed. That is, the second blocking layer 30t may be formed by removing the first blocking layer 30 formed on the second active region II on both sides of the second dummy gate pattern 200a. By the etching process of forming the second recess 210t, the first blocking layer 30 may remain only on the second dummy gate pattern 200a, but is not limited thereto. That is, the top surface of the second dummy gate pattern 200a may be exposed, or the second blocking film 40 may be further formed on the first blocking film 30. This may vary depending on the shape of the photoresist pattern formed on the substrate to form the second recess 210t.

Unlike the first recess 110t, the second recess 210t may have, for example, a box shape, but is not limited thereto. When the second recess 210t has a box shape, the second recess 210t may be formed by, for example, dry etching.

Referring to FIG. 4, a second semiconductor pattern 210 including the second silicon carbide epitaxial layer 210b may be formed in the second active region II on both sides of the second dummy gate pattern 200a. That is, the second semiconductor pattern 210 may be formed in the second recess 210t. The second semiconductor pattern 210 includes a second lower semiconductor pattern 210a, a second silicon carbide epitaxial layer 210b, and a second upper semiconductor pattern 210c that are sequentially formed. In detail, the second lower semiconductor pattern 210a is formed in the second recess 210t, and the second silicon carbide epitaxial layer 210b is successively formed on the second lower semiconductor pattern 210a. Thereafter, a second upper semiconductor pattern 210c is formed on the second silicon carbide epitaxial layer 210b to contact the side surface of the second dummy gate pattern 200a, that is, at least a part of the second spacer 250. An upper surface of the second upper semiconductor pattern 210c may be coplanar with an upper surface of the second dummy gate pattern 200a, but is not limited thereto. That is, the distance from the upper surface of the substrate 10 to the upper surface of the second upper semiconductor pattern 210c may be smaller than the distance from the upper surface of the substrate 10 to the upper surface of the second dummy gate pattern 200a.

Hereinafter, structures and materials of the first semiconductor pattern 110 and the second semiconductor pattern 210 will be described.

Referring to FIG. 4, the first lower semiconductor pattern 110a and the second lower semiconductor pattern 210a may be formed by being raised from the upper surface of the substrate 10, but are not limited thereto. In other words, at least one of the first lower semiconductor pattern 110a and the second lower semiconductor pattern 210a may be formed by being raised from the upper surface of the substrate 10, but the first lower semiconductor pattern 110a and the second lower semiconductor may be formed. All upper surfaces of the patterns 210a may be lower than the upper surface of the substrate 10. The positions of the upper surfaces of the first lower semiconductor pattern 110a and the second lower semiconductor pattern 210a determine the positions at which the first silicon carbide epitaxial layer 110b and the second silicon carbide epitaxial layer 210b are formed. Done. The first silicon carbide epitaxial layer 110b and the second silicon carbide epitaxial layer 210b may be formed at, for example, a position of 10 nm above and below the top surface of the substrate 10, but is not limited thereto. no.

For example, if a PMOS is formed in the first active region I, the first lower semiconductor pattern 110a may be a silicon germanium epitaxial film, and the first upper semiconductor pattern 110c may be silicon or silicon germanium epitaxial. It may be a selective film. The first semiconductor pattern 110 may include p-type impurities. Specifically, the p-type impurity may be boron (B), but is not limited thereto. If an NMOS is formed in the second active region II, the second lower semiconductor pattern 210a and the second upper semiconductor pattern 210c may be silicon epitaxial layers. The first semiconductor pattern 110 may include n-type impurities. Specifically, the n-type impurity may be phosphorus (P) or arsenic (As), but is not limited thereto. The concentration of carbon included in the first silicon carbide epitaxial layer 110b and the second silicon carbide epitaxial layer 210b may be, for example, 1E18 to 1E22, but is not limited thereto. The first silicon carbide epitaxial layer 110b and the second silicon carbide epitaxial layer 210b may be formed to have a thickness of, for example, 1 nm to 10 nm.

Referring to FIG. 5, an interlayer insulating layer 300 may be formed on the substrate 10. The interlayer insulating layer 300 may cover the first dummy gate pattern 100a, the second dummy gate pattern 200a, the first semiconductor pattern 110, and the second semiconductor pattern 210. For example, the interlayer insulating layer 300 may be formed of silicon oxide or a low dielectric constant material, and may be doped with impurities. The interlayer insulating layer 300 may be formed by, for example, CVD, HDCVD, Sputtering, or Spin-On, but is not limited thereto.

Referring to FIG. 6, the first gate pattern 100 may be formed on the first active region I and the second gate pattern 200 may be formed on the second active region II. In detail, the interlayer insulating layer 300 is planarized to expose the first dummy gate pattern 100a and the second dummy gate pattern 200a. In this case, the planarization process may be performed until the dummy gate electrode is exposed. Thereafter, the first dummy gate pattern 100a and the second dummy gate pattern are removed, and the first trench 100t and the second trench 200t are respectively disposed in the first active region I and the second active region II. ) Can be formed. The substrate 10 may be exposed by the first trench 100t and the second trench 200t, but is not limited thereto. The gate insulating layers 102 and 202 and the gate electrodes 104 and 204 are sequentially formed in the first trench 100t and the second trench 200t, respectively, so as to form a first gate pattern on the first active region I. The second gate pattern 200 may be formed on the 100 and the second active region II.

Referring to FIG. 6, the distance from the substrate 10 to the top surface of the first upper semiconductor pattern 110c is equal to the distance from the substrate 10 to the top surface of the first gate pattern 100. The distance from the upper surface of the second semiconductor pattern 210c to the upper surface of the second gate pattern 200 may be equal to the distance from the substrate 10. However, the present invention is not limited thereto, and upper surfaces of the first upper semiconductor patterns 110c and upper surfaces of the second upper semiconductor patterns 210c may be upper surfaces of the first gate patterns 100 and upper surfaces of the second gate patterns 200, respectively. May be closer to the substrate 10 than to the substrate 10.

The gate insulating layers 102 and 202 may include, for example, high dielectric constant insulating layers. The high dielectric constant insulating film is, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide , Aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate, but is not limited thereto. The high dielectric constant insulating film may be formed using, for example, CVD, PVD, or ALD.

The gate electrodes 104 and 204 may be formed of a single layer or multiple layers including hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), and alloys thereof. For example, the gate electrodes 104 and 204 may have a five-layer structure of TiN-TaN-TiAl-TiN-Ti / Al. Gate electrodes 104 and 204 may be formed using, for example, CVD, PVD or ALD.

Referring to FIGS. 7 and 8, a portion of the first gate pattern 100 and the second gate pattern 200 may be removed by a metal pull back process, and the third recess 100r and the third recess 100r may be removed. Four recesses 200r can be formed, respectively. The first blocking insulating layer 120 and the second blocking insulating layer 220 may be formed to fill the third recess 100r and the fourth recess 200r, respectively. The first blocking insulating layer 120 may cover the top surface of the recessed first gate pattern 100, and the second blocking insulating layer 220 may cover the top surface of the recessed second gate pattern 200. By the planarization process, the top surfaces of the first blocking insulating layer 120 and the second blocking insulating layer 220 may be, for example, coplanar with the top surfaces of the first semiconductor pattern 110 and the second semiconductor pattern 210. May be, but is not limited thereto. The blocking insulating layers 120 and 220 may include, for example, silicon nitride (SiN). By the first blocking insulating layer 120 and the second blocking insulating layer 220, the first gate pattern 100 and the second gate pattern 200 may not be exposed, and thus may be protected from an external chemical.

Referring to FIG. 9, the first upper semiconductor pattern 110c and the second upper semiconductor pattern 210c may be silicided to form a first silicide layer 130 and a second silicide layer 230, respectively. The first silicide layer 130 and the second silicide layer 230 may be in direct contact with the first silicon carbide epitaxial layer 110b and the second silicon carbide epitaxial layer 210b, respectively, but are not limited thereto. In this case, all of the first upper semiconductor pattern 110c and the second upper semiconductor pattern 210c are silicide layers, and the first silicide layer 130 and the second silicide layer 230 are formed, respectively.

Specifically, a metal layer (not shown) is formed on the first upper semiconductor pattern 110c and the second upper semiconductor pattern 210c. For example, the metal layer may be formed to a thickness sufficient to silicide the entire first and second upper semiconductor patterns 110c and 210c. The metal layer may include, for example, at least one of Ni, Pt, Hf, W, Co, Al, Pd, Ti, and combinations thereof. Through heat treatment, a reaction with silicide occurs between the semiconductor pattern and the metal layer. In this case, the first upper semiconductor pattern 110c and the second upper semiconductor pattern 210c may both be changed into the first silicide layer 130 and the second silicide layer 230, but are not limited thereto. Thereafter, the unreacted metal layer can be removed. If neither the first upper semiconductor pattern 110c nor the second upper semiconductor pattern 210c is silicided into the first silicide layer 130 and the second silicide layer 230, the first silicide layer may be further heat-treated. The 130 and second silicide layers 230 may directly contact the first silicon carbide epitaxial layer 110b and the second silicon carbide epitaxial layer 210b, respectively.

Hereinafter, an effect obtained by forming a silicon carbide epitaxial layer on the first semiconductor pattern 110 and the second semiconductor pattern 210 will be described.

When recessing the substrate 10 and performing selective epitaxial growth (SEG) on the recessed substrate, a stacking fault may occur at a portion in contact with the gate pattern. For example, unlike the recessed substrate, the cause of the stacking defect may be due to the formation of a spacer, which is an insulating layer, on the sidewall of the gate pattern. As described above, when the semiconductor pattern including the stacking defects is silicided, the stacking defects are used as a fast moving path of the metal atoms, so that the metal atoms can penetrate the source and drain of the transistor. Metal atoms penetrated into the source and drain may inhibit the operation of the transistor, thereby reducing the reliability of the semiconductor device. However, when the silicon carbide epitaxial layer is inserted into the semiconductor pattern, the silicon carbide epitaxial layer may serve to prevent or delay diffusion of metal atoms. Therefore, metal atoms do not penetrate the source and the drain, thereby improving the reliability of the semiconductor device.

10 is a block diagram of a memory card including a semiconductor device manufactured according to embodiments of the present invention.

Referring to FIG. 10, a memory 1210 including a semiconductor device manufactured according to various embodiments of the present disclosure may be employed in the memory card 1200. Memory card 1200 may include a memory controller 1220 that controls the exchange of data between host 1230 and memory 1210. The SRAM 1221 can be used as an operation memory of the central processing unit 1222. [ The host interface 1223 may include a protocol for the host 1230 to connect to the memory card 1200 to exchange data. The error correction code 1224 can detect and correct errors in the data read from the memory 1210. The memory interface 1225 may interface with the memory 1210. The central processing unit 1222 may perform overall control operations associated with the data exchange of the memory controller 1220.

11 is a block diagram of an information processing system using a semiconductor device manufactured according to embodiments of the present invention.

Referring to FIG. 11, the information processing system 1300 may include a memory system 1310 including a semiconductor device manufactured according to various embodiments of the present disclosure. The information processing system 1300 may include a memory system 1310, a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350, electrically connected to the system bus 1360. Can be. The memory system 1310 may include a memory 1311 and a memory controller 1312, and may have substantially the same configuration as the memory card 1200 illustrated in FIG. 24. Data processed by the central processing unit 1330 or data received from an external device may be stored in the memory system 1310. The information processing system 1300 may be applied to memory cards, SSDs, camera image sensors, and various other chipsets. For example, the memory system 1310 may be configured such that an SSD is employed, and in this case, the information processing system 1300 may process a large amount of data stably and reliably.

12 is a block diagram of an electronic device including a semiconductor device according to example embodiments.

Referring to FIG. 12, the electronic device 1400 may include a semiconductor device manufactured according to various embodiments of the present disclosure. The electronic device 1400 may be used in a wireless communication device (eg, PDA, notebook, portable computer, web tablet, cordless phone, and / or wireless digital music player) or various devices that transmit and receive information in a wireless communication environment. have.

The electronic device 1400 may include a controller 1410, an input / output device 1420, a memory 1430, and a wireless interface 1440. The memory 1430 may include a semiconductor device manufactured according to various embodiments of the present disclosure. The controller 1410 may include a microprocessor, a digital signal processor, or a similar processor. The memory 1430 may be used to store a command (or user data) processed by the controller 1410. The air interface 1440 may be used to exchange data over a wireless data network. The air interface 1440 may include an antenna and / or a wireless transceiver. The electronic device 1400 may use, for example, a third generation communication system protocol such as CDMA, GSM, NADC, E-TDMA, WCDMA, CDMA2000.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

10: substrate 100: first gate pattern
110: first semiconductor pattern 130: first silicide film
200: second gate pattern 210: second semiconductor pattern
230: second silicide film
110b and 210b: silicon carbide epitaxial layer

Claims (10)

Forming first and second dummy gate patterns on first and second active regions on the substrate, respectively,
A first semiconductor pattern including a first silicon carbide (SiC) epitaxial layer is formed in first active regions on both sides of the first dummy gate pattern, and the first semiconductor pattern is formed on an upper portion of the first silicon carbide epitaxial layer. And a first upper semiconductor pattern and a first lower semiconductor pattern respectively formed at the bottom thereof,
A second semiconductor pattern including a second silicon carbide epitaxial layer is formed on second active regions on both sides of the second dummy gate pattern, and the second semiconductor pattern is formed on and under the second silicon carbide epitaxial layer. A second upper semiconductor pattern and a second lower semiconductor pattern respectively formed;
And silicideing the first upper semiconductor pattern and the second upper semiconductor pattern to form a first silicide layer and a second silicide layer, respectively. The method according to claim 1,
And the first silicide layer and the second silicide layer are in direct contact with the first silicon carbide epitaxial layer and the second silicon carbide epitaxial layer, respectively. The method according to claim 1,
The forming of the first semiconductor pattern may include etching first active regions on both sides of the first dummy gate pattern to form a first recess,
Forming the first lower semiconductor pattern in the first recess,
Forming the first silicon carbide epitaxial layer on the first lower semiconductor pattern;
And forming the first upper semiconductor pattern on the first silicon carbide epitaxial layer that is at least partially in contact with a side surface of the first dummy gate pattern. The method according to claim 1,
The forming of the second semiconductor pattern may include etching second active regions on both sides of the second dummy gate pattern to form a second recess.
Forming the second lower semiconductor pattern in the second recess,
Forming the second silicon carbide epitaxial layer on the second lower semiconductor pattern;
And forming the second upper semiconductor pattern on at least a portion of the second dummy gate pattern on the second silicon carbide epitaxial layer. The method according to claim 1,
At least one of the first lower semiconductor pattern and the second lower semiconductor pattern is formed to be raised from an upper surface of the substrate. The method according to claim 1,
Between forming the first semiconductor pattern and the second semiconductor pattern and forming the first silicide film and the second silicide film,
The method of manufacturing a semiconductor device further comprising forming a first gate pattern and a second gate pattern. The method of claim 6,
Forming the first gate pattern and the second gate pattern removes the first dummy gate pattern and the second dummy gate pattern to form a first trench and a second trench, respectively.
And sequentially forming a gate insulating film and a gate electrode in the first trench and the second trench, respectively. The method of claim 6,
The distance from the substrate to the top surface of the first upper semiconductor pattern is equal to the distance from the substrate to the top surface of the first gate pattern,
And a distance from the substrate to an upper surface of the second upper semiconductor pattern is equal to a distance from the substrate to an upper surface of the second gate pattern. The method of claim 6,
Forming the first silicide layer and the second silicide layer removes a portion of the first gate pattern and the second gate pattern to form a first recess and a second recess, respectively.
Forming first and second blocking insulating layers covering the first recess and the second recess to cover upper surfaces of the first gate pattern and the second gate pattern, respectively. The method according to claim 1,
Forming a first blocking layer covering the second dummy gate pattern and the second region,
Forming the first semiconductor pattern on first active regions on both sides of the first dummy gate pattern,
Forming a second blocking layer covering the first dummy gate pattern and the first semiconductor pattern,
After forming the second blocking film, the first blocking film formed on the second active regions on both sides of the second dummy gate is removed,
The second semiconductor pattern is formed on both sides of the second dummy gate pattern from which the first blocking film is removed.
KR1020120060477A 2012-06-05 2012-06-05 Method for fabricating semiconductor device KR20130136792A (en)

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