KR20130134539A - Semiconductor device partially doped single graphene by using palladium-hydrogen system and method of manufacturing the same - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor device having excellent stability and productivity through a simple lithography process with graphene having good electrical conductivity and palladium allowing easy exchange of electrons with the graphene and a semiconductor device manufactured by the method. The method for manufacturing a semiconductor device according to the present invention comprises the steps of forming a groove in a substrate and sequentially laminating a gate electrode and a dielectric inside the groove; applying graphene on the substrate to touch the upper surface of the dielectric; patterning the applied graphene in a desired shape using a lithography process; applying photoresist to the substrate so that palladium can be coated on a part of the patterned graphene and then patterning the photoresist through the lithography process; depositing the palladium on the patterned photoresist to coat the palladium on a part of the graphene; removing all photoresist and palladium except for the palladium coated on the part of the graphene; and forming a source electrode and a drain electrode to be connected to both sides of the graphene.

Description

TECHNICAL FIELD The present invention relates to a semiconductor device formed through partial doping of graphene using a palladium-hydrogen system and a method of manufacturing the same.

The present invention relates to a semiconductor device capable of manufacturing a semiconductor device excellent in stability and mass productivity through a simple lithography process using graphene having excellent electrical conductivity and palladium (Pd) A manufacturing method thereof, and a semiconductor device manufactured through the manufacturing method.

Generally, Graphene is a basic form of carbon nanostructure such as carbon nanotube (CNT), fullerene, etc. and has a two-dimensional planar structure of hexagonal structure composed of a single carbon layer. In 2004, Konstantin Novoselov and Andre Geim mechanically peeled the surface layer of graphite through a simple method using the adhesive force of scotch tape to form a two-dimensional hexagonal carbon compound graphene And the field effect characteristics of such graphenes have been reported. Thereafter, attempts have been made to fabricate high-performance transistors using graphene at high operating speeds thereafter.

As it is known, graphene is a two-dimensional carbon nanostructure, and has a charge mobility of about 15,000 cm ² / Vs and is known to have a very high thermal conductivity. Because of this, graphene is now attracting attention as a next-generation material to replace silicon materials used in field effect transistors. In particular, when a carbon nano tube (CNT) is used in the manufacture of a transistor, it is difficult to integrate a large area, but when a graphen material is used, a device can be easily manufactured using a conventional semiconductor process technology There is an advantage.

However, the graphen having a single carbon layer as described above is very popular as a next-generation new material due to many excellent electrical, mechanical and thermal properties. However, since the electrical properties are very uniform and the structure of the carbon lattice is very parallel, there is no band-gap and thus it is difficult to apply the semiconductor device to the semiconductor device.

That is, the graphene is semimetal having a band gap of '0' and has a disadvantage in that the off current is very large, and thus the on / off ratio of the operating current is very small . The on / off ratio of the field effect transistor using semimetal graphenes known to date is about 6. This low ON / OFF ratio is a problem in mass integration of field effect transistor elements and high-speed driving.

In recent years, attempts have been made to increase the on / off ratio of such an operating current. One of these attempts is to produce graphene in a semiconductor state with an appropriate bandgap to produce an efficient field effect. HaoLi Zhang et al. Of Lanzhou University in China have proposed a method of increasing the on / off ratio by simulating a nano-ribbon tunnel transistor model using semiconductor graphene. In addition, Lemme et al. Produced a nonvolatile field effect switching device having a very large on / off ratio by changing the chemical composition of the graphene. Thus, the graphene layer having a bandgap can be realized by, for example, disrupting the symmetry of the graphene crystal structure, which is represented by lattice mismatch between graphene and the substrate, or by forming a pattern in the form of a nanoribbon, And the like.

However, it is not easy to form such graphene in the shape of a nano-size, and it is not easy to form graphene of good quality. Therefore, in spite of excellent characteristics of graphene itself, the integration as a semiconductor device has not been realized yet.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and an object of the present invention is to provide a graphene excellent in electrical conductivity and palladium which is easy to electron- A large number of surplus electrons generated by injecting hydrogen by covering palladium on a portion of the substrate can be partially doped by reacting with the holes in the graphene, thereby generating a concentration gradient of electrons / holes in the graphene, A manufacturing method capable of manufacturing a semiconductor device capable of realizing the same function and capable of manufacturing a semiconductor device having excellent stability and mass productivity through a simple lithography process and a semiconductor device manufactured through the manufacturing method.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a substrate having grooves; A gate electrode formed in the groove and to which a voltage is applied from the outside; A dielectric layer in contact with the gate electrode and formed in the groove; A graphene layer formed on an upper surface of the substrate so as to contact the upper surface of the dielectric layer and over the groove portion; A palladium layer deposited on a part of the graphene layer and reacting with hydrogen introduced from the outside to emit electrons; And a source electrode and a drain electrode stacked on the substrate so as to be connected to both ends of the graphene layer, respectively.

At this time, two grooves are formed on the substrate and spaced apart from each other at a predetermined interval, and the palladium layer may be deposited on the graphene layer region located on one of the two grooves.

Alternatively, three grooves may be formed on the substrate, spaced apart from each other by a predetermined distance, and the palladium layer may be deposited on the graphene layer region located above the central groove of the three grooves. have.

Alternatively, three grooves may be formed on the substrate and spaced apart from each other by a predetermined distance, while the palladium layer may be formed on the graphene layer region located above the two grooves of the three grooves have.

The gas environment may be established such that the concentration of hydrogen reacting with the palladium layer has a hydrogen concentration in the range of 0 to 200 ppm.

At this time, it is preferable that the semiconductor device is operated in a state exposed to a hydrogen concentration environment of 50 ppm or more.

When hydrogen is forcedly injected into the palladium layer and operated, it is preferable that hydrogen is injected into the palladium layer through a mass flow controller (MFC).

On the other hand, as the substrate that can be employed in the present invention, a silicon substrate having a silicon oxide film formed thereon can be employed.

In addition, the source, drain, and gate electrodes formed on the substrate may be formed of gold (Au).

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, including: (a) sequentially forming a gate electrode and a dielectric in a groove in a substrate; (b) applying graphene on the substrate to be in contact with the top surface of the dielectric; (c) patterning the applied graphene into a desired shape using a lithography process; (d) applying a photoresist on the substrate so that palladium can be coated on a part of the patterned graphene, and then patterning the photoresist through a lithography process; (e) depositing palladium on the patterned photoresist to coat palladium on a portion of the graphene; (f) removing all photoresist and palladium except palladium coated on a portion of the graphene; And (g) forming a source electrode and a drain electrode to be connected to both sides of the graphene.

At this time, as a step before the step (b), the upper surface of the dielectric and the upper surface of the substrate may be flattened by a polishing process.

In the step (b), the application of the graphene may be performed by a chemical vapor deposition (CVD) method.

Alternatively, in the step (b), the graphene may be applied by spin coating a graphene oxide.

In addition, the removal of the photoresist and the palladium in the step (f) may be performed through a lift-off process.

On the other hand, it is also possible to manufacture a gas sensor having excellent stability and performance by applying the above-described method for manufacturing a semiconductor device of the present invention.

According to the present invention having the above-described structure, a part of graphene having excellent electrical conductivity is coated with palladium which is easy to electron donate, and a large amount of surplus electrons generated by injecting hydrogen into palladium reacts with holes of the graphene, It is possible to manufacture a semiconductor element having the function of a PN diode by producing a concentration gradient of electrons / holes in the graphene, and by using a simple lithography process, a semiconductor having excellent stability and mass productivity There is an advantage that a device can be manufactured.

1 is a cross-sectional view illustrating a PN type semiconductor device according to an embodiment of the present invention;
FIG. 2 is a manufacturing process diagram sequentially showing a process of manufacturing the PN type semiconductor device shown in FIG. 1; FIG.
FIGS. 3 to 6 are conceptual diagrams sequentially illustrating a process of forming a PN type semiconductor device by forming a concentration gradient of electrons / holes in the graphene by reaction of palladium and hydrogen applied to a part of the graphene.
7 is a graph showing a change in resistance due to a difference in electron / hole concentration in a single graphene.
8 is a cross-sectional view illustrating a PNP-type semiconductor device according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a P-N junction semiconductor device according to an embodiment of the present invention.

1, a semiconductor device 100 according to the present invention includes a silicon substrate 102 on which grooves 104a and 104b are formed, a gate electrode 104a and 104b formed in the grooves 104a and 104b, A dielectric layer 120a and a dielectric layer 120b formed in the grooves 104a and 104b to be in contact with upper surfaces of the gate electrodes 110a and 110b; A palladium layer 140 deposited on a portion of the graphene layer 130 and a second electrode layer 140 disposed on the first surface of the silicon substrate 102 in contact with the upper surface of the second electrode layer 120b, And a source electrode 150 and a drain electrode 160 patterned on the silicon substrate 102 to be connected to both ends of the gate electrode 130, respectively.

The silicon substrate 102 is a substrate in which a silicon oxide film (SiO ₂ ) is stacked. At the center of the silicon substrate 102, two recesses 104a and 104b are formed with a predetermined width and depth from the upper surface.

At this time, two grooves 104a and 104b formed in the silicon substrate 102 are formed at regular intervals from each other. Inside each of the grooves 104a and 104b, a gate electrode 110a (110b) are formed.

Here, when the grooves 104a and 104b are formed in the silicon substrate 102, the shape of the gate electrodes 110a and 110b is firstly patterned on the silicon substrate 102 by using a lithography method, The patterned portions are etched by dry etching to form grooves 104a and 104b for forming the gate electrode. The gate electrodes 110a and 110b and the dielectric layers 120a and 120b are sequentially stacked in the grooves 104a and 104b formed through the lithography process.

After the gate electrodes 110a and 110b and the dielectric layers 120a and 120b are stacked in the grooves 104a and 104b of the silicon substrate 102 as described above, the dielectric layers 120a and 120b And the upper surface of the silicon substrate 102 can be maintained in a horizontal plane flattened to each other by a separate polishing process.

The gate electrodes 110a and 110b may be formed of various metal materials such as Pt, Au, Pd, Ag, Ni, Cr, or a conductive metal. And the gate electrodes 110a and 110b are formed of gold (Au).

The graphene layer 130 is a layer in which a graphene material having a two-dimensional planar coupling structure is deposited in the form of a thin film. The graphene layer 130 is formed of two And is deposited on the substrate with a constant area so that the regions of the grooves 104a and 104b can all be covered. The lower surface of the graphene layer 130 deposited on the silicon substrate 102 is kept in contact with the upper surface of the dielectric layers 120a and 120b formed in the grooves 104a and 104b.

When a graphene layer 130 is formed on the silicon substrate 102, a chemical vapor deposition (CVD) method may be used, or a graphene oxide in an aqueous solution state may be spin coated on the silicon substrate 102 ).

Since the graphenes have a two-dimensional planar structure, the graphenes can be deposited on the entire surface of the silicon substrate 102 in the form of a thin film, and the graphenes can be deposited at desired positions on the silicon substrate 102 After depositing the graphene in a thin film form, the graphene can be realized by patterning the deposited graphene in a necessary form.

The palladium layer 140 is a layer on which palladium Pd is deposited, which is a metal material that facilitates electron exchange with hydrogen (H ₂ ). The palladium layer 140 is formed on two grooves 104a) 104b in the region of the graphene layer 130 located in the upper portion of the one groove 104a.

When hydrogen is added to the palladium deposited on a part of the graphene layer 130 as described above, the palladium reacts with hydrogen to release excess electrons, and as the surplus electrons thus released gradually increase, the graphene layer Type semiconductor with many electrons / holes and a concentration gradation of electrons / holes by changing to N-type semiconductors with many electrons. Thus, the same characteristics as those of a PN junction diode in which a P-type semiconductor and an N-type semiconductor are bonded to each other Have

The source electrode 150 and the drain electrode 160 are patterned on the silicon substrate 102 such that the source electrode 150 and the drain electrode 160 are partially in contact with both ends of the graphene layer 130 and are electrically connected to each other.

The source electrode 150 and the drain electrode 160 may be formed using various metal materials such as Pt, Au, Pd, Ag, Ni, Cr, or a conductive metal such as the gate electrodes 110a and 110b In this embodiment, the source electrode 150 and the drain electrode 160 are formed of gold (Au).

As described above, according to the present invention, a palladium material that is easy to electronically exchange with graphene is coated on a part of graphene, and many surplus electrons generated by reacting the palladium with hydrogen react with holes distributed on the surface of the graphene So that a concentration gradient of electrons / holes is generated in the graphene layer 130 to realize a PN junction type semiconductor device. At this time, a forward or reverse voltage is applied to the P-type graphene portion P and the N-type graphene portion N through the gate electrodes 110a and 110b of the semiconductor device 100 to perform a rectifying action or a switching action The characteristics of the PN diode can be given.

Meanwhile, FIG. 2 is a manufacturing process diagram sequentially illustrating a process of manufacturing the semiconductor device of the present invention shown in FIG. 1.

As shown in FIG. 2, first, a gate electrode pattern is patterned on a silicon substrate 102 through a lithography process, and then the patterned portion is etched by dry etching to form a gate electrode And the gate electrodes 110a and 110b and the dielectric layers 120a and 120b are sequentially stacked in the grooves 104a and 104b to form the grooves 104a and 104b,

The gate electrodes 110a and 110b and the dielectric layers 120a and 120b are formed in the grooves 104a and 104b of the silicon substrate 102 and then the dielectric layers 120a and 120b are formed It is preferable to polish the surface evenly through a separate polishing process so that the upper surface and the upper surface of the silicon substrate 102 can maintain a flat horizontal surface.

After the gate electrodes 110a and 110b and the dielectric layers 120a and 120b are formed in the grooves 104a and 104b of the silicon substrate 102, the upper surfaces of the dielectric layers 120a and 120b, The graphene layer 130 is formed by applying graphene on the silicon substrate 102 so as to be in contact with the surface of the silicon substrate 102. (b)

The graphene layer 130 may be formed on the substrate 102 using a chemical vapor deposition (CVD) method or by using a spin coating process using an aqueous solution of graphene oxide And then coating it on the silicon substrate 102.

After the formation of the graphene layer 130 on the silicon substrate 102, the graphene layer 130 deposited on the silicon substrate 102 is subjected to lithography to form the gate electrodes 110a and 110b Are completely covered with the grooves 104a and 104b.

Then, photoresist is coated on the silicon substrate 102 so that palladium can be coated on a portion of the graphene layer 130, and patterned in the same manner as in (d) through a lithography process.

Next, palladium (Pd) is deposited on the photoresist layer 132 coated on the silicon substrate 102, palladium is injected into the patterned space portion between the photoresist layers 132 as shown in (e) 130).

Then all palladium and all photoresists except the palladium 140 coated on the graphene layer 130 are removed through a lift-off process. (F)

Finally, when the source electrode 150 and the drain electrode 160 are patterned and electrically connected to both ends of the graphene layer 130 coated with the palladium 140, the graphene layer is partially coated with palladium (G) A PN semiconductor element is completed.

3 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. In FIGS. 3 to 6, when hydrogen is implanted into palladium partially coated on graphene, / Hole concentration gradients are generated to change into P-type graphenes and N-type graphenes.

As shown in FIG. 3, when hydrogen (H ₂ ) is introduced into the palladium layer 140 coated on the upper surface of the graphene layer 130 in the semiconductor device of the present invention, H ₂ + Pd -> PdH _x Through a chemical reaction such as + e ^- , palladium (Pd) turns into PdH _x and releases the surplus electrons (e ^- ). The excess electrons e ^- discharged in this manner do not stay inside the palladium layer 140 and move to the surfaces of the graphene layer 130 and the palladium layer 140. In this way, the graphene layer 130 and the palladium layer 140, The excess electrons e ^- moved to the surface start to react with the surface of the graphene layer 130 having a large number of holes h ⁺ , as shown in FIG. 4, and electrons e ^- The regeneration reaction occurs due to the combination of the electron (e ^- ) and the hole (h ⁺ ). As shown in FIG. 5, a part (left portion) of the graphene layer 130 is in contact with the hole (h ⁺ ) in the graphene layer 130 as electrons (e ^- ) are continuously introduced into the graphene layer 130 from the palladium layer 140. [ the distribution lot number than the electron (e ^{- -)} is changed to the number of forms the number of, such a phenomenon the electron (e) as shown in portion is 6 (left side) of the gras pinned layer 130 in accordance with a period of time lasting Type semiconductor characteristic, and the remaining portion (right portion) of the graphene layer 130 is changed to a graphene region having a p-type semiconductor characteristic with a large number of holes (h ⁺ ) distributed, A PN semiconductor diode device in which a semiconductor and an N-type semiconductor are bonded can be realized. The PN junction semiconductor device thus formed can be realized as a semiconductor device which can perform a rectifying action or a switching action like a general PN diode by applying a forward or reverse voltage to the gate electrodes 110a and 110b .

In the P-N junction semiconductor device of the present invention, it is preferable that a suitable hydrogen concentration to be reacted with the palladium layer 140 is formed within a range of 0 to 200 ppm. In particular, the semiconductor device of the present invention is more preferably operated in a state exposed to a hydrogen environment of 50 ppm or more. For example, by putting the semiconductor device of the present invention into a chamber formed with a hydrogen concentration environment of 50 ppm or more, The function of the semiconductor device can be realized.

When hydrogen is introduced into the palladium layer 140 using a separate input means so that the palladium can react with hydrogen, hydrogen is injected into the palladium layer 140 through a mass flow controller (MFC) So that the semiconductor device can be operated.

7 is a graph showing a resistance change according to a difference in electron / hole concentration in a single graphene layer of the semiconductor device of the present invention. As shown in the graph of FIG. 7, It was confirmed that a concentration gradient of electrons / holes was generated in the graphene layer 130 even in a low-concentration hydrogen environment.

On the other hand, FIG. 8 shows a P-N-P type transistor device constructed by applying the principle of the P-N semiconductor device of the present invention described above.

8, the PNP transistor semiconductor device according to the present invention includes three grooves 104a, 104b and 104c spaced apart from each other by a predetermined distance on a silicon substrate 102, After forming the gate electrodes 110a, 110b and 110c and the dielectric layers 120a, 120b and 120c in the grooves 104a, 104b and 104c, the dielectric layers 120a, 120b and 120c, A graphene layer 130 is simultaneously formed on the three grooves 104a, 104b and 104c so as to be in contact with the upper surface of the grooves 104a, 104b and 104c, A PNP transistor device can be manufactured by depositing a palladium layer 140 on a region of the graphene layer 130 located in a portion of the substrate.

As described above, the present invention provides a method of manufacturing a semiconductor device, which comprises a graphene having excellent electrical conductivity and palladium (Pd) which is easy to electronically exchange with the graphene, and a part of the graphene is coated with palladium Many surplus electrons generated by implantation react with the holes of the graphenes and can be partially doped, thereby generating electron / hole concentration gradients in the graphene, thereby forming on / off devices and various logic circuits And a semiconductor device having excellent stability and mass productivity can be manufactured by using a simple lithography process.

Since the graphene itself applied to the semiconductor device of the present invention is formed of a two-dimensional planar material, there is an advantage that it can be deposited on the entire surface of the silicon substrate 102, The graphene film may be deposited at a desired position and then patterned into a desired shape so that the graphene lead can be wired. Palladium (Pd) is deposited on the required portion of the wired graphene wire by a lithography method, There is an advantage that a plurality of PN diodes can be disposed on the pin lead to implement the graphene lead wire circuit.

In addition, the semiconductor device of the present invention having the above-described structure can be used as a gas sensor capable of measuring the concentration of gas (hydrogen). When the semiconductor device of the present invention is exposed to a gas environment, The concentration of the gas can be measured by measuring the rate of change of the conductivity of the graphene in the coated portion and the uncoated portion, which is advantageous in application to a stable sensor.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limited to the embodiments set forth herein. Will be possible.

100: semiconductor element 102: silicon substrate
104a, 104b: grooves 110a, 110b: gate electrode
120a, 120b: dielectric layer 130: graphene layer
140: palladium layer 150: source electrode
160: drain electrode

Claims (15)

A groove-formed substrate;
A gate electrode formed in the groove and having a voltage applied from the outside;
A dielectric layer in contact with the gate electrode and formed in the groove;
A graphene layer formed on an upper surface of the substrate to contact the upper surface of the dielectric layer and to cover the groove portion;
A palladium layer deposited on a portion of the graphene layer and reacting with hydrogen introduced from the outside to emit electrons;
A source electrode and a drain electrode stacked on the substrate so as to be connected to both ends of the graphene layer;
And a semiconductor element
[2] The method of claim 1, wherein the grooves are formed with two spaced apart spaces, and the palladium layer is deposited on the graphene layer region located on one of the two grooves, Semiconductor device.
2. The semiconductor device according to claim 1, wherein the grooves are formed in three spaced apart spaces, and the palladium layer is deposited and formed on a graphene layer region located above the central groove of the three grooves. device
[3] The method of claim 1, wherein the grooves are three spaced apart from each other at a predetermined interval, and the palladium layer is deposited and formed on the graphene layer region located above the two grooves of the three grooves, A semiconductor element
The semiconductor device of claim 1, wherein a concentration of hydrogen reacting with the palladium layer is in a range of 0 to 200 ppm.
The semiconductor device according to claim 1, wherein the semiconductor device is operated in a state exposed to a hydrogen concentration environment of 50 ppm or more.
The method according to claim 1, wherein hydrogen is supplied to the palladium layer through a mass flow controller (MFC).
The semiconductor device according to claim 1, wherein the substrate is a silicon substrate having a silicon oxide film formed thereon
The semiconductor device according to claim 1, wherein the source, drain, and gate electrodes are made of gold (Au).
(a) sequentially forming a gate electrode and a dielectric in the groove after forming a groove in the substrate;
(b) applying graphene on the substrate to be in contact with the top surface of the dielectric;
(c) patterning the applied graphene into a desired shape using a lithography process;
(d) applying a photoresist on the substrate so that palladium can be coated on a part of the patterned graphene, and patterning the photoresist through a lithography process;
(e) depositing palladium on the patterned photoresist to coat palladium on a portion of the graphene;
(f) removing all photoresist and palladium except palladium coated on a portion of the graphene;
(g) forming a source electrode and a drain electrode to be connected to both sides of the graphene;
Wherein the semiconductor device is a semiconductor device.
The manufacturing method of a semiconductor device according to claim 10, further comprising a step of polishing the upper surface of the dielectric and the upper surface of the substrate through a polishing process as a step before the step (b) Way.
[10] The method of claim 10, wherein the application of the graphene is performed by a chemical vapor deposition (CVD) method in the step (b).
The method of claim 10, wherein the application of the graphene in step (b) is performed through a spin coating process of graphene oxide.
11. The method of claim 10, wherein the step (f) is performed through a lift-off process.
A gas sensor manufactured by the method for manufacturing a semiconductor device of claim 10

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