KR20130133105A - Total pon mac apparatus and total pon olt system using the same - Google Patents

Abstract

The present invention relates to an integrated passive optical network MAC processor and an integrated passive optical network optical line terminal system using the same which is capable of providing both a current 1G passive optical network and a future 10G passive optical network in one device. The integrated passive optical network optical line terminal system of the present invention comprises: a plurality of user network interface cards which supports various passive optical network (PON) protocols; a plurality of service network interface cards which supports various PON protocols; and a main processor and a switching block which are connected to each of the user network interface cards and each of the service network interface cards through a differential mode signal line to recover a received packet, provide a packet switching function according to the header information of the packet, and include a CPU and a main switching fabric. The user network interface cards and the service network interface cards execute a passive optical network protocol designated in the initial configuration among the passive optical network protocols and include a storage means for storing the state and control resist of each card. The main processor is configured to execute an operation management program for failure management, configuration management, and performance management and perform reading and writing, through an external bus, on the storage means for storing the state and control resist of the main processor. [Reference numerals] (11,13) Main CPU;(12,14) L2/L3 switching block (480G);(15,16) G/E-PON MAC processing unit;(17,18) NG-PON MAC processing unit;(31) L2 switch;(34) Multiplexing / Demultiplexing unit;(35,36) Optical module

Description

Integrated passive optical network MAC processing device and integrated passive optical network optical line termination system using the same {Total PON MAC apparatus and total PON OLT System using the same}

The present invention relates to an integrated passive optical network (PON) medium access control (MAC) processing apparatus and an integrated passive optical network (PON) optical line termination (OLT) system using the same. The present invention relates to an integrated passive optical network MAC processing apparatus capable of providing both 1G-class and 10G-class passive optical networks being serviced in one device, and an integrated passive optical network optical line termination system using the same.

With the expansion of smart devices such as smart phones and the explosive demand for broadband multimedia such as IPTV (Internet Protocol Television), the advancement of subscriber networks has become a major issue in the telecom industry. In order to advance the existing xDSL (x Digital Subscriber Line) subscriber network, the ultimate goal is to establish the FTTH (Fiber To The Home), which replaces the existing copper wire with an optical cable. Alternative technologies to overcome are attracting attention. Passive optical network (PON) is used as the most economical method of constructing optical subscriber network.

1 is a configuration diagram of one embodiment of a general passive optical network (PON).

As shown in FIG. 1, a general passive optical network (PON) utilizes a passive element such as a passive splitter 2 to share a single fiber 10 with a plurality of subscribers. It has a point-to-multipoint network structure that branches into a plurality of distribution fibers 9. The PON OLT (Optical Line Termination) system 1 is located at the network end point of the optical distribution network (ODN), and the optical network termination (ONT) is located at the subscriber end point. ONT (4 to 8) shown in Figure 1 refers to a single subscriber, in the case of ONU (Optical Network Unit, 3) refers to the equipment that is installed in the inlet of the dense subscribers, such as apartments to accommodate the aggregation function of multiple subscribers, It is in the form of a variety of Layer 2 (L2) switching devices to accommodate existing xDSL or Ethernet subscriber lines prior to full FTTH conversion.

Various methods have been used as a transmission method for exchanging subscriber information between the PON OLT system 1 and the ONU / ONTs 3 to 8. For example, depending on the operator's circumstances, the Gigabit Ethernet PON (GE-PON) method of the IEEE 802.3ah standard or the Gigabit Passive Optical Network (G-PON), an ITU-T G.984 international standard. Most of them use Gigabit-capable PON.

Gigabit Ethernet Passive Optical Network (GE-PON), which provides up to 1Gbps transmission speed for uplink and downlink, has been widely adopted in Japan, Korea, and China because it can accept a variable length Ethernet frame and is relatively inexpensive. . GE-PON can efficiently provide IP services but requires separate devices to provide time division multiplexing (TDM) services, multi-point control protocol (MPCP) overhead and 8B / There is a disadvantage in that transmission efficiency is lowered due to 10B coding.

Gigabit Passive Optical Network (G-PON) technology provides downlink 2.5Gbps / upward 1.25Gbps data rates and uses the newly defined GPON Encapsulation Method (GEM) frame structure to provide variable length IP services and time division multiplexing (TDM) services. Can be provided efficiently. In addition, the G-PON can transmit the ATM (Asynchronous Transfer Mode) protocol used in the mobile communication network without any overhead. G-PON can provide efficient voice service through frame transmission control of 125usec (8kHz) period and is known as a relatively low overhead and efficient system due to Non-Return-to-Zero (NRZ) coding.

Japan and South Korea, the FTTH leaders, are attempting to introduce gigabit-class Internet services beyond the 100Mbps service, and are increasing the number of splitter branches to accommodate more subscribers. In addition, the company is researching and developing technologies that provide gigabit bandwidth per subscriber to realize future IT infrastructure vision such as ultra-wideband, convergence, and intelligence as well as efforts to extend the transmission distance of the existing PON.

In particular, OTT (Over-The-Top) subscribers are increasing more than CATV (Cable Television) subscribers, and IP traffic is increasing tens of times a year with the advent of 3D TVs, smart TVs, and the launch of 4G smartphones. Optical subscriber network needs to be established. The most economical and realistic PON technology for this is the 10G EPON technology under standardization in IEEE 802.3av and XG-PON under standardization in ITU-T G.987.

FIG. 2 is a diagram illustrating a concept of a 10Gbps PON, and FIG. 3 is an explanatory diagram of an optical wavelength used in a PON.

As shown in FIGS. 2 and 3, the upstream (US: Upstream) 1310 nm and the downstream (DS: Downstream) 1490 nm optical wavelengths used in the existing GE-PON and G-PON are 1270 nm and downward for 10G PON. 1577 nm was further allocated. As shown in FIG. 2, the 10G EPON OLT device on the left side must be fully compatible with the existing 1G / 1G EPON ONT / ONU device, and the XG-PON OLT device accommodates 2.5G / 1G GPON ONT / ONU. Should be. There is also the possibility of using OLT / ONT equipment which is asymmetrical in the downward 10G / upward 1G class. Therefore, next-generation 10G PON OLT systems must accommodate all four wavelengths.

However, in the ONT installed at the subscriber or the ONU provided to the dense subscriber, as shown on the right side of FIG. Initially, 10G / 1G will be applied first rather than 10G / 10G, and there will be a demand to use new ONT equipment as well as existing ONT by using one 1G upward. However, depending on the network conditions of the operators, the existing PON network may be maintained mainly for residential subscribers, and 10G / 10G PON may be introduced first for enterprise subscribers.

In addition, as shown in FIG. 3, CATV Overlay (RFOG) technology may be used in the same PON using a wavelength of 1550 nm, and an analog CATV return path of 1610 nm may be used. Is also defined. In addition, 1650 nm is defined as the wavelength for optical cable monitoring using an OTDR (Optical Time Domain Reflectometer).

However, in the case of the 1G grade GE-PON OLT that is already installed and used, the use range of the 1310nm wavelength is widely defined as 1260-1360nm and overlaps with the upward 1270nm of the 10G grade. However, in the case of G-PON, since the specifications of the optical transceiver are more detailed, overlapping does not occur. Therefore, in 10G class GE-PON, uplink traffic uses time division multiplexing (TDM) instead of wavelength division multiplexing. Although the same optical fiber is used, it is impossible to multiplex 1G / 10G upward independently, so it is multiplexed using the TDM method. If 10G and 1G are used in the same PON, although the uplink is 10Gbps, the performance of the 1G-class uplink is increased, the more the performance may be dominant in the 1G class.

10G / 1G PON, 10G / 10G PON, 1G / 1G PON coexist in one fiber, or depending on the technology, many OLT equipments such as GE-PON and G-PON technology, 10G E-PON and XG-PON It must be developed separately.

Therefore, it is a problem of the present invention to solve the problems of the prior art as described above and to meet the needs.

The present invention accommodates both 10G-PON standards XG-PON1 (10G / 2.5G), XG-PON2 (10G / 10G) in one OLT system platform, and 10G / 1G-class 10G EPON or 10G according to user setting conditions Its purpose is to provide an integrated passive optical network MAC processing device that is used in combination with a PON OLT system that can operate as a / 10G-class 10G EPON.

In addition, an object of the present invention is to provide an integrated passive optical network (PON) optical line termination (OLT) system that can be selectively operated as needed by employing the integrated passive optical network MAC processing apparatus as described above.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention which are not mentioned can be understood by the following description, and will be more clearly understood by the embodiments of the present invention. It will also be readily apparent that the objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

The present invention for achieving the above object, a plurality of user network interface card for supporting various passive optical network (PON) protocol; A plurality of service network interface cards for supporting various passive optical network protocols; And between the user network interface card and each service network interface card, recovers the received packet, provides a packet exchange function according to the header information of the packet, and provides a main processor (CPU) and a main switching fabric. And a main process and a switching block, the main process and the switching block comprising 10 Gigabit (10G) Base-KR (IEEE) and each user network interface card and each service network interface card to provide a 10 Gigabit backplane. 802.3ap) via differential mode signal line.

The present invention also provides a plurality of user network interface cards for supporting various passive optical network (PON) protocol; A plurality of service network interface cards for supporting various passive optical network protocols; Connected to each of the user network interface card and each of the service network interface cards through a differential mode signal line to recover a received packet, and provide a packet exchange function according to header information of the packet; A main process and a switching block comprising a main switching fabric, wherein the plurality of user network interface cards and the plurality of service network interface cards execute passive optical network protocols specified during initial configuration of the plurality of passive optical network protocols, Each of the main processor includes a storage means for storing its own state and control registers, and the main processor executes an operation management program for fault management, configuration management, and performance management, and stores its state and control resists through an external bus. In the storage means The letter was made available to read.

In addition, the integrated passive optical network processing apparatus according to the present invention for achieving the above object, the first transmission rate receiver and the second transmission rate receiver for detecting an error-free frame from the signal respectively input from the optical transceiver ; A first upstream MAC processing unit for performing PON MAC protocol processing by analyzing the PON frame received from the first transmission rate receiver; A second upstream MAC processing unit for performing PON MAC protocol processing by analyzing the PON frame received from the second transmission rate receiver; First and second buffers respectively buffering the frames processed by the first and second upward MAC processors; Uplink packet processing means for reading frames stored in the first and second buffers, reconstructing packets through parsing and priority classification, and performing standard protocol processing and scheduling on the reconstructed packets; An uplink transmitter for converting a packet input from the uplink packet processor into an XAUI signal and then converting the packet into a differential mode signal and transmitting the signal to a main process and a switching block; A downlink receiver configured to convert a differential mode signal received from the main process and the switching block into an XAUI signal to form a normal packet; Downlink packet processing means for classifying the packet received from the downlink receiver, performing standard protocol processing and scheduling for downlink traffic, and classifying whether the packet is the first rate packet or the second rate packet; A first frame configuration unit configured to receive a first transmission rate packet from the downlink packet processing means and configure a PON frame suitable for the first transmission rate; A second frame configuration unit configured to receive a second transmission rate packet from the downlink packet processing means and configure a PON frame suitable for the second transmission rate; A first downlink MAC processor for performing downlink MAC protocol processing on the PON frame processed by the first frame configuration unit; A second downlink MAC processor for performing downlink MAC protocol processing on the PON frame processed by the second frame configuration unit; A first downlink transmitter which processes a frame input from the first downlink MAC processor and transfers serialized data to the optical receiver; A second downlink transmitter which processes a frame input from the second downlink MAC processor and transfers serialized data to the optical receiver; And a DBA accelerator for performing a PON DBA (Dynamic Bandwidth Allocation) control function.

Preferably, the integrated passive optical network MAC (MAC) processing apparatus according to the present invention, under the control of the DBA accelerator, performs a self-diagnosis of the optical beam during an empty time period in which user data is not transmitted downward using a received optical wavelength. It further includes an Optical Time Domain Reflectometer (OTDR) processor.

As the speed of traffic increases, the transition to the next-generation PON, which accommodates 10G speed, 40Km long distance transmission and wireless backhaul, will begin, and the development of ubiquitous information and communication environment will increase the demand for high speed access network radically. As expected, 10Gbps PONs are expected to be introduced in the next few years.

The present invention is a total PON OLT system that can simultaneously accommodate one 10G PON and existing 1G PON according to the high speed of the PON, and provides the most common technologies such as GE-PON and G-PON at the same time It can be applied to all access networks. In addition, the present invention can provide a reliable service to the user and expand the service availability by providing an OLT system capable of redundancy of the main components in the OLT system and PON line protection switching.

In addition, the present invention allows one line card configuration and one PON MAC chip to be used in common, rather than implementing the system individually according to various standards and functions. That is, according to the development of chip integration technology, the present invention may integrate one common function and detailed functions into one chip, and correspond to a detailed standard according to a user's request. For this reason, the present invention can produce a single unified product, thereby lowering the manufacturing cost due to the increase in production.

In addition, the present invention generates a pulse by using a 1310nm wavelength used by uplink data of 1G PON, rather than an outband of OTDR (Optical Time Domain Reflectometer) measurement using a wavelength different from that used in the PON. By measuring the intensity of the reflected wave, the PON subscriber was able to self-diagnose the optical line during service. In this way, an in-band OTDR function can be provided for all OLT ports without using a separate OTDR meter. As a result, the operator can immediately respond to sudden failure of the optical path or degradation of performance. As a result, the network operation cost can be reduced by having a self-diagnostic function for the PON section at a lower cost.

1 is a configuration diagram of an embodiment of a general PON network;
2 is a view for explaining the concept of a 10Gbps PON,
3 is an explanatory diagram of an optical wavelength used in a PON;
4 is a view showing the structure of a total PON OLT system according to the present invention;
5 is a configuration diagram of a main CPU and a switching block according to the present invention;
6 is a configuration diagram of a 10G integrated PON line card according to the present invention;
7 illustrates an embodiment of an integrated PON MAC chip in accordance with the present invention;
8 is a signal timing diagram for an optical fiber diagnostic function using RSSI according to the present invention;
9 is a view for explaining the diagnosis of optical path failure using the in-band OTDR according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, It can be easily carried out. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

And throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between. Also, when a component is referred to as " comprising "or" comprising ", it does not exclude other components unless specifically stated to the contrary .

First, in order to help the understanding of the present invention, the technical gist of the present invention is summarized as follows.

The present invention accommodates both 10G-PON standard XG-PON1 (10G / 2.5G) and XG-PON2 (10G / 10G) in one OLT system platform, and 10G / 1G-class 10G EPON or 10G according to user setting conditions Provides integrated PON OLT system that can operate as 10G EPON / 10G class. Here, 10G / 1G means downlink 10Gbps, uplink 1Gbps, likewise 10G / 10G means downlink 10Gbps, uplink 10Gbps. To this end, the applicant of the present invention has developed a PON medium access control (MAC) chip having an integrated PON function, and developed a PON interface card that accommodates it.

The present invention technically implements a Dynamic Bandwidth Allocation (DBA) function by applying a transmission efficiency improvement technique according to a transmission rate and a transmission distance in a PON, and performs forward error correction (FEC) and recovery. Multi-layer network protocols and high-speeds, as well as PHY and MAC access and dependent technologies such as power budget improvement in PON networks, 10G dynamic bandwidth management and virtual transmission distance control Integration of OLT system technologies related to switching technology and multiple 10G high-speed backplane design technology has been achieved.

In other words, the present invention relates to an integrated PON OLT system that can develop one platform and one general-purpose PON MAC chip and selectively operate as needed. In addition, the present invention combines up to 128 branches of ONT / ONU on the same optical fiber, and the transmission distance can accommodate up to 20Km to 60Km. The present invention relates to an OLT system having a self diagnostics function capable of automatically detecting a malfunctioning device.

In particular, since one ONT abnormal operation may cause the service of other ONTs in the same PON to fail, it is very important to take predictable measures in advance in the network. To this end, the ITU-T standard recommends a separate optical time domain reflectometer (OTDR) device and an outband monitoring device using an optical switch using a 1650nm wavelength. However, the present invention proposes an in-band method for monitoring an optical path using optical pulses in a time interval not using in the uplink burst mode by using the same wavelength of 1310 nm but using a time division method. As a result, the present invention can provide a low cost self-diagnostic function, allowing the operator to solve the problem early, thereby reducing operating costs. In addition, the present invention can measure the reception strength (RSSI: Received Signal Strength Indication) of the optical transceiver, compare the BER (Bit Error) and the like can provide life prediction and replacement cycle prediction of the optical transmitter.

In implementing 10Gbps backplane technology, there is a limit to increase the transmission speed by about 5Gbps using the existing PCB technology using FR4. In order to overcome this, the present invention utilizes parallel signals to transfer signals. In the case of 10 Gigabit Media Independent Interface (XGMII) or X Attachment Unit Interface (XAUI), there are too many signal lines to be input and output to the switching block, which may limit the system design.

In the case of the fast switching block, 10Gbps packet streams from multiple PON interface ports and service network interface ports must be analyzed and exchanged according to the corresponding destination. For example, in order to provide 48 10Gbps interfaces, connectors corresponding to 48 times the existing signal lines must be implemented in the switching block. This can cause difficulties in system implementation, such as increasing the number of connectors on the backplane and increasing board size. In contrast, the present invention uses four signal lines capable of transmitting at 10.3125 Gbps using the general 10G base-KR technology. As a result, accommodating 48 ports reduces the cost of the device by reducing the system board height and reducing the backplane size using 4 * 48 = 192 signals.

In addition, the present invention is capable of interworking with the existing network for flexible network evolution from the existing G-PON, and provides a duplication and protection switching technology to ensure the reliability of the network required for the mobile backhaul convergence service. In addition, the present invention is applicable to the IEEE P1588, and applied to the network synchronization board that distributes 1PPS (Pulse Per Second) and TOD (Time of Date). In addition, since the present invention is an OLT system that provides a switching capability of 480Gbps, it is possible to increase service availability by providing Ethernet uplink protection switching within 50ms and redundancy function of each main part.

4 is a block diagram of a PON OLT system providing up to 40 10Gbps PON interfaces according to the present invention and providing up to 8 ports of 10G Base-LX as uplink.

The integrated PON OLT system according to the present invention has 48 ports of 10G Base-KR interfaces 41 to 48 defined in IEEE 802.3ap, and control of the main processors (CPUs) 11 and 13 through the PCIe bus 66. It is provided with a main process and switching blocks (MPS_A, MPS_B) to perform a high-speed L2 / L3 layer switching. To this end, the main process and the switching blocks MPS_A and MPS_B include L2 / L3 switching blocks 12 and 14 and main processors 11 and 13. The detailed configuration of the main process and the switching block MPS will be described later with reference to FIG. 5.

In the case of 10 Gigabit (10G) PON, it is necessary to manage more than tens of thousands of subscribers because it connects and uses various ONUs having the aggregation switch function rather than the general subscriber. Therefore, the main process and the switching block (MPS) must be configured in redundancy because equipment failure due to an unexpected cause may cause service interruption to many subscribers.

The main process and the switching blocks MPS_A and MPS_B must continue to synchronize state information through the defined channel 50. MPS that is waiting for redundancy switchover must match MPS in operation state with all address table and state management variables so that service can be restored in the shortest possible time.

Various line interface cards 401 to 404 connected to MPS include 10G EPON interface card for 10 Gigabit service, XG-PON interface card, GE-PON card and G- for existing 1 Gigabit (1G) level service. PON cards and various 10 Gigabit (10G) interface cards defined in IEEE 802.3ae, such as 1000Base-Tx, 1000Base-LX, and 10G Base-LR, can be connected.

Referring to FIG. 4, in the present invention, a user network interface (UNI) card includes 8 ports of GE-PON for the existing 1G / 1G service or 8 ports for the existing 2.5G / 1.25G service. G-PON interface card (SIIU-G, SIU-E) (401) and 4-port Next Generation PON (NG-PON) card or 10G EPON interface card (PIU) for 10 Gigabit (10G) service -XE, PIU-XG) 402 can be mounted. As a service network interface card, an NIU card (NIU-X) 403 having a 4-port 10G Base-LR interface and an NIU card (NIU-GE) 404 having a 4-port 1000 Base-LR interface are provided. Can be mounted. However, the embodiment shown in FIG. 4 is just one embodiment, and the present invention is not limited thereto and can accommodate various line interface cards.

The line interface cards 401 to 404 and the MPS are connected to each other by 10G electrical signals using two differential signals of 10G Base-KR. In order to implement a 10Gbps backplane technology, XGMII or XAUI is frequently used due to the limitation of high speed connection and the difficulty of PCB manufacturing technology. This is because existing FR4 technology can only transmit data at transfer rates of up to 5Gbps on a 50cm or larger backboard.

When using XGMII (10 Gigabit Media Independent Interface, IEEE 802.3ae), it includes 32-bits data (Rx & Tx) signal operating at 156.25MHz DDR (Double Data Rate), 4-bits control signal (Rxc & Txc) Up to 72 signal lines should be used, and 16 3.125 Gbps signal lines should be used for the X Attachment Unit Interface (XAUI).

However, in the case of the high-speed switching block, in order to switch 48-port 10G-class ports, 10Gbps packet streams from multiple PON user interface cards and service network interface cards must be analyzed and exchanged according to their destinations. For example, to provide 48 10Gbps interfaces, the switching block requires 48 times the number of connectors on existing signal lines. This results in too many pins of L2 / L3 switching elements in the MPS, which can be constrained by paging die size issues when implemented on a chip. In addition, problems in system implementation may occur, such as an increase in the number of connectors on the backplane of the MPS board and an increase in board size.

In order to solve this problem, the present invention used a differential mode two-pair signal line capable of transmitting signals at a transmission rate of 10.3125 Gbps using a general 10G Base-KR (IEEE 802.3ap) technology. As a result, accommodating 48 ports can reduce system board height and backplane size by using 4 x 48 = 192 signals, reducing system manufacturing costs. Referring to FIG. 4, the MPS and each of the line interface cards 401 to 404 are connected using signal lines 41 to 48 of the 10G base-KR method. At this time, each of the line interface cards 401 to 404 is connected to both the MPS in the operation mode and the MPS in the standby mode using the signal lines 41 to 48 of the 10G base-KR method.

Referring to FIG. 4, an optical transceiver 405 connected to the bottom of the MAC functional block in each of the line interface cards 401 to 404 is used in various implementations according to transmission speed, distance, and requirements. Can be.

In case of PON card, burst mode optical transceiver for PON is used. In case of general Giga-class Ethernet, SFP type optical transceiver is used. In the case of 10G E-PON or XG-PON user network interface card 402 that can provide 10 Gigabit-class services, the user network interface card 402 accepts four PON interface ports and enters from one PON port. It performs protocol processing for 10G E-PON and XG-PON such as frame processing suitable for PON method. On the other hand, in the case of the GE-PON or G-PON user network interface card 401 capable of providing 1 gigabit-class service, the user network interface card 401 accommodates eight PON interface ports and in one PON port. It performs protocol processing for GE-PON or G-PON such as frame processing for incoming PON method.

Each user network interface card 401, 402 extracts the Ethernet packets in the PON frame and forwards them to the MPS for exchange to the destination of the packet. To this end, packets output from the PON MAC processing units 15 to 18 of the respective user network interface cards 401 and 402 are converted into XAUI interface signals and output, and the converted signals are physical layer chips (10G Base-KR transceivers). PHY) are converted into 10G Base-KR signals by PHYs 23 to 26 and then transferred to the main process and switching blocks MPS_A and MPS_B through two pairs of differential mode signal lines.

In the L2 / L3 switching blocks 12 and 14 in the MPS, each Ethernet frame is found and the headers of the packets are analyzed, service priorities according to Class of Service (CoS), type of service (ToS), and the quality of service (QoS). After performing the LAN (VLAN: Virtual LAN) analysis, L2 layer switching processing is performed according to the requirements.

When only the L2 layer bridge function and aggregation function are required for the OLT system, the L2 / L3 switching blocks 12 and 14 perform packet exchange according to the MAC destination address by the L2 header. When the L3 routing function is required for the OLT system, the L2 / L3 switching blocks 12 and 14 perform L3 packet exchange based on the IP header. L2 or L3 switching is determined according to the needs of the OLT system in the network.

The packets exchanged in the MPS are delivered to the service network interface cards 403 and 404 corresponding to the respective destinations. The MPS outputs an output signal in a 10G Base-KR manner. The 10G Base-KR physical layer processor (PHY) 29, 30 of the network interface card (NIU-X; 403) receiving the signal output by the 10G Base-KR method converts to an XAUI signal, and then L2 switch 31 Transfer to the XFI physical layer processing unit (PHY) 32 through. The XFI physical layer processing unit 32 converts the XAUI signal into an XFI signal and outputs it.

Meanwhile, the service network interface card 403 transmits signals converted to XFI through a separate XAUI-to-XFI converter to a remote upper network router through an XFP (10 Gbps Small form Factor Pluggable) or SFP + type optical transceiver. I can deliver it. Here, XFP refers to a standard that specifies the mechanical and electrical interface specifications between the optical transceiver and the physical layer (PHY) processing unit. And XFI means the interface signal between the 10Gbps PHY and the optical transceiver. Small Form Pluggable (SFP) stands for Gigabit Optical Transceiver and SFI stands for Interface.

Recently, SFP + optical transceivers are converted to high speed SFI interfaces due to size constraints. However, if the interface of the upper network router or other aggregation switch does not have 10Gbps class depending on the network condition, an existing interface such as NIU-GE must be provided for accessing Gigabit Ethernet (GbE).

Referring to FIG. 4, the NIU-GE 404 includes a multiplexing / demultiplexing unit (MuX / DeMUX) 34 that selects a signal in an operating state from signals connected to four 10G Base-KR lines from each redundant MPS. In addition, the configuration of the output interface in the MPS as a Serial (Deserializer Deserializer) output (SerDes) output can be directly coupled to the optical module (35, 36) SFP optical transceiver of 1Gbit Ethernet (1GbE) class. Here, the sudes means a component connected after the optical transceiver to convert parallel data in series and to convert serial data in parallel.

Initially, when configuring the device's Configuration management, the PON protocol to be used is designated, and the management program conforming to the specified protocol is stored by the local processor (LCPU: local control processor, 19, 20, 28), and Initialization and control are performed by the processor. To this end, local processors (LCPUs) 19 and 20 and respective PON MAC processing units 15 to 18 are connected through a 16-bit local bus. Detailed description thereof will be described later with reference to FIG. 6.

Each user network interface card and service network interface card stores state and control registers in a programmable device programmable logic device (CPLD) 21, 22, 27, 33, and the main processor 11, 13 in the MPS is an external bus. Read and write to the CPLD (21, 22, 27, 33) as a programmable device through (49). When the redundancy function operates, only the MPS, which is an operating state of the MPS_A and the MPS_B, becomes the master of the external bus 49, and the MPS in the standby state does not control the external bus 49.

Synchronization for matching the state variables of the redundant MPS is performed through a separate channel 50. In addition, a separate Ethernet channel 49 is supported for communication between the local processor (LCPU) 19, 20, 28, which is a management process in each line interface card, and the main processors 11, 13, for managing the system operation. Although not shown in FIG. 4 and referring to FIG. 5, a 10/100 Fast Ethernet (FE) switch 59 is provided in the main process and the switching block (MPS) to provide all local processors (LCPU) 19, 20, 28) and an Ethernet communication channel between the main processor (11, 13).

5 is a detailed configuration diagram of a main process and a switching block (MPS) according to the present invention.

The main process and switching block (MPS) is a main switching fabric (Fabric) that inputs and outputs signals in service network interface cards (NIUs) and subscriber network interface cards (SIUs) with 48 10G Base-KR schemes (41 to 48). 12, the main CPU 11 for real-time control of the main switching fabric 12 via the PCIe bus 66, and necessary protocols related to the main L2 / L3 switch must be implemented in software to operate organically. And a volatile memory (DDR) 56 for driving related software, and a non-volatile memory (FLASH) 57 and RTC / NVRAM 58 for storing an initial booting program and a system operating program.

A serial communications (RS232c) drive chip 55 is provided for the operational console port of the device, and a front console port 53 connected to the RS232c drive chip 55 is provided. As an external management port, an RJ45 Ethernet port (MGNT) 52 and an Ethernet processing unit (10 / 100BASE-T PHY) 54 are provided. A 10/100 FE switch 59 is provided for the communication channel between the main CPU 11 and the local processor (LCPU) of each line interface card.

The main CPU 11 drives operation management programs such as fault management, configuration management, and performance management of the OLT system. Further, in the detailed initialization and operation of each line interface, the local processor (LCPU) 19, 20, 28 of each line interface card drives a program suitable for the line interface characteristic. However, direct access to the CPLDs 21, 22, and 27, including the board type identifier storage of each line interface card and the in-board detailed state registers, detailed port initialization, control registers, etc., allows the main CPU 11 to access the local bus ( 49). In addition, the main CPU 11 also manages the CPLD 60, which centralizes and manages board mounting and detachment information and board failure status, through the local bus 49.

The PON OLT system can be used as a backhaul device in a mobile communication network. In order to use it as a carrier Ethernet switch, a function of distributing a network synchronizer clock signal is required. For this purpose, the main process and switching block (MPS) receives the E1 / T1 synchronizer signal 69 from the external network and processes 1PPS (Pulse Per Second) and TOD (Time of Date) directly processed from a GPS synchronizer such as an external base station. System clock module (SCM) 61 that can receive a signal 68, such as) may be included.

The system clock module 61 recovers the necessary synchronizing signal under the control of the main CPU 11 connected through the SPI bus, and then the frame synchronization pulse Frame_Sync and the system clock Sysclk to the subscriber network interface card (SIU). (67) to perform the function of distributing. The system clock module 61 may be implemented in a separate card form according to the mounting structure of the device. In the present embodiment, the case where the slot is insufficient due to the mounting structure, the case is mounted in the main process and the switching block (MPS).

6 is a 10G integrated PON line interface capable of performing the existing 1G-grade GE-PON or G-PON MAC protocol according to the present invention and at the same time can perform 10G 10G EPON and XG-PON MAC protocol Detailed configuration of the card.

The present invention simultaneously satisfies EPON standards such as IEEE 302.ah and 802.3av and G-PON standards such as ITU-T G.984 and G.987, and the down / upward speeds are 10G / 10G, 10G / 1G, It can support all possible configurations such as 10G / 2.5G, 1G / 1G and 2.5G / 1G, so it is designated as “Total PON” MAC. In actual operation, it is not necessary to support all speeds during operation, but when setting up the equipment, it supports the possible speed when specifying PON method. And it is assumed that the G-PON and EPON schemes are not simultaneously supported in one PON line.

In this embodiment, a plurality of independent PON ports are provided. In FIG. 6, two integrated PON MAC chips 17 and 18 are illustrated. An independent local processor (LCPU) 20 is provided that controls a plurality of integrated PON MAC chips 17, 18, such as four to eight, and is connected via a 16-bit local bus 88 for state management. In addition, DDR2 84, which is a volatile memory for driving a process, and a FLASH memory 85, which is a nonvolatile memory, are provided. In addition, an RS232c serial communication port is used as a management port of the local processor (LCPU) 20, and an RS232c drive chip 83 and an external console port 78 are provided for this purpose.

The local processor (LCPU) 20 communicates with the main CPU (MPS) of the system via an Ethernet method through a Fast Ethernet (FE) 86 connected to a port such as MII or RMII. The communication between the local processor (LCPU) 20 and the main CPU is performed through the Interprocessor Communication (IPC) protocol. For this purpose, detailed IPC protocols need to be defined, but the detailed communication message structure and The protocol can be easily implemented from known techniques, and thus a detailed description thereof will be omitted.

Optical signals input to one PON line interface card are received through an XFP (79 to 82) or an SFP + type PON optical transceiver, and the total PON MAC chips 17 and 18 according to the XFI or SFI method. ) Is entered. Although one optical line may correspond to one integrated PON MAC chip, in this embodiment, two XFP optical transceivers are connected to one integrated PON MAC chip, so that a problem occurs in a normal optical transmission line. Redundancy was carried out so that switching could be made to the optical transmission line. In general, the problem of optical line or optical transceiver is higher than that of PON MAC chip.

The total PON MAC chips 17 and 18 interpret the input PON frames according to the PON scheme and recover user communication packets according to the defined PON protocol. Ethernet packets recovered by the integrated PON MAC chips 17 and 18 are output (89 to 92) in the XAUI manner. 10GE physical layer processor (PHY) 25 to convert signals 45-1 to 45-4 in the differential mode of the two lines of the 10G Base-KR method of the backplane in order to transfer the XAUI-type Ethernet packet to the MPS. 26).

Depending on the size of the OLT system, redundancy is required, so the integrated PON MAC chip can choose between the XAUI-primary signal path and the redundancy XAUI-redundant signal path, and the 10GE PHY (25, 26) Performs 2 * 2 cross point switching. Here, the 1G-class G-PON or GE-PON MAC function block and the XG-PON, 10G EPON MAC function block may be implemented separately, but in the present invention, the line interface card of FIG. 6 and one PON MAC chip of FIG. It can be used in common.

With the development of chip integration technology, it is possible to integrate one common function and detailed functions into one chip and to cope with detailed specifications according to user's requirements. An embodiment of a total PON MAC chip is shown in FIG. 7, which shows in detail the optical transceiver and the integrated PON MAC chip portion of the XFP type of FIG. 6.

The optical transceiver 405 can accommodate all wavelengths except the wavelength for CATV overlay described in FIG. 3. The optical transmitter 405 receives a 1G class and 10G class PON uplink optical signal on an optical fiber path 100 made of one optical fiber, converts it into an electrical signal, and then transfers the signal to the integrated PON MAC chips 17 and 18. Do this. The optical transmitter 405 receives the data in the downward direction, converts the data into an optical signal, and transmits the optical signal through the optical path. In the embodiment of the present invention is shown an integrated optical transceiver to transmit and receive all 1G, 2.5G, 10G signals.

An integrated optical transceiver uses an optical transmitter (O / T, 102) that transmits data using a 1577nm wavelength for downlink of 10 gigabytes, and receives downlink data of 1G or 2.5Gbps using a 1490nm wavelength. Optical Transmitter (O / T) 103, which is converted into an optical signal and then transmitted, uses a dynamic bandwidth allocation (DBA) accelerator 125 during an empty time interval in which user data is not transmitted downward using a 1310 nm wavelength. Receives control of the optical transmitter (O / T, 104) and 1310nm test optical pulses in conjunction with the Optical Time Domain Reflectometer (OTDR) processor 110 to transmit optical pulses for OTDR for self-diagnosis of the optical path. Optical receivers (O / R, 105) for receiving 1G or 2.5G uplink data with valid 1310nm wavelength, and optical receivers (O / R, 106) for receiving 10G data using 1217nm wavelength, each Separate optical signals of wavelength and It is: (Wavelength Division Multiplexing WDM) includes a device (101) for wavelength division multiplexing.

Here, each optical transmitter (O / T) 102 and 103 receives and drives an electric signal in a differential mode and converts it into an electric signal, and drives and controls a laser diode such as a distributed feedback laser diode (DFB-LD) and a laser diode. It consists of a diode (LD) driver element.

In addition, the optical receivers (O / R) 105 and 106 may convert a light signal into an electrical signal, such as a photo diode such as an Avalanche Photo Diode (APD), a trans-impedance amplifier (TIA), and a PON limiting amplifier (LIA). ). The optical receiver O / R performs a function of analogly detecting a received signal strength indication (RSSI) and converting the signal into a voltage. This voltage can be used to detect the intensity of the optical signal transmitted from each ONT system. The voltage is converted into a digital signal through an analog-to-digital converter (A / D) and used as a refined value. If the received optical signal intensity is less than a predetermined threshold, it is defined as a Loss of Signal (LOS) state. The optical transmitter (O / T) may be independently transmitted for each wavelength under the control of each MAC chip.

The total PON MAC chips 17 and 18 may be divided into a transmission part and a reception part. The receiving part includes receivers 111 and 112 performing a deserializer function, an uplink MAC processor 115 and 116 performing MAC protocol processing, and a decryption engine that decrypts an encrypted packet. 120, synchronous FIFOs 123 and 124 performing a temporary buffer function, an uplink packet processing and frame configuration unit 128 that performs processing and frame reconstruction for uplink packets, a network engine 134, a data location table ( 135), the uplink traffic manager 138, the XAUI MAC processing unit 143, and the sudest 144.

The transmission part also consists of almost the same elements as the reception part. The transmission part is SerDes 142, XAUI MAC 141, downlink network engine 139, data location table 131, downlink traffic manager 129, frame components 127, 126, synchronous FIFO ( 121 and 122, encryption engines 117 and 118, downlink MAC processing units 113 and 114, and transmitters 108 and 109 performing parallel-serial conversion functions.

An integrated PON MAC chip having such a configuration will be described in detail with reference to FIG. 7.

A first receiver 111 that performs a deserializer function extracts a clock from a 1.25 Gbps (first rate) bit stream and performs FEC processing (Reed Solomon (239,255) coding scheme). Afterwards, an error-free frame is transmitted to the 1G upstream (US) MAC processor (first uplink MAC processor) 115 through scrambling and 8B / 10B decoding.

In addition, the second receiver 112, which performs a deserializer function, receives a 10.3125 Gbps (second transmission rate) bit stream converted into an electrical signal by an optical transceiver, extracts a clock, and performs forward error correction ( According to the presence or absence of the FEC: Forward Error Correction (FEC) method, an error-free frame is found and transmitted to the 10G uplink (US) MAC processor (second uplink MAC processor) 116 through FEC decoding processing, scrambling, and 64B / 66B decoding processing.

In the present invention, a 1Gbps or 2.5Gbps transmission rate is defined as a first transmission rate, and a 10Gbps transmission rate is defined as a second transmission rate.

The first uplink (US) MAC processor 115 receives a PON frame from the first receiver 111 and performs a PON frame analysis and an associated PON MAC protocol according to a PON scheme defined at initialization. The second uplink (US) MAC processor 116 interprets the 10G PON frame received from the second receiver 112 and processes the associated PON MAC protocol.

 The first and second decryption engines 119 and 120 receive the packets processed by the first uplink MAC processor 115 and the second uplink MAC processor 116, respectively, and encrypt (AES) Advanced Encryption. Standard) performs decoding or passes the function right away.

Packets output from each of the first and second decryption engines 119 and 120 are stored in first and second sync first-in first-out buffers 123 and 124 for subsequent processing. In other words, when 1G and 10G traffic are simultaneously input, the traffic cannot be processed at the same time. Therefore, the traffic is stored in the sync first-in-first-out buffer (Sync FIFO) in consideration of the waiting of the received traffic.

If there is a packet to be delivered upward in the first and second synchronous first-in, first-out buffers 123 and 124, the uplink packet processing & frame editor 128 may use the first and second synchronous FIFOs 123. A packet is read from any one of the first and second FIFOs 123 and 124 in a priority order according to the packet storage level information of the first and second FIFOs. The uplink packet processing and frame construction unit 128 parses a packet read from any one FIFO to extract detailed information, and according to priorities such as Class of Service (CoS) and Type of Service (ToS). The packet is reconstructed after the classification and unnecessary information are extracted or deleted. The frame output from the uplink packet processing and frame configuration unit 128 is transferred to an uplink network engine (US Network Engine) 134.

The uplink network engine 134 processes L2 / L3 / L4 related protocols that are already defined or pre-standardized protocols, Address Resolution Protocol (ARP), IPv4, IPv6, Transmission Control Protocol (TCP), User Datagram Protocol (UDP), and the like. Perform the necessary protocol processing. In addition, the uplink network engine 134 performs an L2 level bridge function such as interpretation of a virtual LAN (VLAN) and modification of an associated VLAN tag. In this case, the uplink network engine 134 stores the FIFO 136 in the case of a packet that needs to be delivered to the local processor (CPU) and processes it, and then stores an external buffer (External Data) to store it in the classified buffer according to the analyzed classification information. Buffer 137) and related storage location and packet size information in a separate data location table 134. Of course, the uplink network engine 134 may refer to a separate address table and a VLAN table 132 for L2 bridging and VLAN processing. In addition, the upstream network engine 134 may update the address table and the VLAN table 132 for new connections as needed.

The US Traffic Manager 138 inquires the data storage location and size information of the packet data stored for each classification, reads the actual packets from the external data buffer, and schedules the packets according to their priorities. At this time, the uplink traffic manager 138 processes within the speed limit if there is a speed limit for each port, and performs an appropriate shaping function for the traffic. In this case, when there is a packet to be transmitted upward from the local processor (CPU), the uplink traffic manager 138 inserts a packet stored in the FIFO 136-1 into the flow to the upper network at an appropriate timing.

The XAUI MAC processing unit 143 converts the packets received from the upstream traffic manager 138 into signals of four lanes driving at 3.125 Gbps according to the XAUI interface and then transmits the signals to Serdes 144. . The SerDes 144 refers to a converter for converting parallel data into serial and converting serial data into parallel. The SerDes 144 converts the four lane signals transmitted from the XAUI MAC processing unit 143 into the differential mode signaling method to transfer the four lane signals to the MPS. Here, SerDes 144 provides a primary port 89 and a secondary port 90 for redundancy of the switch.

The operation of the next transmission part will be described with reference to FIG.

The sudes 142 converts a signal transmitted in a differential mode signaling method into parallel data and transmits the converted signal to the XAUI MAC processor 141. The XAUI MAC processing unit 141 receives data from four lanes from the sudes 142, constructs a normal packet from 3.125 Gbps data of four lanes, and delivers the normal packet to the downlink network engine 139. .

The downlink network engine (DS Network Engine) 141 parses and analyzes the header of the input packet and stores the packet in the related FIFO 130-1 when the packet is to be delivered to the local processor (LCPU). In addition, the downlink network engine 141 classifies according to the packet header information and stores the data in the external data buffer 140 according to the classification information, and stores the storage location information and the data size information of the related data in a data location table. Table 131). At this time, the address table 132 is queried for lookup with address information of the header information or for VLAN tag conversion, deletion, and insertion.

The downlink traffic manager (DS Traffic Manager) 129 receives a packet to be transmitted downward from the local processor (CPU) through the buffer 130, and classifies each data from the data location table 131 according to the presence or absence of data to be transmitted downward. The packet is scheduled and delivered downward according to the priority of the packet. In this case, the downlink traffic manager 129 performs queue scheduling according to each class level according to each QoS priority, and performs various queue services such as a strict priority (SP) method or a weighted round robin (WRR). Of course, the downlink traffic manager 129 may include the timing of the DBA accelerator 125 for PON multiplexing in a time-division manner through the downlink packet and the timing of delivery and other operation and maintenance (OAM) packets. Under control. Then, whether the destination of the packet to be sent is ONT in the 1G class PON or ONT in the 10G class PON is transmitted to the corresponding first and second frame components (Frame Editors 126 and 127).

The first frame configuration unit 127 constituting the 1G or 2.5G class downlink frame generates a PON frame corresponding to the 1G or 2.5G class downlink frame, and stores the PON frame in the third sync FIFO 122 and configures the second frame constituting the 10G downlink frame. The unit 126 generates a PON frame suitable for the 10G speed and stores the PON frame in the fourth synchronous FIFO 121. A sync FIFO exists to buffer the difference between the processing speed at the upper level and the actual lower transmission speed, and in particular, a third synchronization FIFO 122 of 1G class should be relatively large.

The first and second encryption engines 117 and 118 encrypt or directly pass frames input from the third and fourth synchronous FIFOs, respectively, according to the AES 128 encryption application option. The frames passing through the first and second encryption engines 117 and 118 are transmitted to the first and second downlink MAC processing units 113 and 114, respectively.

The first downlink MAC processing unit 114 receives the control of the DBA accelerator 125, processes the frame according to the PON protocol corresponding to 1G / 2.5G, and transmits the frame to the first transmitter 109 for 1G / 2.5G. . The first transmitter 109 performs 8B / 10B coding on the packet input from the first downlink MAC processor 114, performs scrambling processing, RS (255, 239) FEC encoding, and then serializes the serialized data. To the optical transceiver.

In addition, the second MAC processing unit 113 is controlled by the DBA accelerator 125, configures a complete frame according to the PON protocol corresponding to 10G, and transfers it to the second transmitter 108 for 10G. The second transmitter 108 performs 64B / 66B coding on the packet input from the second downlink MAC processing unit 113, and then performs scrambling processing, RS (255, 223) FEC encoding, and then serializes the serialized data. To the optical transceiver.

In the upward direction of 10G EPON, 1G EPON ONU and 10G EPON ONU use the same wavelength to transmit data to the OLT system in a time division manner. In order to process these data, the OLT receiving side requires a 10G burst receiving mode and a 1G burst receiving mode of 1310 nm wavelength. The 1G EPON ONU transmits 1.25Gb / s data encoded in 8b / 10b as a burst signal using 1310nm (100nm band) wavelength, whereas the 10G EPON ONU transmits 10.3125Gb / s data encoded in 64b / 66b to 1270nm. Transmit with burst signal of (20nm band) wavelength.

10 Gbps optical receivers typically have much lower sensitivity than 1 Gbps, so high performance FEC and high power optical transmitters are required to meet high power budgets. The FEC code adopted in the 10G EPON is RS (255,223) belonging to the Reed-Solomon (RS) group. Unlike the 1G EPON, the FEC code operates on a bit stream basis, not on a frame basis. RS (255, 223) has about 13% overhead, and the 10G EPON must use FEC, but FEC is optional for the 1Gbps uplink of asymmetric 10G EPON. Bitstream-based FEC has a fixed-length overhead, making it easy to match 10Gbps 64b / 66b coding schemes, as well as only a 3% increase in overhead with 10G EPON's 64b / 66b line code, leading to 8b Coding efficiency is higher than 1G EPON using / 10b code.

In the case of the GE-PON method, a multipoint control protocol (MPCP) is used to provide a point-to-multipoint PON network. In OLT, to distinguish several ONTs in one PON, each ONT is given a different ID called LLID (Logical Link Identification).

Multipoint Control Protocol (MPCP) allows the ONT to be assigned an LLID when it connects to the PON and to continuously communicate over the PON. In this PON, time division multiplexing (TDM) is used, so time synchronization between OLT and ONT is important.

Accordingly, the OLT sends a timestamp indicating its time to all frames transmitted to the ONT, and the ONT checks the timestamp in the received frame and synchronizes its time. This timing reference is managed by the DBA accelerator 125. In the case of G-PON, ONU_ID is allocated and managed, and 125usec synchronized frames are used for time synchronization with each other. Therefore, the time synchronization of the sync frame in the G-PON is also managed by the DBA accelerator 125.

The G-PON protocol layer exists below the data link layer and converts services of various data link layers into G-PON frames and transmits them. G-PON® protocol consists of physical layer and transmission convergence layer (TC).

The physical layer performs photoelectric conversion and burst reception functions and extracting clock functions. The transmission convergence layer is composed of a frame framing sub-layer and a transmission convergence matching layer (TC Adaptation sub-layer).

In the frame sublayer, frames transmitted from ATM and G-PON Encapsulation Method (GEM) transmission convergence matching devices, physical layer operation and maintenance (PLOAM) information, dynamic bandwidth allocation (DBA) information, synchronization information, etc. It performs the function of multiplexing or demultiplexing into G-PON transmission convergence (GTC, GPON TC) frames at every 125usec cycles.

The transport convergence layer recognizes “Virtual Path Identifier / Virtual Channel Identifier (VPI / VCI)” in case of “ATM” service and “Port Identifier” (Port-ID) in case of GEM service and performs filtering function. . In addition, time slot assignment and ONU management functions for uplink transmission control of ONUs are performed.

ATM clients are connected to ATM transport convergence matching devices via VPI / VCI, and GEM clients receiving services such as IP, Ethernet, and TDM are connected to GEM transmission convergence devices through port-IDs.

PLOAM (Physical layer OAM) transfers information such as management of PON physical layer and operation management of frame sublayer, and is transmitted through 13 bytes of PLOAM area. The ONU Management and Control Interface (OMCI) performs statistical information and state management of ONUs.

In G-PON network, ONT is registered and activated in two ways, static / dynamic, using PLOAM between OLT and ONT. Among them, in the dynamic method, ONU first adjusts the transmission optical power level based on the OLT request. The OLT finds the serial numbers of the ONUs connected to its PON network. OLT assigns the ONU ID to the serial number of the found ONU. OLT measures the arrival time of uplink transmission from ONU. The OLT sends an equalization delay (EqD) to the ONU. The ONU applies the transmission time passed from the OLT. Synchronization information (visual information) is sent to the header in the packet sent downward from the OLT. Accordingly, all ONTs transmit information in a frame synchronized with 125usec.

OLT manages the bandwidth for delivery of each ONT. Bandwidth management based on the amount of data required for ONT is called DBA (Dynamic Bandwidth Allocation), and uses an algorithm that dynamically allocates bandwidth to subscribers according to subscriber demand level for efficient bandwidth usage. Dynamic bandwidth allocation operates by requesting allocation from ONT (U) and appropriate allocation from OLT, and requesting bandwidth allocation by using Dynamic Bandwidth Report-upstream (DBRu) among upstream frames, and T-CONT (Transmission Container) unit. Bandwidth is allocated. The ONU transmits its upstream queue information to the OLT, and the OLT allocates an upstream time slot based on the information.

The ONU carries queue information when transmitting upstream, and the OLT performs scheduling to efficiently perform dynamic bandwidth allocation (DBA) for each T-CONT type while continuously updating the information. In addition, NSR-DBA (non status report method) uses OLT itself to analyze the upstream traffic (Upstream Traffic) to allocate bandwidth.

The optical path monitoring function of the existing OLT system uses a separate wavelength of light in the outband and measures the transmission interval of the point-to-point connection using the OTDR equipment. OTDR uses Backscattering, which is the result of Rayleigh scattering and Fresnel reflections, to determine the extent and point of attenuation at each discrete point.

Both input and backscattered light are attenuated over distance. Therefore, the signal detected with time becomes smaller. Anomalies in connectors, splices, fiber ends, or fibers may result in increased power. Light travels through the fiber at a rate of about 5 ns / m, depending on the index of refraction of the core. Therefore, by measuring the RSSI value with respect to the time of the reflected wave, it is possible to measure the distance of each point by the following Equation 1 for a pulse of a certain size or more.

Where D is the length of the fiber, c is the speed of light, t is the round trip time of the input pulse, and n is the average refractive index of the core.

However, since the PON has a point-to-multipoint structure, it is difficult to monitor the rear end of the splitter. This is because the reflected backscattered light traces overlap each other because the reflected waves of the light pulses introduced into a single beam are reflected from the splitter branch to the starting point. Measurements can be made if the track lengths at the rear of the splitter are significantly different.

Various studies have been conducted to apply this in the PON network structure. In addition, the ITU-T L.40 International Standard defines the wavelength of an optical pulse as 1650 nm. However, when redefining other wavelengths used in the PON, it is difficult to implement them in the optical transceiver, and in particular, since the reflective semiconductor optical amplifier (RSOA) must be used separately, When implemented in a single optical transceiver, such as a wavelength, the size thereof is increased, thereby making the OLT system less practical. In order to solve this problem, the present invention uses 1310nm, which is used upward in the existing GE-PON / G-PON, so that the 10G PON transceiver can be embedded in the present invention.

Referring to FIG. 7, as in the embodiment of the integrated PON MAC chip, the OTDR processor 110 is controlled by the DBA accelerator 125 and transmits 1310 nm optical pulses downward to the subscriber side, avoiding the PON data service interval. The intensity of the backscattered wave is measured.

Referring to FIG. 8, the OTDR processor 110 measures in real time according to a signal timing diagram for diagnosing a light path using Received Signal Strength Indication (RSSI) illustrated in FIG. 8. According to the actual input pulse (data), after a predetermined time T1, the RSSI_TRG trigger signal is provided to read the RSSI output. After T3, the serial data is read through the SPI interface.

For example, place splitter 1 (3 to 4 dBm attenuation) at a distance of 2 km (0.5 dBm / Km * 2 = 1 dBm loss) from the OLT, followed by 1: 8 splitter 2 (-9 to -10 dBm loss) after 2 km. Eight ONTs are installed in each drop fiber. The other line of the 1: 2 branch connects ONT9 100M away. The distance between ONT1 and ONT8 is 50m to 100m respectively, while ONT8 is 500m away.

Figure 9 shows the waveform measured by using the in-band 1310nm wavelength in this environment.

The measured value 502 in the normal network configuration is recorded, and the difference with the waveform 503 measured at the time of cutting the track of ONT3 can be inferred to cause a problem at the track point of the ONT3. Therefore, as shown in this example, after comparing the wave form measurement value and the periodically measured value with each other after installation, the analysis of the large change part is performed. Can be detected.

The BER (Bit Error) value detected by the PON MAC is compared with the RSSI value, and when the BER increases above a certain threshold and the RSSI falls below a certain threshold, the degradation of the optical transceiver can be predicted. have. Using this, it can be determined that the specific optical transmitters of the OLT and ONT / ONU must be replaced. Therefore, as in the present invention, in-band OTDR by implementing a control interface that can query the RSSI value of the Trans-Impedance Amplifier (TIA) or the Limiting Amplifier (LIA) of the receiver of the optical transceiver when the PON MAC is implemented. It can be operated as follows to realize useful optical self-diagnosis function.

As described above, although the present invention has been described with reference to the limited embodiments and the drawings, the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains should understand the present invention. Various substitutions, modifications, and changes can be made without departing from the spirit.

Therefore, the scope of the present invention should not be construed as being limited to the embodiments described, but should be determined by the scope of the appended claims, as well as the appended claims.

401 to 404: Line Interface Card 405: Optical Transceiver
11, 13: main CPU 12, 14: L2 / L3 switching block
15 to 18: integrated PON MAC processing unit
19, 20, 28: Local Processor (LCPU) 21, 22, 27, 33: CPLD
23 to 26, 29, 30: 10G Base-KR PHY 31: L2 switch
32: XFI PHY 34: Multiplexing / Demultiplexing Unit
35, 36: optical module

Claims (19)

A plurality of user network interface cards for supporting various passive optical network (PON) protocols;
A plurality of service network interface cards for supporting various passive optical network protocols; And
It is connected between each of the user network interface card and each service network interface card, recovers the received packet, provides a packet exchange function according to the header information of the packet, and includes a main processor (CPU) and a main switching fabric. Including the main process and switching blocks,
The main process and switching block is connected to each of the user network interface card and each service network interface card through a 10 Gigabit (10G) Base-KR (IEEE 802.3ap) differential mode signal line to provide a 10 Gigabit class backplane. Integrated passive optical network optical line termination system.
A plurality of user network interface cards for supporting various passive optical network (PON) protocols;
A plurality of service network interface cards for supporting various passive optical network protocols; And
It is connected to each of the user network interface card and each service network interface card through a differential mode signal line, recovers the received packet and provides a packet exchange function according to the header information of the packet, and the main processor (CPU) and the main A main process and a switching block comprising a switching fabric,
The plurality of user network interface cards and the plurality of service network interface cards include storage means for executing a passive optical network protocol designated at an initial configuration of the plurality of passive optical network protocols, and storing their state and control register, respectively. ,
The main processor executes an operation management program for fault management, configuration management, and performance management, and is configured to enable reading and writing of the storage means for storing its state and control register through an external bus. Optical line termination system.
3. The method according to claim 1 or 2,
The main process and the switching block,
Integrated passive optical network optical line termination system having a redundant structure.
The method of claim 3, wherein
Each user network interface card,
Redundant integrated passive optical network MAC (MAC) processing means capable of supporting various passive optical network protocols;
A first local processor (CPU) for controlling said redundant integrated optical network MAC processing means to process a passive optical network protocol designated at initial configuration management setting;
A first programmable device that stores its state and control resist and is accessible by the main processor via an external bus;
Redundant first physical layer processing means for transferring the packet processed by the integrated passive optical network MAC processing means to the main switching fabric through the differential mode signal line; And
Optical transmitter and receiver connected to the dual integrated passive optical network MAC processing means to provide communication via optical path
Integrated passive optical network optical line termination system comprising a.
5. The method of claim 4,
Each user network interface card,
Integrated passive optical network optical line termination system further comprising a fast Ethernet physical layer processing means for providing a fast Ethernet channel between the first local processor (CPU) and the main processor.
The method of claim 3, wherein
Each of the redundant main process and switching block,
The main network transmits and receives a signal with the plurality of user network interface cards and the plurality of service network interface cards in a 10G base-KR scheme, extracts a packet from the signal, and exchanges packets according to header information of the packet. Switching fabric;
Connected to the main switching fabric via a PCIe bus to control switching based on L2 / L3 protocol of the main switching fabric, to perform operational management, the plurality of user network interface cards and the plurality of service network interface cards The main processor directly accessing their programmable device;
A memory for storing various programs and data executed by the main processor; And
A second programmable device connected to the main processor via a local bus to collect and manage board detachable or fault related signals
Integrated passive optical network optical line termination system comprising a.
The method according to claim 6,
The main process and the switching block,
And a high speed Ethernet switch for providing an Ethernet communication channel for outband communication with local processors of said plurality of user network interface cards and said plurality of service network interface cards.
The method of claim 7, wherein
The main process and the switching block,
The system clock module may further include a system clock module configured to receive an E1 / T1 network synchronizer clock, extract a synchronization clock, and distribute time information, frame synchronization signals, and system synchronization signals to the plurality of user network interface cards and the plurality of service network interface cards. Integrated passive optical network optical line termination system.
The method according to claim 6,
Each of the plurality of service network interface cards,
A first service network interface card for transmitting and receiving 10Gbps Ethernet signals; And
Second service network interface card for transmitting and receiving 1Gbps Ethernet signal
Integrated passive optical network optical line termination system comprising a.
The method of claim 9,
The first service network interface card,
Redundant second physical layer processing means for communicating with the main switching fabric of the main process and the switching block in a 10G Base-KR scheme and converting an input signal into an X Attachment Unit Interface (XAUI) signal;
An L2 switch connected to the second redundant physical layer processing unit to perform a layer 2 (L2) switching function of a received packet;
Third physical layer processing means connected to the L2 switch to convert an XAUI signal into an XFI signal and output the converted XFI signal;
A second local processor that performs a PON protocol for a 10G service network interface; And
A third programmable device that stores its state and control register and is accessible to the main processor via an external bus
Integrated passive optical network optical line termination system comprising a.
The method of claim 9,
The second service network interface card,
Multiplexing / demultiplexing means for communicating with a main switching fabric of the main process and the switching block in a 10G Base-KR scheme, and multiplexing or demultiplexing packets transmitted and received;
An optical module connected to the multiplexing / demultiplexing means and optically transmitting or receiving a signal transmitted and received; And
A fourth programmable device that stores its state and control register and is accessible by the main processor via a bus
Integrated passive optical network optical line termination system comprising a.
5. The method of claim 4,
The integrated passive optical network MAC processing means is divided into a receiving part and a transmitting part,
The receiving part,
A receiver for a first transmission rate and a receiver for a second transmission rate for respectively detecting an error-free frame from the signals respectively input from the optical transceiver;
A first upstream MAC processing unit for performing PON MAC protocol processing by analyzing the PON frame received from the first transmission rate receiver;
A second upstream MAC processing unit for performing PON MAC protocol processing by analyzing the PON frame received from the second transmission rate receiver;
First and second buffers respectively buffering the frames processed by the first and second upward MAC processors;
Uplink packet processing means for reading frames stored in the first and second buffers, reconstructing packets through parsing and priority classification, and performing standard protocol processing and scheduling on the reconstructed packets;
An uplink transmitter for converting a packet input from the uplink packet processor into an XAUI signal and then converting the packet into a differential mode signal and transmitting the signal to the main process and the switching block;
The transmission part,
A downlink receiver configured to convert a differential mode signal received from the main process and the switching block into an XAUI signal to form a normal packet;
Downlink packet processing means for classifying the packet received from the downlink receiver, performing standard protocol processing and scheduling for downlink traffic, and classifying whether the packet is the first rate packet or the second rate packet;
A first frame configuration unit configured to receive a first transmission rate packet from the downlink packet processing means and configure a PON frame suitable for the first transmission rate;
A second frame configuration unit configured to receive a second transmission rate packet from the downlink packet processing means and configure a PON frame suitable for the second transmission rate;
A first downlink MAC processor for performing downlink MAC protocol processing on the PON frame processed by the first frame configuration unit;
A second downlink MAC processor for performing downlink MAC protocol processing on the PON frame processed by the second frame configuration unit;
A first downlink transmitter which processes a frame input from the first downlink MAC processor and transfers serialized data to the optical receiver;
A second downlink transmitter which processes a frame input from the second downlink MAC processor and transfers serialized data to the optical receiver; And
DBA Accelerator for PON Dynamic Bandwidth Allocation (DBA) Control
Integrated passive optical network optical line termination system comprising a.
13. The method of claim 12,
The DBA accelerator,
Integrated passive optical network optical line termination system for managing a timing reference by checking a timestamp in the frames received through the first and second upward MAC processing unit.
13. The method of claim 12,
The integrated passive optical network MAC processing means,
Integrated passive optical network optical line termination system further including an optical time domain reflectometer (OTDR) processor for performing a self-diagnosis of the optical line during the empty time period under the control of the DBA accelerator does not transmit user data downward using the receiving optical wavelength .
15. The method of claim 14,
The optical transmitter,
A first optical transmitter for transmitting data using a wavelength for downlink of 10 gigabits;
A second optical transmitter configured to receive downlink data of one or two-gigabit class, convert the data into an optical signal, and then transmit the downlink data;
A third optical transmitter for transmitting an optical pulse for an OTDR for self-diagnosis of an optical line in association with the OTDR processor during an empty time period in which user data is not transmitted downward using a received optical wavelength;
A first optical receiver receiving the reflected wave of the optical pulse for OTDR or receiving uplink data of 1 Gigabyte or 2.5 Gigabyte;
A second optical receiver receiving up to 10 gigabit of upstream data; And
Wavelength division multiplexing means for separating and multiplexing optical signals of each transmit and receive wavelength
Integrated passive optical network optical line termination system comprising a.
15. The method of claim 14,
The first optical receiver,
Integrated passive optical network optical line that detects the received intensity (RSSI) of the received optical signal analog and converts it to digital, and sets the Loss of Signal (LOS) state when the converted received intensity is below a threshold. Termination system.
In the integrated passive optical network MAC processing apparatus used in the integrated passive optical network optical line termination system,
A receiver for a first transmission rate and a receiver for a second transmission rate for respectively detecting an error-free frame from the signals respectively input from the optical transceiver;
A first upstream MAC processing unit for performing PON MAC protocol processing by analyzing the PON frame received from the first transmission rate receiver;
A second upstream MAC processing unit for performing PON MAC protocol processing by analyzing the PON frame received from the second transmission rate receiver;
First and second buffers respectively buffering the frames processed by the first and second upward MAC processors;
Uplink packet processing means for reading frames stored in the first and second buffers, reconstructing packets through parsing and priority classification, and performing standard protocol processing and scheduling on the reconstructed packets;
An uplink transmitter for converting a packet input from the uplink packet processor into an XAUI signal and then converting the packet into a differential mode signal and transmitting the signal to a main process and a switching block;
A downlink receiver configured to convert a differential mode signal received from the main process and the switching block into an XAUI signal to form a normal packet;
Downlink packet processing means for classifying the packet received from the downlink receiver, performing standard protocol processing and scheduling for downlink traffic, and classifying whether the packet is the first rate packet or the second rate packet;
A first frame configuration unit configured to receive a first transmission rate packet from the downlink packet processing means and configure a PON frame suitable for the first transmission rate;
A second frame configuration unit configured to receive a second transmission rate packet from the downlink packet processing means and configure a PON frame suitable for the second transmission rate;
A first downlink MAC processor for performing downlink MAC protocol processing on the PON frame processed by the first frame configuration unit;
A second downlink MAC processor for performing downlink MAC protocol processing on the PON frame processed by the second frame configuration unit;
A first downlink transmitter which processes a frame input from the first downlink MAC processor and transfers serialized data to the optical receiver;
A second downlink transmitter which processes a frame input from the second downlink MAC processor and transfers serialized data to the optical receiver; And
DBA Accelerator for PON Dynamic Bandwidth Allocation (DBA) Control
Integrated passive optical network MAC processing device comprising a.
The method of claim 17,
The DBA accelerator,
Integrated passive optical network MAC processing apparatus for managing timing criteria by checking a timestamp in the frames received through the first and second upward MAC processing unit.
The method of claim 17,
The integrated passive optical network MAC (MAC) processing apparatus,
And an optical time domain reflectometer (OTDR) processor for performing self-diagnosis of an optical line during an empty time period in which the user data is not transmitted downward by using the received optical wavelength under the control of the DBA accelerator.

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