KR20130127346A - Memory device, memory system and operating method thereof - Google Patents

Abstract

Disclosed are a memory device, a memory system, and an operating method thereof. The operating method of the memory device according to the embodiment of the present invention comprises the steps of: (a) updating a disturbance count value about a second memory cell by counting the amount of disturbance of the second memory cell which is adjacent to a first memory cell when the first memory cell is accessed; (b) controlling a refresh operation schedule according to a comparison result by comparing the disturbance count value of the second memory cell with a preset threshold value and the maximum disturbance count value; and (c) resetting the disturbance count value of the second memory cell and the maximum disturbance count value if the second memory cell is refreshed according to the controlled schedule.

Description

MEMORY DEVICE, MEMORY SYSTEM AND OPERATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly, to a memory device, a memory system, and a method of operating the same, which can reduce the dynamic refresh characteristic deterioration caused by the disturbance generated when the memory cell is accessed by controlling the refresh operation. It is about.

A high voltage is applied to a word line (WL) of a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) to enable a transistor for accessing a memory cell. In this case, the electric field generated by the high voltage may lower the threshold voltage of the access transistor in the adjacent cell. As a result, the leakage amount of the adjacent cell is increased, which is called a pass gate effect. In order to prevent data loss due to leakage current, DRAM requires that data be read, read and written back to the cell before the data stored in the cell is completely lost. Such an operation is called a refresh operation, and the refresh operation may be performed periodically at a predetermined time in the DRAM or at the request of a system.

The refresh operation characteristics include a static refresh characteristic and a dynamic refresh characteristic. At this time, a time interval between a first refresh operation for a predetermined cell of the memory cell array and a second refresh operation performed next for the cell is called a refresh interval.

The static refresh characteristic refers to the cell's refresh characteristic when there is little or no access to the DRAM during the refresh interval. The dynamic refresh characteristic refers to the cell's refresh characteristic when access to the DRAM cell is performed relatively frequently compared to the static refresh characteristic during the refresh interval.

Static refresh is less affected by adjacent cells or adjacent lines than dynamic refresh, and is less affected by power noise when accessing other cells.

On the other hand, in the case of dynamic refresh, the access to DRAM cells is frequent, so the influence of each cell depends on the frequency of access. At this time, the degree of influence of each remaining cell by access to one DRAM cell is called a disturb.

When the spacing between cells of a DRAM memory cell array is large, the access tends to have a disturb effect on each remaining cell. However, if the spacing between the memory cells is narrowed due to scaling, interference by adjacent cells or lines passing adjacent to each other, that is, disturbance, tends to be affected.

In the case of random access memory (eg DRAM), access to a particular address cannot be restricted, so access may be concentrated in some specific cells. When access is concentrated, the refresh characteristics of the cell deteriorate sharply due to the disturb.

Therefore, in order to improve the refresh characteristic, it is necessary to make the refresh more frequent for the cell in which the disturbance is concentrated.

An object of the present invention is to provide a memory device, a memory system, and a method of operating the memory device capable of improving dynamic refresh characteristics by controlling a refresh operation on a cell in which a disturbance is concentrated.

In order to solve the above technical problem, a method of operating a memory device including a plurality of memory cells according to an embodiment of the present invention (a) each time the first memory cell is accessed, adjacent to the first memory cell Counting the amount of disturbances of the second memory cell to update the disturb count value for the second memory cell, (b) comparing the disturb count value of the second memory cell with a predetermined threshold value and a maximum disturb count value; Adjusting a refresh operation schedule according to a result; and (c) resetting the disturb count value and the maximum disturb count value of the second memory cell when the second memory cell is refreshed according to the adjusted schedule. Include.

The disturb amount may be a value obtained by dividing a cumulative access time for the first memory cell by a unit time.

Each time the first memory cell is accessed, the disturb count value is updated by adding a value that is periodically counted during the current access time of the first memory cell to a disturb count value stored at a previous access time.

In step (b), if the disturb count value of the second memory cell is equal to or greater than the threshold value and exceeds the maximum disturb count value, the step of advancing a refresh operation sequence for the second memory cell in the schedule and And updating the maximum disturb count value to the disturb count value of the second memory cell.

In the step (c), after the memory device is powered up, the irregular refresh flag is activated to control to perform a refresh operation according to a schedule. When the memory device is in a test mode, the irregular refresh flag is deactivated. The refresh operation can be stopped.

When refreshing the second memory cell, the irregular refresh flag may be reset.

The method may further include initializing the disturb count values of the memory device when the memory device is powered up and initialized.

In order to solve the above technical problem, a memory device according to an embodiment of the present invention, a memory cell array including a plurality of memory cells, when accessing at least one first memory cell of the plurality of memory cells, Read a current disturb count value for a second memory cell adjacent to a first memory cell and compare the current disturb count value with a predetermined threshold and maximum disturb count value; and during the current access time of the first memory cell, A control logic for counting a disturb amount of a memory cell to update the disturb count value and a word line address of the second memory cell, and calculating a current refresh schedule for the second memory cell according to a result of comparing the disturb count value. To adjust the refresh operation of the second memory cell and power up signal. The base includes a refresh unit controlling whether or not the initialization performing refresh operation.

The memory cell array may include a normal cell array including a plurality of the first memory cells storing data and a disturb count cell array including a plurality of disturb count cells storing the disturb count value.

At least one disturb count cell belongs to the same word line as the first memory cell.

The control logic receives a clock signal, an active command and an address from a host, decodes the control signals corresponding to the command based on the clock signal, and decodes the address into a row address and a column for accessing the first memory cell. An address comment decoder for decoding to an address, a count value comparison unit for comparing the read current disturb count value with the threshold value and the maximum disturb count value, and a disturb count stored at a previous access time each time the first memory cell is accessed A count value updater configured to update a value by adding a value that is periodically counted during the current access time of the first memory cell and the disturb count values of the second memory cell from an initialization time point of the memory device to a current operation time point. Maximum disturb count value Chapter, and the disturbing the updated count value may include the current count value is greater than the maximum disturbance, disturbance maximum count value stored to update the updated disturb the count value of up to disturb the count value portion.

The refresh unit may include an adjacent address calculator configured to calculate an address for the second memory cell based on the address for the first memory cell received from the control logic, and wherein the current disturb count value for the second memory cell is calculated. When the threshold value is greater than or equal to the maximum disturb count value, the address of the second memory cell is stored as a next irregular refresh address, and whether or not to perform an irregular refresh operation on the second memory cell. ) May include a refresh controller for adjusting the current refresh schedule to preferentially perform an irregular refresh operation of the second memory cell according to the next non-normal refresh address and non-normal refresh flag storage reflected to the second non-normal refresh flag.

The refresh unit may further include a periodic internal refresh command generation unit configured to refresh the entire memory cell array based on the power-up signal and output an internal refresh signal for controlling to initialize the disturb count value.

The control logic may include a count valid flag unit for activating a count valid flag according to the internal refresh signal to reset the count value updater, the count value comparator, and the maximum disturb count value storage.

The count value updater may reset the disturb count value for the second memory cell after performing an irregular refresh operation on the second memory cell.

The refresh controller inserts an irregular refresh operation sequence for the second memory cell between the current refresh schedule when the current disturb count value for the second memory cell is greater than or equal to the threshold and exceeds the maximum disturb count value. Can be prioritized.

The refresh controller performs parallel processing of the irregular refresh operation on the second memory cell with the current refresh schedule when the current disturb count value for the second memory cell is greater than or equal to the threshold and exceeds the maximum disturb count value. Can be scheduled to do so.

When the memory device is in the test mode, the count valid flag unit may deactivate the count valid flag so as not to perform an irregular refresh operation on the second memory cell.

The memory device reads a current disturb count value for the second memory cell from the disturb count cell, and further includes a count write lead block for writing the updated disturb count value to the disturb count cell. It may include.

In order to solve the above technical problem, a method of operating a memory system including a plurality of memory cells according to an embodiment of the present invention (a) at least one of the first memory cell (Access) while access (Access) Updating a disturb count value by counting a disturb value of a second memory cell adjacent to a word line of the memory cell, (b) updating the disturb amount by a maximum disturb count value and a predetermined threshold value; Changing the order of the refresh operation for the second memory cell based on a result of comparing the same; (c) if the refresh operation for the second memory cell is performed according to the order, the second memory Resetting the disturb count value of the cell.

The disturb amount is a value obtained by periodically increasing a counter during a cumulative access time for the first memory cell.

In the step (b), if the amount of disturbance of the second memory cell is equal to or larger than the threshold and is greater than the maximum disturb count value, scheduling the refresh operation of the second memory cell as a priority, the second The method may include updating a disturb amount of a memory cell to a new maximum disturb count value, and updating a non-refresh refresh flag indicating whether to perform a refresh operation on the second memory cell.

When the irregular refresh flag is activated, the operation method may further include performing a refresh operation on the second memory cell, resetting a maximum disturb count value of the second memory cell and a disturb amount of the second memory cell, and then resetting the second memory cell. The method may further include resetting the irregular refresh flag.

The method may further include enabling all word lines of the memory system to reset all of the disturb count values when the memory system is powered up.

According to the memory device, the memory system, and an operating method thereof, the refresh operation is performed more frequently on a cell in which a disturbance is concentrated, thereby improving the refresh characteristics of the corresponding cell and improving the data reliability of the memory device. .

1 is a simplified block diagram of a memory device according to example embodiments.
2 is a block diagram illustrating a memory device in accordance with an embodiment of the present invention.
3 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present invention.
FIG. 4 is a flowchart illustrating a case where the operation method of the memory device shown in FIG. 3 is initialized.
FIG. 5 is a flowchart illustrating an active state of the operating method of the memory device illustrated in FIG. 3.
FIG. 6 is a flowchart illustrating a case where the memory device is in the refresh state among the operating methods of the memory device shown in FIG. 3.
FIG. 7 is a table for describing an operation of a method of refreshing a memory cell according to example embodiments.
8A and 8B are tables for describing an operation of a method of refreshing a memory cell according to example embodiments.
9A and 9B are tables for explaining an operation of a method of refreshing a memory cell according to example embodiments.
10A and 10B are tables for describing an operation of a method of refreshing a memory cell according to example embodiments.
11A to 11C are tables for describing an operation of a method of refreshing a memory cell according to example embodiments.
FIG. 12 illustrates an embodiment of a computer system including the memory device shown in FIG. 1.
FIG. 13 illustrates another embodiment of a computer system including the memory device shown in FIG. 1.
FIG. 14 illustrates another embodiment of a computer system including the memory device shown in FIG. 1.
FIG. 15 illustrates another embodiment of a computer system including the memory device shown in FIG. 1.
FIG. 16 illustrates another embodiment of a memory system including the memory device shown in FIG. 1.
FIG. 17 illustrates an embodiment of a data processing system including the memory device shown in FIG. 1.
FIG. 18 is a conceptual diagram schematically illustrating an embodiment of a multi-chip package including the memory device shown in FIG. 1.
19 is a conceptual diagram three-dimensionally showing an embodiment of the multi-chip package shown in FIG. 18.

Specific structural and functional descriptions of embodiments according to the concepts of the present invention disclosed in this specification or application are merely illustrative for the purpose of illustrating embodiments in accordance with the concepts of the present invention, The examples may be embodied in various forms and should not be construed as limited to the embodiments set forth herein or in the application.

Embodiments in accordance with the concepts of the present invention can make various changes and have various forms, so that specific embodiments are illustrated in the drawings and described in detail in this specification or application. It is to be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms of disclosure, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Terms such as first and / or second may be used to describe various components, but the components should not be limited by the terms. The terms are intended to distinguish one element from another, for example, without departing from the scope of the invention in accordance with the concepts of the present invention, the first element may be termed the second element, The second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the terms "comprises ", or" having ", or the like, specify that there is a stated feature, number, step, operation, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

In order to prevent data loss due to leakage current, DRAM requires a refresh operation to take out data, read data, and write data back to the cell before the data stored in the cell is completely lost. The refresh characteristics of a memory cell are not determined solely by the characteristics of the cell itself, but the dynamic noise of voltages applied to the cell, the potential of a cell adjacent to the access cell, or the potential of lines passing adjacent to the memory cell. Will be affected by

The terms "normal refresh operation" and "non-regular refresh operation" as used herein are merely used to describe specific embodiments and are not intended to limit the present invention. As used herein, a regular refresh operation refers to refreshing a normal cell either internally in a memory device or according to a control command of an external system regardless of a disturb, and an Irregular Refresh Operation. In this case, the refresh schedule is adjusted in consideration of the amount of disturbance of each memory cell, and the refresh operation for the memory cell having a large amount of disturbance is performed before or in parallel with the normal refresh operation.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings.

1 is a simple block diagram of a memory device according to example embodiments. FIG. 2 is a block diagram illustrating a memory device according to an example embodiment of the present invention.

The memory device 100 of FIG. 1 includes a plurality of cell arrays 10, at least one row multiplexer ROW MUX 31, at least one row buffer 32, and at least one row decoder. ROW Decoder, 33), Bank Control Logic 40, at least one Column Buffer 510, at least one Column Decoder 52, Sense Amplifier 61, Includes Output Driver (65), Input Buffer (67), I / O Control Unit (70), Control Logic (200) and Refresh Unit (250) do.

Each of the cell arrays 10 includes a normal cell array 11 and a disturb count cell array 20. The normal cell array 11 includes cells for storing data, that is, a plurality of normal cells. The disturb count cell array 20 includes cells for storing disturb count values received by a specific cell adjacent to or adjacent to the attack cell by an attack cell in which memory access is concentrated among normal cells. . The disturb count cell array 20 also includes cells for storing disturb count values received by other cells that depend on the word line WL _k to which the specific cell (x = k) adjacent / adjacent to the attack cell belongs. do.

For example, each of the plurality of cell arrays 10 may be implemented as a dynamic random access memory (DRAM). However, the concept of the present invention is not limited to the type of memory.

The control logic 200 controls the elements 250, 31, 40, 51, and 70 in response to the signals CK, Command, and Add.

The clock signal CK may be output from a clock driver (not shown). The plurality of command / address signals Command and Add may be output from a memory controller (not shown) connected to the memory device 100.

The control logic 200 includes an address command decoder 210 and a disturb count unit DC unit 220.

The address command decoder 210 decodes a plurality of signals CK, Command, and Add, and generates a command and / or an address (eg, Sel_WL) for controlling each component according to the decoding result. .

For example, the address command decoder 210 outputs an active command, a read command, and the like to read data of the cell array 10 and adds an address of the target cell in which the data is stored. ) Can be printed together. For example, the address command decoder 210 may output a refresh command and output an address Add of a refresh target cell to preserve data of a specific cell of the cell array 10.

The bank control unit 40 schedules the refresh operation according to the command output from the control logic 200, and each bank 10-1 to 10-k performs the refresh operation according to the schedule. can do. The bank control logic 40 may select each of the plurality of banks. According to an embodiment, the number of banks including the cell array 10 may vary.

The disturb count unit 220 calculates the amount of disturbance received by the second memory cells adjacent to (or close to) the first memory cell in which memory access is concentrated. For convenience of description, a more detailed description of the disturb counter unit 220 will be given below with reference to FIG. 2.

The refresh unit 250 generates a row address ROW Add in response to a command output from the control logic 200 to perform a refresh command.

That is, in response to the memory cell or bank refresh command, the bank control logic 40 counts rows included in any one of the plurality of banks before the bank Bank to be refreshed is switched to another bank. For convenience of description, a more detailed description of the refresh unit 250 will be made with reference to FIG. 2.

The row multiplexer 31 selects one of a row address (or word line address) generated by the refresh unit 250 and a row address output from the control logic 200 in response to the selection signal (not shown). When the refresh operation is performed, the row multiplexer 31 selects the row address output from the refresh unit 250. When a write operation or a read operation is performed, the row multiplexer 31 selects a row address output from the control logic 200.

At least one row buffer 32 temporarily stores a row address output from the row multiplexer 31.

At least one row decoder 33 operates when it corresponds to a bank switched by the bank control logic 40. The row decoder 33 decodes the row address output from the corresponding row buffer 32 and selects any one row (or word line) among the plurality of rows (or word lines) according to the decoding result.

Each of the plurality of banks (10-1 to 10-N, where N is a natural number) includes a plurality of cell arrays labeled Bank 1 to Bank N and at least one sense amplifier S / A, 61).

Each of the plurality of cell arrays 10 includes a plurality of word lines (or rows), a plurality of bit lines (or columns), and a plurality of normal memory cells 11 and a disturb count for storing data. Disrupt count cell arrays 20 for storing a value.

The sense amplifier 61 senses and amplifies the voltage change of each bit line according to whether the cell stores data.

The at least one column buffer 51 temporarily stores the column address output from the control logic 200.

At least one column decoder 52 operates when it corresponds to a bank switched by the bank control logic 40. The column decoder 52 decodes the column address output from the corresponding column buffer 51 and selects any one column (or bit line) among the plurality of columns (or bit lines) according to the decoding result.

The input / output control unit 70 transmits a plurality of signals sensed and amplified by the sense amplifier 70 to the output driver 65 or the input buffer 67 according to the control signal output from the control logic 200. .

During the write operation, the input / output control unit 70 transmits the data DQi (i is a natural number) received from the input buffer 67 according to a control signal output from the control logic 200. Transfer to the normal cell array 11 through.

During the read operation, the input / output control unit 70 transmits a plurality of signals sensed and amplified from the sense amplifier 61 to the output driver 65 according to the control signal output from the control logic 200. . The output driver 65 outputs data to a memory controller (not shown).

The input / output control unit 70 may include a count write read block 75. The count write lead block 75 accesses the disturb count cell array 10 to read the current disturb count value stored in the disturb count cell and to read the updated disturb count value. Write).

Referring to FIG. 2, the disturb count unit DC unit 220 includes a count value updater 221, a count value comparator 222, and a maximum disturb count value storage unit. (Max Count Value Storage, 223), and Count Valid Flag (224).

The count value updating unit 221 converts the count value converted into a minimum refresh time / number of cycles (tRC) to the current disturb count value during the active period (time to access the first memory cell). In addition, update. For example, each time the first memory cell is accessed, a value that is periodically counted during the current access time of the first memory cell may be updated by adding a disturb count value stored at a previous access time.

The count value comparison unit 222 compares the current count value of the adjacent or adjacent cells received from the disturb count cell array 20 with a preset threshold or maximum count value. do. At this time, the predetermined threshold value is set in the count value comparison unit 222, and the maximum disturb count value is received from the maximum disturb count value storage unit 223. The count value comparison unit 222 transmits the comparison result to the next irregular refresh address and irregular refresh flag storage unit 252.

For example, if the current disturb count value is equal to or greater than the threshold value and is greater than the maximum disturb count value (count value≥Threshold, count value> Max Count Value), the second memory cell is next moved. It is intended for irregular refresh operation. The count value comparison unit 222 notifies the irregular refresh address and the irregular refresh flag storage unit 252 when the second memory cell is the target of the next irregular refresh operation.

However, if the current disturb count value is less than the threshold or equal to or less than the maximum disturb count value (count value <Threshold, count value ≤ Max Count Value), the corresponding cell is not targeted for the next irregular refresh operation.

The maximum disturb count value storage unit 223 stores a maximum value of the disturb count values for the second memory cell from the initialization time of the memory device 100 to the current operation time.

For example, when the current disturb count value (Count Value) of the second memory cell outputted from the disturb count cell array 20 through the count write read block 75 is greater than the previously stored maximum disturb count value ( count value> current MAX count value), and store (or update) the current disturb count value as a new maximum disturb count value.

The count valid flag unit 224 controls whether or not to stop the disturb count operation according to whether the count valid flag is activated. The count valid flag is deactivated when the disturb count value is nondeterministic, that is, when the count value is invalid. In addition, when the memory device 100 measures the dynamic refresh characteristic of the memory cell in the test mode or the like, the count valid flag unit 224 disables the count valid flag to stop the disturb count operation or the irregular refresh operation. Can be controlled.

That is, the count valid flag unit 224 activates the count valid flag by activating the count valid flag when all of the disturb count values of the disturb count unit 250 are reset.

Count values may not be valid when the memory device 100 is powered up. Therefore, the memory device 100 must be initialized and each word line of the disturb count cell array 20 must be enabled and updated to a reset value at the time of initialization. In this case, although the initialization time may vary depending on the characteristics of the memory device 100, the word data WL may be reset by writing the same data by enabling a plurality of word lines WL, such as testing a memory device.

For example, when the periodic internal refresh command generator 254 is activated based on the power up master signal, the periodic internal refresh command generator 254 may be a count valid flag unit. And transmits a control signal to 224. The count valid flag unit 224 is disabled in accordance with the control signal to stop the disturb counting function. That is, the values stored in the components 221, 222, and 223 are reset.

For example, when the periodic internal refresh command generator 254 is deactivated, the count valid flag unit 224 transmits a count valid flag to the count value comparator 222 to activate the disturb counting function.

The refresh unit 250 of FIG. 2 controls the refresh operation of the elements 220, 75, etc. in the memory device 100. The refresh unit 250 may include an adjacent address calculator 251, a next irregular refresh address and an irregular refresh flag storage 252, and a refresh controller 253. And a periodic internal refresh command generator 254.

The neighbor address calculator 251 may determine the cells of the word lines adjacent to or adjacent to the word line based on the address of the current cell WLx received from the address command decoder 210, that is, the addresses of the second memory cells. (WL (x ± k), k is a natural number).

The next irregular refresh address and the irregular refresh flag storage unit 252 store the irregular refresh flag and the address of a cell to perform the next refresh operation. The irregular refresh flag indicates whether to perform the next irregular refresh operation. That is, when the current disturb count value for the second memory cell is greater than or equal to the threshold and exceeds the maximum disturb count value, the address of the second memory cell is stored as a next irregular refresh address, and the second memory Whether the refresh operation is performed on the cell is reflected in the non-normal refresh flag.

The refresh controller 253 controls the refresh operation of the memory device 100 by combining the normal refresh operation and the irregular refresh operation of the memory device 100. For example, the refresh operation sequence may be scheduled according to the non-normal refresh flag.

For example, the non-regular refresh operation schedule may be inserted in the current schedule to preferentially perform the non-regular refresh operation in the current schedule. Alternatively, the irregular refresh operation may be performed in parallel with the current schedule within the current schedule.

For example, the refresh controller 253 may reset the refresh schedule under the control of the periodic internal refresh command generator 254.

The periodic internal refresh command generator 254 performs a refresh on the entire word line address (or the entire normal memory cell array) internally in the memory device based on a power up master signal, and initializes the disturb count value. .

In more detail, the periodic internal refresh command generator 254 transmits the internal refresh signal to the count valid flag 224 according to the power-up master signal.

The count valid flag 224 controls the reset count values previously stored in the elements 221, 222, and 223 according to the internal refresh signal. In this case, the power-up master signal may be received from an external system (not shown) or a memory controller (not shown) according to an embodiment.

3 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present invention.

Referring to FIG. 3, when power is supplied to the memory device 100, the power is turned on (S10), and the memory device 100 may enable all word lines to initialize all of the disturb count values of the disturb count cell array. There is (S20). For example, the memory device 100 may enable word lines of each of the plurality of memory cells, reset them to the same data value, and initialize the same.

In the idle state after the memory device is initialized (S30), the memory device 100 becomes an active state operating according to a command of a host (not shown) or refreshes the memory cells by itself for data reliability. The refresh state (Refresh State, S50).

When the memory device 100 becomes active, the memory device 100 counts respective disturb values for the remaining memory cells during an access time to the target memory cell (S40). The memory device 100 performs a read operation, a write operation, an erase operation, or the like according to a command of the host (S60), and repeatedly performs an operation of counting the amount of disturb. When the memory device 100 performs an operation according to the command, the memory device 100 precharges the target memory cell to be in an idle state again.

When the memory device 100 is in the refresh state, the memory device 100 performs a refresh operation on the remaining memory cells except for the target memory cell (S50). At this time, the refresh operation includes a normal refresh operation and an irregular refresh operation. The memory device 100 may perform a normal refresh operation according to a scheduling determined by a predetermined rule for each of the memory cells. Meanwhile, in consideration of the amount of disturbance of each of the memory cells, the memory device 100 may perform an irregular refresh operation first or in parallel with the scheduling in the case of the memory cell having the maximum disturbance amount (S50). After the refresh operation is completed, the memory device 100 enters an idle state again.

FIG. 4 is a flowchart illustrating a case where the operation method of the memory device shown in FIG. 3 is initialized.

3 and 4, when power is supplied to the memory device 100 and powered on, the periodic internal refresh command generation unit 354 is enabled (S21). Whether or not the power is on is determined according to the Power Up Master Signal. When the periodic internal refresh command generation unit 254 is enabled, the refresh controller 253 controls the disturb count value corresponding to the current refresh address to be reset (or cleared) (S22). The periodic internal refresh command generation unit 254 deactivates the count valid flag by deactivating the count valid flag to deactivate the count function of the disturb count unit 250. This is repeated until the disturb count values of all the memory cells are reset (S23). FIG. 5 is a flowchart illustrating a case in which an active state of the operating method of the memory device shown in FIG.

Referring to FIG. 5, when the address command decoder 210 receives an active command, the memory device 100 reads a word line of a corresponding address (called a target memory cell) corresponding to the active command in the normal cell array 11. Enable and read the disturb count value from the disturb count cell connected to the word line of the target memory cell (S41). The disturb count value represents the amount of disturb of remaining cells other than the target memory cell, for example, cells adjacent to (or close to) the target memory cell.

For example, the disturb amount may be expressed as a value obtained by dividing an access time of the word line WLx of the target memory cell by a unit time, that is, a minimum enable cycle (Minimum tRC or Minimum tRAS). For example, the disturb count value x may include adjacent or adjacent cells Disturb (xk) and Disturb (x + k), that is, at least one or more cells located in the left or right word line of the target memory cell, hereinafter, remaining remainder. The memory cell, k, can be divided by the disturb count value of one or more natural numbers). When the remaining memory cells x-k or x + k are refreshed, the disturb count value for the remaining memory cells is reset (or cleared) to zero after the refresh operation.

Since the memory device 10 has accessed the target memory cell x, the remaining memory cells x-k and x + k accumulate more disturb. Thus, unless it is initialized, the disturb amount is counted and the disturb count value is updated by adding the counted value to the disturb count value stored in the disturb count cell connected to the word line of the target memory cell x. The updated disturb count value is written to the read disturb cell and stored (S42). That is, the disturb amount may be a value obtained by dividing the accumulated access time by the unit time.

The updated disturb count value is compared with a predetermined value to determine whether to perform the refresh operation according to the comparison result (S43). For example, if the updated disturb count value is larger than the current maximum disturb count value or a predetermined threshold value stored in the previous step, the address of the remaining memory cell corresponding to the disturb count value is stored as an address to perform the next irregular refresh operation. (S44). The updated disturb count value is stored as a new maximum disturb count value (S45).

For example, if the updated disturb count value is smaller than the current maximum disturb count value and the predetermined threshold value stored in the previous step, the refresh operation is not performed and the address is not stored as the address and the maximum disturb count value of the next irregular refresh operation ( S43).

That is, when the active command is executed, the memory device 100 is accessible only to the word line WLx of the target memory cell x corresponding to the active command, so that the disturbance of the adjacent or adjacent cells x ± k (rest of the remaining memory cells) is possible. The count value is stored in the disturb count cell 11 connected to the word line of the target memory cell x.

For example, when the target memory cell x is multi-accessed on both sides (left and right) around one of the remaining memory cells (x + k or xk) (ie, two or more target memory cells). When each word line is intensively accessed), the amount of disturb received by the remaining memory cells is the sum of the amount of disturb received from each of the target memories on both sides. At this time, the disturb amount of the remaining memory cells stored in the disturb count cell connected to the word line of the target memory cell may store only one disturb value, so that an accurate disturb amount may not be known, thereby causing an error.

However, if the active command continues to be executed at this time, the disturb count value of each of the target memory cells of both sides is increased, and the remaining memory cells may be the target cells of the irregular refresh operation. In consideration of this, the error can be reduced. A more detailed description will be given in the description below with reference to FIG. 9A.

FIG. 6 is a flowchart illustrating a case where the memory device is in the refresh state among the operating methods of the memory device shown in FIG. 3.

Referring to FIG. 6, when the address command decoder 254 receives a refresh command, the memory device 100 performs a refresh operation. Refresh operations include regular refresh operations and irregular refresh operations. According to the refresh command, the memory device 100 determines whether to perform an irregular refresh operation (S51).

When the irregular refresh operation is not performed, that is, the memory device 100 disables the irregular refresh flag (Flag) and performs the refresh operation according to an existing schedule (S52).

However, when performing a non-normal refresh operation, the memory device 100 adjusts the refresh schedule by activating the non-normal refresh flag Flag. For example, a non-normal refresh operation may be performed on the remaining memory cells in parallel with the normal refresh operation. For example, an irregular refresh operation for the remaining memory cells may be preferentially inserted between the normal refresh operations (S53).

When the irregular refresh operation of the remaining memory cells is completed, the memory device 100 clears (or resets) the address of the remaining memory cells for the irregular refresh operation (S54). In addition, after performing the irregular refresh operation, the current maximum disturb count value previously stored is cleared (or reset) (S55).

Then, the word line of the target memory cell x, which stores the disturb count value of the remaining memory cells subjected to the irregular refresh operation, is accessed to clear (or reset) the disturb count value for the remaining memory cells (S56).

Therefore, in the memory cell access operation, the refresh schedule is adjusted to preferentially perform the refresh operation on the memory cell most vulnerable to the disturbance (ie, the memory cell having the largest disturbance amount). As a result, by limiting the amount of disturb within the refresh interval time of the memory cell, the data reliability of the memory device is increased, thereby improving the performance of the device.

FIG. 7 is a table for describing an operation of a method of refreshing a memory cell according to example embodiments.

The memory device 100 repeatedly accesses the first memory cell (target memory cell) several times based on an active command and monitors the amount of disturbance of the remaining memory cells (second memory cell) adjacent to / in proximity to the accessed target memory cell. do. The memory device 100 preferentially performs an irregular refresh operation on the second memory cell having the highest disturbance and the weakest refresh characteristic. The maximum disturb count value in the refresh interval is reset every time the irregular refresh operation is performed, and thus is limited at a constant level without increasing continuously.

Referring to FIG. 7, assume that the memory device 100 intensively accesses the first memory cell x located at ROW = 3, and the threshold is 159. Since the memory device 100 is powered up before the first access to the first memory cell (T = 0), the disturb count values of the second memory cells ROW 2 and ROW 4 that are already stored in the device are changed. Initialize That is, values (Disturb (x-1) and Disturb (x + 1)) stored in the disturb count cell connected to ROW = 3 are initialized ((ROW 2, ROW 4) = (0, 0)).

The memory device 100 accesses the first memory cell to perform an operation according to a command of a host after initialization. If access to the first memory cell is intensively repeated (T = 1 to 159), the memory device 100 counts and increases the amount of disturb during the access time of the word line ROW = 3 of the first memory cell. . For example, the disturb count value (1, 1) at the second memory cells ROW = 2 (Left) and ROW = 4 (Right) at T = 1 and the second memory cells ROW = 2 at the T = 2 The disturb count value (2,2) at ROW = 4 is increased, and each disturb count value of the second memory cells is stored and updated in the disturb count cell 20 connected to ROW = 3 every time it is counted.

In the table of FIG. 7, the gray portion ROW = 3 represents a disturb count value for second memory cells stored in the disturb count cell 20 connected to the same word line as the first memory cell 11 to be accessed. That is, since only the first address (ROW = 3) of the first memory cell in which the active command is performed is accessible, the disturb count cells are located on the same word line as the first memory cell in which the access command is performed.

The stored count value counts the amount of disturbances of the second memory cells ROW = 2 and 4 adjacent to the first memory cell during the word line enable time (accessed time) of the first memory cell.

When the active command for the first memory cell is repeatedly performed, the disturb count value of each of the two adjacent second memory cells ROW = 2, Left and ROW = 4, Right increases, resulting in at least one of the second memory cells. One is subject to irregular refresh.

The method for determining whether to perform an irregular refresh operation may include a word of ROW = 2 in FIG. 7 when the current disturb count value stored in the disturb count cell becomes larger than a threshold value (threshold = 159) (T = 160). The non-normal refresh operation is preferentially scheduled for the second adjacent memory cells belonging to the line. When the refresh operation sequence of the second memory cell comes according to a refresh schedule, the operation is performed (Refresh 2), and the disturb count value of the second memory cell is reset (ROW = 2, Disturb Count Value = 0).

Subsequently, when intensively accessing the first memory cell (ROW = 3) (T = 161 to 319), the disturb count value of the adjacent second memory cell continuously increases (in the case of ROW = 2, it continues from 0). Count, counting continues from 160 for ROW = 4). Among the second memory cells, ROW = 2 has a refresh operation, but since ROW = 4 has not performed a refresh operation, the amount of disturb for ROW = 4 increases.

If access continues to be concentrated on the first memory cell at ROW = 3 (T = 161 to 319), the second memory cell at ROW = 4 exceeds the maximum disturb count value (T = 320), thus overriding the irregular refresh operation. Scheduling When the sequence is reached according to the refresh schedule, an irregular refresh operation is performed on the second memory cell having ROW = 4 (Refresh 4). The word line of the first memory cell is enabled to reset the disturb count value of the second memory cell having ROW = 4 stored in the disturb count cell.

Each time a subsequent access to the first memory cell ROW = 3 is continued, the disturb count value for the second memory cell is continuously counted as described above. The memory device performs an irregular refresh operation on the second memory cell based on the disturb count value compared with a threshold value or a maximum disturb count value.

Thus, the maximum amount of disturbance when intensively accessing at least one non-overlapping memory cell in the memory cell array is given by the following equation. In this case, n is the number of word lines (ie, ROWs) to which the cells to be accessed intensively belong.

Since the amount of disturbance is the total time that the word line is enabled, it must be integerized by dividing the accumulated enabled time by the unit time (word line access time when tRASmin or tRCmin). For example, assuming that tREF is 64 ms and the refresh cycle time is intensively accessed at the first memory cell at 8K, the access time tRCmin of the word line to which the first memory cell belongs is 50 ns. lets do it. At this time, since tREFI becomes 7.8us, the maximum disturbance MaxDisturb received during tREFI becomes 7.8us / 50ns = 160 according to Equation 1.

8A and 8B are tables for describing an operation of a method of refreshing a memory cell according to example embodiments. 8A and 8B differ from FIG. 7 in that only one word line is accessed intensively in that access is concentrated to two word lines.

Assume that the memory device 100 has intensive access to two or more word lines, for example, first memory cells located at ROW = 3 and ROW = 6, with a threshold of 159.

In FIG. 8A, since the memory device 100 is powered up before the first access (T = 0), previously stored second memory cells ROW = 2, ROW = 4, ROW = 5, and ROW = 7. Initialize the disturb count value for. That is, each of the values Disturb (x-1) and Disturb (x + 1) stored in the disturb count cell connected to ROW = 3,6 is initialized ((ROW 2, ROW 4) = (0,0 in FIG. 9A). ) And (ROW 5, ROW 7) = (0,0)).

After initialization, the memory device 100 accesses the first memory cells (x = 3,6) located at ROW = 3,6. When access to the first memory cell is intensively repeated (T = 1 to 159), the memory device 100 accesses the first memory cell every time the second memory cell (ROW = 2, 4, 5, 7). Count the amount of disturb for.

Each of the disturb count values (ROW 2, ROW 4) and (ROW 5, ROW 7) of the second memory cells is stored in each of the disturb count cells of the first memory cell ROW = 3,6 that is accessed. The memory device 100 enables and accesses only the first memory cell corresponding to the first address (ROW = 3,6) where the active command is performed, and does not enable ROW 2, 4, 5, and 7 to which the remaining cells belong. Because it does not.

If the current disturb count value 160 of the remaining cells ROW 2, 4, 5, 7 read out from the disturb count cell is larger than the threshold (threshold = 159) (T = 160), the memory device generates a first row of ROW = 2. 2 Refresh the memory cell (Refresh 2). The memory device resets the disturb count value for the refreshed second memory cell ROW = 2 ((ROW 2, ROW 4) = (0, 160) at ROW = 3).

If the first memory cell (ROW = 3,6) is intensively accessed (T = 321-479), the disturb count value of the second memory cell is continuously increased (from 0 when ROW = 2). Count, counting continues from 160 for ROW = 4,5,7).

Among the second memory cells, ROW = 2 has a refresh operation, but since ROW = 4,5,7 has not performed a refresh operation, the disturb count value for ROW = 4,5,7 continues to increase.

If access is continuously concentrated in the first memory cells ROW = 3 and 6 (T = 321 to 480), the actual disturb count value of the second memory cell having ROW = 4 reaches the maximum disturb count value 240 (T). = 480), the memory device adjusts the schedule to preferentially perform a refresh operation on the second memory cell having ROW = 4. The memory device performs an irregular refresh operation on the second memory cell having ROW = 4 according to the adjusted schedule (Refresh 4), and resets the disturb count value of ROW = 4 (ROW 3 to (ROW 2, ROW 4)). = (80,0)).

The memory device then continues to count the disturb count value for the second memory cell each time the first memory cell ROW = 3,6 is accessed. If access is continuously concentrated in the first memory cell ROW = 3, 6, the disturb count value (ROW 2, ROW) of the second memory cell having ROW = 5 at T = 640 received by the first memory cell ROW = 6. 4) = (320,320) not only exceeds the threshold (thereshold = 159) but also exceeds the maximum disturb count value 240. In this case, the memory device performs an irregular refresh operation on the second memory cell where ROW = 4 (ROW2, ROW4) = (0,320).

Similarly, in FIG. 8B, each time the first memory cell is accessed, the disturb count value of the second memory cell is continuously updated, and the disturb count value is compared with a threshold value or a maximum disturb count value. Decide That is, the memory device may adjust the schedule of the operation sequence to perform the irregular refresh operation even during the normal refresh operation based on the disturb count value for the second memory cell.

As a result, the size of the maximum disturb count value is increased as compared to non-overlapping access of one word line as in the embodiment of FIG. 7, but the memory device 100 may not determine the current disturb count value even if the maximum disturb count value is increased. Since the refresh schedule is adjusted based on, the maximum disturb count value is ultimately limited even if the access is continuously concentrated in the first memory cell (the maximum disturb count value = 400 in FIG. 8B).

As such, when the memory device intensively accesses at least two or more memory cells, at least one adjacent / adjacent memory cell receives a disturbance, respectively, where the maximum amount of disturbance is as follows. In this case, n is the number of word lines to which the intensively accessed cell belongs.

Since the amount of disturbance is the total time that the word line is enabled, it must be integerized by dividing the accumulated enabled time by the unit time (word line access time when tRASmin or tRCmin). Equation 2 is an increasing function, when n is infinite, the maximum disturb count value converges at 480. 480 x tRC becomes 24us (where tRC = 50ns), which is a worst case when at least one of the remaining memory cells does not receive overlapping disturbances from the target memory cell.

9A and 9B are tables for explaining an operation of a method of refreshing a memory cell according to example embodiments. 9A and 9B differ from FIGS. 8A and 8B in that access is concentrated in two non-adjacent word lines in that access is concentrated in two adjacent word lines.

 Assume that the memory device 100 intensively accesses two or more word lines, for example, first memory cells located at ROW 3 and ROW 5, and has a threshold of 159.

In FIG. 9A, since the memory device 100 is powered up before the first access (T = 0), disturb for the previously stored second memory cells ROW = 2, ROW = 4, and ROW = 6. Initialize the count value. That is, each of the values Disturb (x-1) and Disturb (x + 1) stored in the disturb count cell connected to ROW = 3,5 is initialized ((ROW 2, ROW 4) = (0,0 in FIG. 9A). ) And (ROW 4, ROW 6) = (0,0)).

The memory device 100 accesses the first memory cell x located at ROW = 3 after initialization. When access to the first memory cell is intensively repeated (T = 1 to 159), each time the memory device 100 accesses the first memory cell, the memory device 100 may access the second memory cell ROW = 2,4,6. The disturb count value is counted. In contrast to FIG. 7, the second memory cell having ROW = 4 among the second memory cells of the word lines to which access is concentrated receives overlap disturbances from ROW = 3 and ROW = 5, respectively.

Each of the disturb count values (ROW 2, ROW 4) and (ROW 4, ROW 6) of the second memory cells is stored in each of the disturb count cells of the first memory cell ROW = 3,5 that is accessed. This is because the memory device 100 may access only the first memory cell corresponding to the first address ROW = 3,5 where the active command is performed. At this time, since the second memory cell of ROW = 4 receives the disturbances superimposed, the sum of the disturb count values stored in each of the disturb count cells of the first memory cell ROW = 3,5 adds up to the actual amount of disturbance (Fig. Effective 9) becomes 9a.

When the current disturb count value 160 read from the disturb count cell is greater than the threshold value threshold = 59 (T = 160), the memory device refreshes the second memory cell having ROW = 2 (Refresh 2). The memory device resets the disturb count value for the refreshed second memory cell ROW = 2 (ROW = 2, Disturb Count Value = 0).

If intensively accesses the first memory cell (ROW = 3,5) (T = 321-479), the disturb count value of the second memory cell continuously increases (continuously from 0 when ROW = 2). Count, counting continues from 160 for ROW = 4,6).

Among the second memory cells, ROW = 2 has a refresh operation, but since ROW = 4,6 has not performed a refresh operation, the disturb count value for ROW = 4,6 continues to increase.

If access is continuously concentrated in the first memory cells ROW = 3 and 5 (T = 321 to 480), the actual disturb count value of the second memory cell having ROW = 4 reaches the maximum disturb count value (T = 480). The memory device adjusts a schedule to preferentially perform a refresh operation on the second memory cell having ROW = 4. The memory device performs an irregular refresh operation on the second memory cell having ROW = 4 according to the adjusted schedule (Refresh 4), and resets the disturb count value of ROW = 4 (ROW 3 to (ROW 2, ROW 4)). = (80,0)).

The memory device then continues to count the disturb count value for the second memory cell each time the first memory cell ROW = 3,5 is accessed. If access is continuously concentrated in the first memory cell ROW = 3, 5, the actual disturb count value of the second memory cell where ROW = 4 at T = 640 received by the first memory cell ROW = 5 (effective 4 = 160 ) Exceeds the threshold (thereshold = 159). In this case, the memory device performs an irregular refresh operation on the second memory cell having ROW = 4.

Likewise, in FIG. 9B, each time the first memory cell is accessed, the disturb count value of the second memory cell is continuously updated, and the disturb count value is compared with a threshold value or a maximum disturb count value, and thus the order of the irregular refresh operation is determined. Decide That is, the memory device may adjust the schedule of the operation sequence to perform the irregular refresh operation even during the normal refresh operation based on the disturb count value for the second memory cell.

As a result, the size of the maximum disturb count value is increased rather than non-overlapping access of at least one word line as in the embodiment of FIG. Since the refresh schedule is adjusted based on the value, the maximum disturb count value is ultimately limited even if access is concentrated in the first memory cell.

As such, when the memory device intensively accesses at least two or more memory cells, at least one adjacent / adjacent memory cell receives an overlapped disturbance, where the maximum disturb count value MaxDistrub is represented by Equation 3 below. In this case, n is the number of word lines to which the intensively accessed cell belongs.

10A and 10B are tables for describing an operation of a method of refreshing a memory cell according to example embodiments. 10A and 10B differ from FIG. 7 in that only one word line is accessed intensively in that access is concentrated on three word lines.

Assume that the memory device 100 has intensive access to two or more word lines, for example, first memory cells located at ROW = 1, ROW = 4, and ROW = 7, with a threshold of 159.

In FIG. 10A, since the memory device 100 is powered up before the first access (T = 0), the previously stored second memory cells ROW = 0,2,3,5,6,8 are stored. Initializes the disturb count value. That is, each of the values (Disturb (x-1), Disturb (x + 1)) stored in the disturb count cell connected to ROW = 1, 4, 7 is initialized ((ROW 0, ROW 2) = (0 in FIG. 10A). , 0), (ROW 3, ROW 5) = (0,0) and (ROW 6, ROW 8) = (0,0)).

The memory device 100 accesses first memory cells (target memory cells) located at ROW = 1, 4, 7 after initialization. When the access to the first memory cell is intensively repeated (T = 1 to 480), the memory device 100 may access the second memory cell ROW = 0, 2, 3, 5, every time the first memory cell is accessed. Count the amount of disturbances for 6,8). For convenience of explanation, it is assumed that the second memory cell does not receive the disturbance from the first memory cell other than the first memory cell of the nearest word line. For example, it is assumed that the second memory cell at ROW = 2 receives no disturb from ROW = 4 or ROW = 7, and receives only the disturb by ROW = 1.

Each of the disturb count values ((ROW 0, ROW 2), (ROW 3, ROW 5), (ROW 6, ROW 8) of the second memory cells is accessed in the first memory cell (ROW = 1, 4, 7). Are stored in each of the disturb count cells. The memory device 100 enables and accesses only the first memory cell corresponding to the first address (ROW = 1, 4, 7) in which the active command is performed, and the rows 0, 2, 3, 5, and 6 to which the remaining cells belong. , 8 is not enabled.

If the current disturb count value 160 of the remaining cells ROW 0,2,3,5,6,8 read from the disturb count cell is larger than the threshold (threshold = 159) (T = 480), then the memory device ROW The second memory cell of = 0 is refreshed (Refresh 0). The memory device resets the disturb count value for the refreshed second memory cell ROW = 0 ((ROW 0, ROW 2) = (0, 160) at ROW = 1).

Subsequently, when the intensive access to the first memory cells ROW = 1, 4, and 7 is performed (T = 481 to 639), the disturb count value of the second memory cell is continuously increased (0 when ROW = 0). Counting starts from 160 and counts from 160 for ROW = 2,3,5,6,8). Among the second memory cells, ROW = 0 has a refresh operation, but since ROW = 2,3,5,6,8 has not performed a refresh operation, the disturb count value for ROW = 2,3,5,6,8 Continues to increase.

If access is continuously concentrated in the first memory cells ROW = 1, 4, and 7 (T = 481 to 640), the actual disturb count value of the second memory cell having ROW = 2 reaches the maximum disturb count value 214. (T = 640), the memory device adjusts the schedule to preferentially perform a refresh operation on the second memory cell having ROW = 2. The memory device performs an irregular refresh operation on the second memory cell having ROW = 2 according to the adjusted schedule (Refresh 2), and resets the disturb count value of ROW = 2 (ROW 1 to (ROW 0, ROW 2)). = (54,0)).

10A and 10B, the memory device 100 continuously counts the disturb count value for the second memory cell each time the first memory cell ROW = 1, 4, 7 is accessed. If access to the first memory cell (ROW = 1, 4, 7) continues to be concentrated, the disturb count values of the second memory cell exceed the threshold (thereshold = 159) or the maximum disturb at T = 800,960,1120,1280, respectively. The non-normal refresh operation is performed on the second memory cell exceeding the count value 426 (Refresh 3, 5, 6, 8).

Similarly, each time the first memory cell is accessed, the disturb count value of the second memory cell is continuously updated, and the disturb count value is compared with a threshold value or a maximum disturb count value, thereby determining the order of the irregular refresh operation. That is, the memory device may adjust the schedule of the operation sequence to perform the irregular refresh operation even during the normal refresh operation based on the disturb count value for the second memory cell.

As a result, the size of the maximum disturb count value increases as compared to non-overlapping access of only one word line as in the embodiment of FIG. Since the refresh schedule is adjusted on the basis of the above, even if access is continuously concentrated in the first memory cell, the maximum disturb count value is ultimately limited (the maximum disturb count value = 426 in FIG. 10B).

As such, when the memory device intensively accesses at least two or more memory cells, at least one adjacent / adjacent memory cell receives a disturbance, respectively, where the maximum disturb count value is limited by Equation 4. In this case, n is the number of word lines to which the intensively accessed cell belongs.

Since the amount of disturbance is the total time that the word line is enabled, it must be integerized by dividing the accumulated enabled time by the unit time (word line access time when tRASmin or tRCmin).

11A to 11C are tables for describing an operation of a method of refreshing a memory cell according to example embodiments. 11A and 11B intensively access only one word line in that access is concentrated on three adjacent word lines, and memory cells located in at least three word lines among the remaining memory cells receive overlapping disturbances. 10a to 10b.

Assume that the memory device 100 intensively accesses four memory lines, for example, first memory cells located at ROW = 1, 3, 5, and 7, and has a threshold of 159.

In FIG. 11A, since the memory device 100 is powered up before the first access (T = 0), disturb for the previously stored second memory cells ROW = 0, 2, 4, 6, and 8 Initialize the count value.

The memory device 100 accesses first memory cells (target memory cells) located at ROW = 1,3,5,7 after initialization. When access to the first memory cell is intensively repeated, the memory device 100 may access the second memory cell ROW = 0, 2, whenever the first memory cell ROW = 1, 3, 5, 7 is accessed. Count the amount of disturb for 4,6,8). In this case, ROW = 2, 4, and 6 are positioned in the middle of the first memory cells and receive the disturbances from both sides.

Each of the disturb count values of the second memory cells is stored in each of the disturb count cells of the first memory cell ROW = 1, 3, 5, and 7 which are accessed. In this case, the disturb count value of ROW = 2,4,6 stored in ROW = 1,3,5,7 is taken into account only by the disturbance by ROW = 1,3,5,7, so that ROW = 2,4,6 is The disturbance actually received is the sum of the disturbances received by ROW 1,3,5,7 (for example, T = 640 at ROW = 2 and ROW = 1 at ROW = 1 is 160 and ROW = 2 Since the disturb count value received by ROW = 3 is 160, the actual disturb count value (E2) received by ROW = 2 is 160 + 160 = 320)

If the current disturb count value of the remaining cells ROW = 0,2,4,6,8 read from the disturb count cell becomes larger than the threshold value = 159, the memory device refreshes the second memory cell of ROW = 0. (Refresh 0 at T = 640). The memory device resets the disturb count value for the refreshed second memory cell ROW = 0.

In FIGS. 11A to 11C, the memory device 100 continuously counts the discontinuity count value for the second memory cell every time the first memory cell ROW = 1, 3, 5, 7 is accessed, and the threshold value or the maximum value. Adjust the irregular refresh order by comparing the disturb count value. If access is continuously concentrated in the first memory cells ROW = 1,3,5,7, the threshold count values of the second memory cells are thresholded at T = 800,960,1120,1280,1440,1600,1760, respectively. = 159) or exceeds the maximum disturb count value 720, and performs an irregular refresh operation on the second memory cell (T = 800,960,1120,1280,1440,1600,1760). , 4,6,6,8). That is, since the second memory cells that receive overlapped disturbances consider the disturb count value for each word line, the refresh operation may be overlapped.

As a result, the magnitude of the maximum disturb count value is greater than when accessing only one word line as shown in the embodiment of FIG. 7 or when accessing two or more word lines as shown in the embodiments of FIGS. 10A and 10B. However, even if the maximum disturb count value is taken into consideration, the memory device 100 adjusts the refresh schedule based on the current disturb count value, so that the maximum disturb count value is ultimately increased even though the access is continuously concentrated in the first memory cell. Is limited (maximum disturb count value = 720 in FIG. 11B, and maximum disturb count value = 560 in subsequent loops).

As described above, when the memory device intensively accesses at least two or more memory cells, at least one adjacent / proximity memory cell receives a disturbance, and the maximum disturb count value is limited by Equation 5 below. In this case, n is the number of word lines to which the intensively accessed cell belongs.

Since the amount of disturbance is the total time that the word line is enabled, it must be integerized by dividing the accumulated enabled time by the unit time (word line access time when tRASmin or tRCmin). Equation 5 is an increasing function for all the regions of n and n converges to 960 at infinity. From tRC = 50ns to n * tRC = 960 * 50ns, this is 48us, which is the worst case.

FIG. 12 illustrates an embodiment of a computer system including the memory device shown in FIG. 1.

Referring to FIG. 12, a computer system 300 including the memory device 100 shown in FIG. 1 may be a cellular phone, a smart phone, a personal digital assistant, or a wireless communication device. It can be implemented as.

The computer system 300 includes a memory device 100 and a memory controller 320 that can control operations of the memory device 100. The memory controller 320 may control a data access operation of the memory device 100, for example, a write operation or a read operation, under the control of the host 310.

Data in the memory device 100 may be displayed through the display 330 under the control of the host 310 and the memory controller 320. The radio transceiver 340 may transmit or receive a radio signal through the antenna ANT. For example, the radio transceiver 340 may convert a radio signal received through the antenna ANT into a signal that can be processed by the host 310. Accordingly, the host 310 may process a signal output from the wireless transceiver 340 and transmit the processed signal to the memory controller 320 or the display 330. The memory controller 320 may store a signal processed by the host 310 in the memory device 100.

In addition, the wireless transceiver 340 may convert a signal output from the host 310 into a wireless signal and output the changed wireless signal to an external device through the antenna ANT. The input device 350 is a device capable of inputting a control signal for controlling the operation of the host 310 or data to be processed by the host 310. The input device 350 may include a touch pad and a computer mouse. The same may be implemented with a pointing device, a keypad, or a keyboard.

The host 310 may display the data output from the memory controller 320, the data output from the wireless transceiver 340, or the data output from the input device 350 through the display 330. Can control the operation of.

According to an embodiment, the memory controller 320 that can control the operation of the memory device 100 may be implemented as part of the host 310 or may be implemented as a chip separate from the host 310.

FIG. 13 illustrates another embodiment of a computer system including the memory device shown in FIG. 1.

Referring to FIG. 13, a computer system 400 including the memory device 100 illustrated in FIG. 1 may be a personal computer, a network server, a tablet PC, or a net-book. It may be implemented as a book, an e-reader, a personal digital assistant, a portable multimedia player (PMP), an MP3 player, or an MP4 player.

The computer system 400 includes a host 410, a memory device 100, and a memory controller 420, a display 430, and an input device 440 that can control data processing operations of the memory device 100. .

The host 410 may display data stored in the memory device 420 through the display 440 according to data input through the input device 450. For example, the input device 450 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard. The host 410 may control the overall operation of the computer system 400 and may control the operation of the memory controller 420.

According to an embodiment, the memory controller 420 capable of controlling the operation of the memory device 100 may be implemented as a part of the host 410, or may be implemented as a chip separate from the host 410.

FIG. 14 illustrates another embodiment of a computer system including the memory device shown in FIG. 1.

Referring to FIG. 14, the computer system 500 including the memory device 100 illustrated in FIG. 1 may be implemented as an image processing device, such as a digital camera or a mobile phone or a smartphone to which a digital camera is attached. Can be.

The computer system 500 includes a memory controller 520 that can control data processing operations, such as a write operation or a read operation, of the host 510, the memory device 100, and the memory device 100. In addition, computer system 500 further includes an image sensor 530 and a display 540.

The image sensor 530 of the computer system 500 converts the optical image into digital signals, and the converted digital signals are sent to the host 510 or the memory controller 520. Under the control of the host 510, the converted digital signals may be displayed through the display 540 or stored in the memory device 100 through the memory controller 520.

In addition, the data stored in the memory device 100 is displayed through the display 540 under the control of the host 510 or the memory controller 520.

According to an embodiment, the memory controller 520 capable of controlling the operation of the memory device 100 may be implemented as part of the host 510 or may be implemented as a separate chip from the host 510.

FIG. 15 illustrates another embodiment of a computer system including the memory device shown in FIG. 1.

Referring to FIG. 15, a computer system 600 including the memory device 100 illustrated in FIG. 1 includes a memory device 100 and a host 610 that can control operations of the memory device 100. . The memory device 100 illustrates that the memory device 100 is implemented as a nonvolatile memory such as a flash memory. The computer system 600 further includes a system memory 620, a memory interface 630, an ECC block 640, and a host interface 650.

Computer system 600 includes system memory 620 that can be used as an operation memory of host 610. The system memory 620 may be implemented as a nonvolatile memory such as read only memory (ROM) and may be implemented as a volatile memory such as static random access memory (SRAM).

The host connected to the computer system 600 may perform data communication with the memory device 100 through the memory interface 630 and the host interface 650.

According to the control of the host 610, an error correction code (ECC) block 640 detects an error bit included in data output from the memory device 100 through the memory interface 630. The error bits may be corrected and the error corrected data may be transmitted to the host HOST through the host interface 650. The host 610 may control data communication between the memory interface 630, the ECC block 640, the host interface 650, and the system memory 620 via the bus 670.

Computer system 600 may be implemented as a flash memory drive, a USB memory drive, an IC-USB memory drive, or a memory stick.

FIG. 16 illustrates another embodiment of a memory system including the memory device shown in FIG. 1.

Referring to FIG. 16, the memory system 700 including the memory device 100 illustrated in FIG. 1 may be implemented as a host computer 710, a memory card, or a smart card. Can be. The memory system 700 includes a host computer 710 and a memory card 730.

The host computer 710 includes a host 740 and a host interface 720. The memory card 730 includes a memory device 100, a memory controller 750, and a card interface 760. The memory controller 750 may control the exchange of data between the memory device 100 and the card interface 760.

According to an embodiment, the card interface 760 may be a secure digital (SD) card interface or a multi-media card (MMC) interface, but is not limited thereto.

When the memory card 730 is mounted in the host computer 710, the card interface 570 may interface data exchange between the host 740 and the memory controller 750 according to the protocol of the host 740.

According to an embodiment, the card interface 760 may support a universal serial bus (USB) protocol and an interchip (IC) -USB protocol. Here, the card interface may refer to hardware capable of supporting a protocol used by the host computer 710, software mounted on the hardware, or a signal transmission scheme.

When the memory system 700 is connected with the host interface 720 of the host computer 710, such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box, The host interface 720 may perform data communication with the memory device 100 through the card interface 760 and the memory controller 750 under the control of the host 740.

FIG. 17 illustrates an embodiment of a data processing system including the memory device shown in FIG. 1.

MOD (E / O) shown in FIG. 17 means an optical modulator used as an all-optical converter for converting an electrical signal into an optical signal, and DEM (O / E) is an optical modulator for converting an optical signal into an electrical signal. Means an optical demodulator used as a pre-converter.

Referring to FIG. 17, the data processing system 800 includes a CPU 810, a plurality of data buses 801-1 to 801-3, and a plurality of memory modules 840.

Each of the plurality of memory modules 840 is optically connected through each of the plurality of couplers 811-1, 811-2, and 811-3 connected to each of the plurality of data buses 801-1 to 801-3. You can give or receive signals.

According to an embodiment, each of the plurality of couplers 811-1, 811-2, and 811-3 may be implemented as an electrical coupler or an optical coupler.

The CPU 810 may include a first optical transceiver 816 including at least one optical modulator (MOD (E / O)) and at least one optical demodulator (DEM (O / E)), and a memory controller 812. Include. At least one optical demodulator (DEM (O / E)) is used as the photoelectric converter.

The memory controller 812 may control an operation of the first optical transceiver 816, for example, a transmission operation or a reception operation, under the control of the CPU 810.

For example, during a write operation, the first optical modulator (MOD (E / O)) of the first optical transceiver 816 modulates the addresses and control signals by the optical modulators under the control of the memory controller 812. May be generated, and the generated optical signal ADD / CTRL may be transmitted to the optical communication bus 801-3.

After the first optical transceiver 816 transmits the optical signal ADD / CTRL to the optical communication bus 801-3, the second optical modulator MOD (E / O) of the first optical transceiver 816 The modulated optical light data WDATA may be generated and the generated optical light data WDATA may be transmitted to the optical communication bus 801-2.

Each memory module 840 includes a second optical transceiver 830 and a plurality of memory devices 80.

Each memory module 840 includes an optical dual in-line memory module (DIMM), an optically fully buffered DIMM, an optical small outline dual in-line memory module (SO-DIMM), an optical registered DIMM (RDIMM), and an optical LRDIMM (Load). Reduced DIMMs, UDIMMs (Unbuffered DIMMs), optical MicroDIMMs, or optical single in-line memory modules (SIMMs).

Referring to FIG. 17, the optical demodulator DEM (O / E) implemented in the second optical transceiver 830 demodulates and demodulates the optical light data WDATA input through the optical communication bus 801-2. The signal may be transmitted to at least one of the plurality of memory devices 80.

According to an embodiment, each memory module 840 may further include an electrical buffer 833 for buffering the electrical signal output from the optical demodulator DEM (O / E).

For example, the electrical buffer 833 may buffer the demodulated electrical signal and transmit the buffered electrical signal to at least one of the plurality of memory devices 100.

In the read operation, the electrical signal output from the memory device 100 is modulated into the optical read data RDATA by the optical modulator MOD (E / O) implemented in the second optical transceiver 830. The optical read data RDATA is transmitted to the first optical demodulator DEM (O / E) implemented in the CPU 810 through the optical communication bus 801-1. The first optical demodulator DEM demodulates the optical read data RDATA and transmits the demodulated electrical signal to the memory controller 812.

FIG. 18 is a conceptual diagram schematically illustrating an embodiment of a multi-chip package including the memory device shown in FIG. 1.

Referring to FIG. 18, the multi-chip package 900 may include a plurality of semiconductor devices 930 ˜ 950 (Chip # 1 ˜ Chip # 3) sequentially stacked on the package substrate 910. Each of the semiconductor devices 930 to 950 may include the memory device 100 described above. A memory controller (not shown) for controlling operations of each of the plurality of semiconductor devices 930 to 950 may be provided inside one or more semiconductor devices of the plurality of semiconductor devices 930 to 950, and may include a package substrate ( It may be implemented on 910. In order to electrically connect the semiconductor devices 930 to 950, a through-silicon via (TSV), a connection line (not shown), a bump (not shown), and a solder ball 920 are provided. And the like can be used.

For example, the first semiconductor device 930 may be a logic die, and may include an input / output interface device and a memory controller, and the second semiconductor device 940 and the third semiconductor device 950 may include a plurality of memory devices. Each stacked die may include a memory cell array. In this case, the memory device and the third semiconductor device 950 of the second semiconductor device 940 may be the same type of memory device or different types of memory devices, depending on the embodiment.

In another example, each of the first to third semiconductor devices 930 to 950 may include a respective memory controller. In this case, the memory controller may be on the same die as the memory cell array or may be on a different die from the memory cell array.

As another example, the first semiconductor devices Die 1 and 930 may include an optical interface device. The memory controller may be located in the first semiconductor device 930 or the second semiconductor device 940, and the memory device may be located in the second semiconductor device 940 or the third semiconductor device 950 to penetrate the memory controller and the silicon. It may be connected to the electrode TSV.

In addition, the above embodiments may be implemented as a hybrid memory cube (HMC) having a structure in which a memory controller and a memory cell array die are stacked. Implementing with HMC reduces power consumption and production costs by improving memory device performance due to increased bandwidth and minimizing the footprint of the memory device.

19 is a conceptual diagram three-dimensionally showing an embodiment of the multi-chip package shown in FIG. 18.

Referring to FIG. 19, the multi-chip package 900 ′ may include a plurality of dies Die 1 to 3 and 930 to 950 interconnected through a silicon through electrode TSV 960. Each of the dies 1 to 3 and 930 to 950 may include a plurality of circuit blocks (not shown) and a peripheral circuit for implementing the functions of the memory device 100. The dies 930 ˜ 950 may be referred to as cell layers, and the plurality of circuit blocks may be implemented as memory blocks.

The silicon through electrode 960 may be made of a conductive material including a metal such as copper (Cu), disposed in the center of the silicon substrate, and the silicon substrate may have a structure surrounding the silicon through electrode 960. An insulating region (not shown) may be disposed between the silicon through electrode 960 and the silicon substrate.

The method of operating a memory device according to embodiments of the present invention may also be embodied as computer readable codes on a computer readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored.

Examples of the computer-readable recording medium include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like.

The computer readable recording medium may also be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner. And functional programs, codes, and code segments for implementing the present invention can be easily inferred by programmers skilled in the art to which the present invention pertains.

While the present invention has been described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the scope of the present invention. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

10-1 to 10-N: memory cell array
11: normal cell array 20: disturb count cell array
31: ROW MUX 32: ROW Buffer
33: ROW Decoder 40: Bank Control Logic
51: Column Buffer 52: Column Decoder
61: Sense Amplifier 70: I / O Control Unit
100: memory device
200: control logic
210: address command decoder
220: Disturb Count Unit
221: count value updating unit 222: count value comparison unit
223: maximum disturb count value storage unit
224: Count Valid Flag Unit
250: refresh unit
251: adjacent address calculation unit
252: Next irregular refresh address and irregular refresh flag storage unit
253: refresh controller 254: periodic internal refresh command generation unit

Claims (20)

In the operating method of a memory device including a plurality of memory cells,
(a) each time the first memory cell is accessed, counting the amount of disturbances of the second memory cell adjacent to the first memory cell to update the disturb count value for the second memory cell;
(b) adjusting a refresh operation schedule according to a result of comparing the disturb count value of the second memory cell with a preset threshold value and a maximum disturb count value; And
(c) resetting the disturb count value and the maximum disturb count value of the second memory cell when the second memory cell is refreshed according to the adjusted schedule. The method of claim 1 wherein the disturb amount is
And a cumulative access time of the first memory cell divided by unit time. The method of claim 1, wherein the disturb count value is
And each time the first memory cell is accessed, it is updated by adding a value that is periodically counted during the current access time of the first memory cell to a disturb count value stored at a previous access time. The method of claim 1, wherein step (b)
Advancing a refresh operation sequence for the second memory cell in the schedule when the disturb count value of the second memory cell is greater than or equal to the threshold and exceeds the maximum disturb count value; And
Updating the maximum disturb count value to the disturb count value of the second memory cell. The method of claim 1, wherein step (c)
A memory for controlling a refresh operation according to a schedule by activating a non-normal refresh flag after the memory device is powered up, and when the memory device is in a test mode, deactivating the non-normal refresh flag to stop the refresh operation. How the device works. The method of claim 5, wherein the irregular refresh flag is reset when the second memory cell is refreshed. The method of claim 1, wherein the operation method is
And initializing the disturb count values of the memory device when the memory device is initialized by being powered up. A memory cell array including a plurality of memory cells;
When accessing at least one first memory cell of the plurality of memory cells, the current disturb count value is read for a second memory cell adjacent to the first memory cell, and the current disturb count value is preset to a threshold and a maximum disturb. Control logic for comparing the count value and counting the disturb amount of the second memory cell during the current access time of the first memory cell to update the disturb count value; And
Calculates a word line address of the second memory cell, adjusts a current refresh schedule for the second memory cell according to a comparison result of the disturb count value, and performs a refresh operation of the second memory cell; And a refresh unit to control whether to initialize the refresh operation based on the refresh operation. The method of claim 8, wherein the memory cell array
A normal cell array including a plurality of the first memory cells for storing data; And
A disturb count cell array including a plurality of disturb count cells for storing the disturb count value,
At least one disturb count cell belongs to the same word line as the first memory cell. The method of claim 8, wherein the control logic
Receiving a clock signal, an active command, and an address from a host, decoding the signal into control signals corresponding to the command based on the clock signal, and decoding the address into a row address and a column address for accessing the first memory cell; An address comment decoder;
A count value comparison unit comparing the read current disturb count value with the threshold value and the maximum disturb count value;
A count value updater for updating each time the first memory cell is accessed by adding a value that is periodically counted during the current access time of the first memory cell to a disturb count value stored at a previous access time; And
Storing a maximum disturb count value among the disturb count values for the second memory cell from an initialization time point of the memory device to a current operation time point, and if the updated disturb count value is greater than a current maximum disturb count value, the update is performed. And a maximum disturb count value storage unit for updating the calculated disturb count value to the maximum disturb count value. The method of claim 8, wherein the refresh unit
A neighbor address calculator configured to calculate an address for the second memory cell based on the address for the first memory cell received from the control logic;
If the current disturb count value for the second memory cell is greater than or equal to the threshold and exceeds the maximum disturb count value, the address of the second memory cell is stored as a next irregular refresh address and stored in the second memory cell. A next non-normal refresh address and a non-normal refresh flag storage unit reflecting whether or not a non-normal refresh operation is performed in a non-normal refresh flag; And
And a refresh controller that adjusts the current refresh schedule to preferentially perform an irregular refresh operation of the second memory cell according to the irregular refresh flag. The method of claim 11, wherein the refresh unit
And a periodic internal refresh command generation unit configured to refresh all of the memory cell arrays based on the power-up signal, and output an internal refresh signal for controlling to initialize the disturb count value.
The control logic is
And a count valid flag unit for activating a count valid flag according to the internal refresh signal to reset the count value updater, the count value comparator, and the maximum disturb count value storage. The method of claim 10, wherein the count value updating unit
And resetting the disturb count value for the second memory cell after performing an irregular refresh operation on the second memory cell. The method of claim 11, wherein the refresh controller
If the current disturb count value for the second memory cell is greater than or equal to the threshold and exceeds the maximum disturb count value, the non-normal refresh operation sequence for the second memory cell is inserted between the current refresh schedules and prioritized. Memory device. The method of claim 11, wherein the refresh controller
A memory for scheduling an irregular refresh operation sequence for the second memory cell to be processed in parallel with the current refresh schedule when the current disturb count value for the second memory cell is greater than or equal to the threshold and exceeds the maximum disturb count value. Device. The method of claim 12, wherein the count valid flag unit
And when the memory device is in a test mode, deactivating the count valid flag so as not to perform an irregular refresh operation on the second memory cell. 10. The method of claim 9,
The memory device may further include a count write read block configured to read a current disturb count value for the second memory cell from the disturb count cell, and to write the updated disturb count value to the disturb count cell. . In the operating method of a memory system including a plurality of memory cells,
(a) updating a disturb count value by counting a disturb value of a second memory cell adjacent to a word line of the first memory cell while accessing at least one first memory cell; step;
(b) changing an order of a refresh operation on the second memory cell based on a result of comparing the updated disturb amount with a maximum disturb count value and a predetermined threshold value;
(c) resetting the disturb count value of the second memory cell when the refresh operation is performed on the second memory cell according to the order;
The disturb amount
A method of periodically increasing a counter during a cumulative access time for the first memory cell. 19. The method of claim 18, wherein step (b)
Scheduling refresh operations of the second memory cell with priority if the disturb amount of the second memory cell is equal to or greater than the threshold and greater than the maximum disturb count value;
Updating the disturb amount of the second memory cell to a new maximum disturb count value;
Updating a irregular refresh flag indicating whether to perform a refresh operation on the second memory cell;
Performing a refresh operation on the second memory cell when the irregular refresh flag is activated; And
And resetting the irregular refresh flag after resetting a maximum disturb count value of the second memory cell and a disturb amount of the second memory cell. The method of claim 18, wherein the operation method
Enabling all word lines of the memory system to reset all of the disturb count values when the memory system is powered up.

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