KR20130126321A - Intergrated circuit - Google Patents

Intergrated circuit Download PDF

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Publication number
KR20130126321A
KR20130126321A KR1020120050360A KR20120050360A KR20130126321A KR 20130126321 A KR20130126321 A KR 20130126321A KR 1020120050360 A KR1020120050360 A KR 1020120050360A KR 20120050360 A KR20120050360 A KR 20120050360A KR 20130126321 A KR20130126321 A KR 20130126321A
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KR
South Korea
Prior art keywords
calibration
unit
control signal
clock
control
Prior art date
Application number
KR1020120050360A
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Korean (ko)
Inventor
송청기
Original Assignee
에스케이하이닉스 주식회사
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Publication date
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Priority to KR1020120050360A priority Critical patent/KR20130126321A/en
Publication of KR20130126321A publication Critical patent/KR20130126321A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance

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Abstract

An integrated circuit according to an embodiment of the present invention, the calibration unit for generating an impedance code for adjusting the termination impedance value; A control signal input unit which receives at least one control signal from an external source and is inactivated in an operation section of the calibration unit; And a calibration controller configured to decode the at least one control signal transmitted from the control signal input unit to activate / deactivate the operation of the calibration unit.

Description

Integrated Circuits {INTERGRATED CIRCUIT}

The present invention relates to an integrated circuit using an impedance control circuit for generating an impedance code for adjusting an impedance value.

Various semiconductor devices implemented as integrated circuit chips such as CPUs, memories and gate arrays are incorporated into various electrical products such as personal computers, servers or workstations. In most cases, the semiconductor device has a receiving circuit for receiving various signals transmitted from the outside through an input pad and an output circuit for providing an internal signal to the outside through an output pad.

On the other hand, as the operating speed of electrical products is increased, the swing width of signals interfaced between semiconductor devices is gradually decreasing. The reason is to minimize the delay time for signal transmission. However, as the swing width of the signal decreases, the influence on external noise increases, and the reflection of the signal due to impedance mismatching (also referred to as mismatch) at the interface stage becomes more severe. The impedance mismatch occurs due to external noise, fluctuations in power supply voltage, change in operating temperature, change in manufacturing process, or the like. When impedance mismatching occurs, high-speed data transfer is difficult and output data output from the data output terminal of the semiconductor device may be distorted. Therefore, when the semiconductor device on the receiving side receives the distorted output signal to the input terminal, problems such as setup / hold fail or input level determination error may occur frequently.

In particular, a memory device requiring high speed of operation employs an impedance matching circuit called on die termination in the vicinity of a pad in an integrated circuit chip to solve the above problems. Typically, in an on die termination scheme, source termination by an output circuit is performed on the transmitting side, and parallel termination is performed by a termination circuit connected in parallel to the receiving circuit connected to the input pad on the receiving side.

ZQ calibration refers to the process of generating an impedance code that changes as the PVT (Process, Voltage, Temperature) process changes. The impedance code generated as a result of ZQ calibration To adjust the termination impedance value. In general, a pad to which an external resistor, which is a reference for calibration, is connected is called a ZQ pad (ZQ PAD). For this reason, the term ZQ calibration is mainly used. On the other hand, the configuration of the ZQ calibration circuit is well known to those skilled in the art as described in Korean Publication No. 10-2010-0006887, detailed description thereof will be omitted.

When a ZQ calibration operation is started in response to a ZQ calibration command, no signal (address, command, etc. in the case of a memory device) is allowed to be input from the outside during the ZQ calibration operation. This is because power noise may occur when a signal is input from the outside while the clock and the buffer are activated during the ZQ calibration operation, and such power noise may cause a calibration error. Therefore, in order to minimize the calibration error, the signal input from the outside should be restricted by deactivating the clock, the buffer, etc. during the ZQ calibration operation. An object of the present invention is to provide an integrated circuit capable of preventing a signal from being input from the outside by deactivating a clock, a buffer, and the like during a ZQ calibration operation.

An integrated circuit according to the present invention includes a calibration unit for generating an impedance code for adjusting a termination impedance value; A control signal input unit which receives at least one control signal from an external source and is inactivated in an operation section of the calibration unit; And a calibration controller configured to decode the at least one control signal transmitted from the control signal input unit to activate / deactivate the operation of the calibration unit.

In addition, the integrated circuit according to the present invention, the calibration unit for generating an impedance code for adjusting the termination impedance value; A calibration controller to decode at least one control signal to activate / deactivate an operation of the calibration unit; And an internal voltage generator which generates an internal voltage but is deactivated in an operation period of the calibration unit.

According to the present invention, the power supply noise can be minimized by deactivating the buffer, the clock, etc. during the ZQ calibration operation, thereby minimizing the calibration error.

1 illustrates an integrated circuit in accordance with an embodiment of the present invention.
2 is a diagram illustrating an embodiment of a control signal input unit 100 shown in FIG. 1.
3 is a diagram illustrating an embodiment of a calibration control unit 200 shown in FIG. 1.
4 is a waveform diagram of a signal representing the operation of the integrated circuit shown in FIG.
5 illustrates an integrated circuit in accordance with another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

1 illustrates an integrated circuit according to an embodiment of the present invention.

The integrated circuit may include a calibration unit 300, a control signal input unit 200, a calibration control unit 200, and a clock control unit 400. 1 illustrates a case in which an integrated circuit according to the present invention is a memory device for convenience of description.

The control signal input unit 200 receives at least one or more control signals A <10> and CMD from the outside, but is deactivated in the operation section of the calibration unit 300. Here, the at least one control signal may include an address A <10> and a command CMD if the integrated circuit according to the present invention is a memory device. The command CMD may include / CS, / WE, / RAS, and / CAS signals. In addition, the meaning that the control signal input unit 200 is inactivated includes a meaning that an operation of receiving signals A <10> and CMD from the outside is not performed. The control signal input unit 200 may be designed to be inactivated during the activation period of the calibration activation signal CALEN. Here, the calibration activation signal CALEN is a signal for controlling the operation of the calibration unit 300, and the calibration unit 300 is calibrated during the activation period of the calibration activation signal CALEN. Perform the action. 1 illustrates a case in which the control signal input unit 200 receives some address bits A <10> and a command CMD from an external address. The control signal input unit 200 may include a buffer unit 110 and a latch unit 120, which will be described in detail with reference to FIG. 2.

The calibration controller 200 decodes the address A <10> and the command CMD transmitted from the control signal input unit 100 to activate / deactivate the operation of the calibration unit 300. In detail, the calibration control unit 200 may be designed to decode the address A <10> and the command CMD to activate the calibration activation signal CALEN. If the combination of the decoded command CMD, i.e., / CS, / WE, / RAS, and / CAS signals corresponds to the ZQ calibration command, activate the calibration enable signal CALEN, address A <10>. The activation width of the calibration activation signal CALEN is determined according to the logic level of the. In detail, the calibration controller 200 may include a decoder 210 and an activation signal generator 220, which will be described in detail with reference to FIG. 3.

The calibration unit 300 generates an impedance code CODE <1: N> for adjusting the termination impedance value. In detail, the calibration unit 300 may be designed to perform an operation of generating an impedance code CODE <1: N> during an activation period of the calibration activation signal CALEN. On the other hand, since the configuration and operation principle of the calibration unit 300 is similar to the prior art, a detailed description thereof will be omitted.

The clock control unit 400 receives the clock CK and outputs the control clock CK_CTR of the first level in the operation section of the calibration unit 300, and in other sections, the clock CK remains as it is. Output is performed by the control clock (CK_CTR). Here, the clock CK may be an external clock input from an external source or an internal clock obtained by delaying the external clock by a delay locked loop (DLL) circuit. In detail, the clock controller 400 outputs the low level control clock CK_CTR to the control signal input unit 100 during the activation period of the calibration activation signal CALEN. The control clock CK_CTR having the same level may be designed to be output to the control signal input unit 100. Meanwhile, since the clock controller 400 is not an essential component of the present invention, the integrated circuit according to the present invention may be designed without the clock controller 400, and in this case, the control signal input unit 100 may be replaced with the control clock CK_CTR. The clock CK can be input as it is.

FIG. 2 is a diagram illustrating an embodiment of the control signal input unit 100 shown in FIG. 1.

The control signal input unit 100 may include a buffer unit 110 and a latch unit 120.

The buffer unit 110 buffers the address A <10> and the command CMD that are input from the outside and outputs the buffers to the latch unit 120, but is deactivated in the operation period of the calibration unit 300. In detail, the buffer unit 110 may be designed not to receive the address A <10> and the command CMD from the outside in the activation period of the calibration activation signal CALEN.

The latch unit 120 latches the address A <10> and the command CMD output from the buffer unit 110 in synchronization with the control clock CK_CLK. The latch unit 120 may be configured as a flip-flop (FLIP-FLOP). The control clock CK_CLK is a signal output from the above-described clock control unit 400, and since the control clock CK_CLK is constantly maintained at a low level in the operation period of the calibration unit 300, the latch unit 120 eventually becomes a calibration unit ( In the operation section 300, the latch operation described above is not performed. That is, the latch unit 120 is deactivated in the operation section of the calibration unit 300.

FIG. 3 is a diagram illustrating an embodiment of the calibration controller 200 shown in FIG. 1.

The calibration controller 200 may include a decoder 210 and an activation signal generator 220.

ZQ calibration control mode is the ZQINIT mode which is executed first after power-up, ZQOPER mode generated by the input from the controller during the operation of the integrated circuit, and ZQCS mode performed periodically during the operation of the integrated circuit, as shown in Table 1 below. It includes. The ZQINIT mode and ZQOPER mode are included in the ZQCL mode, and the calibration operation must be performed within at least 512 cycles in the ZQINIT mode, at least 256 cycles in the ZQOPER mode, and at least 64 cycles in the ZQCS mode.

[Table showing JEDEC SPEC related to ZQ Calibration] Symbol
DDR3 800/1066/1333/1600 Min Max Units tZQOPER 256 NA tCK tZQINIT 512 NA tCK tZQCS 64 NA tCK

The decoding unit 210 decodes the command CMD, and when the decoded command corresponds to a calibration command (a command to perform a calibration operation), the decoding unit 210 according to the logic level of the address A <10>. One of the calibration control signal ZQCL and the second calibration control signal ZQCS is activated. The first calibration control signal ZQCL is a signal that is activated in the ZQCL mode, and the second calibration control signal ZQCS is a signal that is activated in the ZQCS mode. In detail, the decoding unit 210 generates a calibration command by a combination of the / CS, / RAS, / CAS, and / WE signals constituting the input command CMD as shown in Table 2 below. 10>) is designed to activate the first calibration control signal ZQCL when the high level is high and to activate the second calibration control signal ZQCS when the address A <10> is low. Can be.

[ZQ Calibration Command Truth Table] FUNCTION CKE / CS / RAS / CAS / WE A10 ZQ Calibration Long (ZQCL) H L H H L H ZQ Calibaration Short (ZQCS) H L H H L L

The activation signal generator 220 clocks the calibration activation signal CALEN, the activation width of which is determined according to an activated signal of the first calibration control signal ZQCL and the second calibration control signal ZQCS. Activate with (CK). In detail, the activation signal generator 220 is a calibration activation signal that is activated for 256 cycles based on a preset number of cycles, for example, a clock CK, when the first calibration control signal ZQCL is activated. Create (CALEN). Similarly, when the second calibration control signal ZQCS is activated, the activation signal generator 220 generates a calibration activation signal CALEN that is activated for a preset number of cycles, for example, 64 cycles.

4 is a waveform diagram of a signal representing an operation of the integrated circuit of FIG. 1. The overall operation of the integrated circuit shown in FIG. 1 together with FIG. 4 will be described.

The clock controller 400 outputs the control clock CK_CTR having the same level as the input clock CK to the control signal input unit 100.

The buffer unit 110 of the control signal input unit 100 buffers and outputs the address A <10> and the command CMD input from the outside, and the latch unit 120 of the control signal input unit 100 controls the control clock. The address A <10> and the command CMD are latched in synchronization with (CK_CTR).

The decoding unit 210 of the calibration controller 200 decodes the address A <10> and the command CMD output from the control signal input unit 100 to decode the first calibration control signal ZQCL and the first calibration control signal. Activate any one of the 2 calibration control signals ZQCS. In FIG. 4, for convenience of description, a combination of the / CS, / RAS, / CAS, and / WE signals constituting the command CMD indicates a ZQ calibration command, and the address A <10> is at a low level. It is assumed that the second calibration control signal ZQCS is activated.

The activation signal generator 220 of the calibration controller 200 may perform a calibration activation signal that is activated for a preset number of cycles, for example, 64 cycles in response to the activated second calibration control signal ZQCS. CALEN). The generated calibration activation signal CALEN is input to the calibration unit 300, the control signal input unit 100, and the clock control unit 400.

The calibration unit 300 performs a ZQ calibration operation that generates an impedance code CODE <1: N> during the activation period of the calibration activation signal CALEN.

Meanwhile, the buffer unit 110 of the control signal input unit 100 is inactivated during the activation period of the calibration activation signal CALEN in response to the activated calibration activation signal CALEN. That is, the buffer unit 110 of the control signal input unit 100 does not perform an operation of buffering and outputting the address A <10> and the command CMD during the activation period of the calibration activation signal CALEN.

The clock controller 400 outputs the low level control clock CK_CTR to the control signal input unit 100 during the activation period of the calibration activation signal CALEN in response to the activated calibration activation signal CALEN. . Therefore, the latch unit 120 of the control signal input unit 100 does not perform a latch operation during the activation period of the calibration activation signal CALEN.

Meanwhile, although FIG. 1 illustrates a case in which both the buffer unit 110 and the latch unit 120 of the control signal input unit 100 are deactivated in the operation period of the calibration unit 300, this is only an example. In the integrated circuit according to the present invention, at least one of the buffer unit 110 and the latch unit 120 may be designed to be inactivated in an operation period of the calibration unit 300. For example, when designing only the buffer unit 110 among the buffer unit 110 and the latch unit 120 to be deactivated during the operation period of the calibration unit 300, the clock control unit 400 is omitted, and the control is omitted. The signal input unit 100 may be designed such that the clock CK is input as it is instead of the control clock CK_CTR. As another example, when only the latch unit 120 of the buffer unit 110 and the latch unit 120 is designed to be deactivated during the operation period of the calibration unit 300, the calibration is activated in the buffer unit 110. The signal CALEN may be designed not to be input.

As a result, according to the present invention, at least one of the buffer unit 110 and the latch unit 120 of the control signal input unit 100 is deactivated during the ZQ calibration operation of the calibration unit 300 to thereby deactivate the power of the integrated circuit. Minimizing consumption reduces power noise, which minimizes calibration errors.

5 is a diagram illustrating an integrated circuit according to another exemplary embodiment of the present invention.

The integrated circuit may include a calibration unit 300, a calibration controller 200, and an internal voltage generator 500. The inventive concept of the integrated circuit shown in FIG. 5 is to control the internal voltage generator 500 not to operate in the operation period of the calibration unit 300.

The configuration and operation principle of the calibration control unit 200 are similar to the calibration control unit 200 described above with reference to FIG.

Since the configuration and operation principle of the calibration unit 300 is similar to the calibration unit 300 described above with reference to FIG. 1, a detailed description thereof will be omitted.

The internal voltage generator 500 generates the internal voltage but is deactivated in the operation period of the calibration unit 300. In this case, the deactivation of the internal voltage generator 500 includes a meaning of not performing an operation of generating an internal voltage. In detail, the internal voltage generator 500 may be designed to generate an internal voltage and to be inactivated during an activation period of the calibration activation signal CALEN. Here, the calibration activation signal CALEN is the same signal as the calibration activation signal CALEN described above with reference to FIG. 1. On the other hand, the internal voltage generator 500 is a circuit for generating the internal voltage required for the operation of the chip internal circuit, a circuit well known to those skilled in the art of the present invention for the configuration of the internal voltage generator 500 Detailed description will be omitted.

Since the calibration unit 300 uses an external power source during the ZQ calibration operation, the calibration unit 300 operates normally even when the internal voltage generator 500 is deactivated during the operation of the calibration unit 300. There is no problem. On the other hand, since the internal voltage generator 500 is deactivated in the operation period of the calibration unit 300, power consumption due to the operation of the internal voltage generator 500 may be reduced, and thus calibration may be caused by power noise. The error can be minimized.

1 and 5 illustrate an example in which an integrated circuit according to the present invention is a memory device, this is only an example, and an integrated circuit using a calibration circuit and a configuration that receives signals from the outside, such as a buffer or a latch, may be used. The present invention can be applied to a circuit.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

100: control signal input unit 200: calibration control unit
300: calibration unit 400: clock control unit
500: internal voltage generator

Claims (6)

A calibration unit generating an impedance code for adjusting a termination impedance value;
A control signal input unit which receives at least one control signal from an external source and is inactivated in an operation section of the calibration unit; And
A calibration controller for decoding / activating the at least one control signal transmitted from the control signal input unit to activate / deactivate the operation of the calibration unit.
&Lt; / RTI &gt;
The method of claim 1,
The integrated circuit is a memory device,
The at least one control signal includes an address and a command.
Integrated circuit.
The method of claim 2,
The control signal input unit,
A buffer unit which buffers and outputs the address and the command, but which is deactivated in an operation period of the calibration unit;
A latch unit for latching the address and the command outputted from the buffer unit in synchronization with a control clock
&Lt; / RTI &gt;
The method of claim 3, wherein
A clock control unit which receives a clock and outputs the control clock of the first level in the operation section of the calibration unit, and outputs the input clock as the control clock in other sections.
&Lt; / RTI &gt;
5. The method of claim 4,
The calibration control unit,
Decoding to decode the command to activate a first calibration control signal if the address is deactivated and to activate a second calibration control signal if the address is deactivated when the decoded command corresponds to a calibration command. Wealth and
An activation signal generator configured to activate a calibration activation signal, the activation width of which is determined according to an activated signal of the first calibration control signal and the second calibration control signal, using the clock;
The calibration unit is operated in response to the calibration activation signal
Integrated circuit.
A calibration unit generating an impedance code for adjusting a termination impedance value;
A calibration controller to decode at least one control signal to activate / deactivate an operation of the calibration unit; And
An internal voltage generator that generates an internal voltage but is deactivated in an operation section of the calibration unit.
&Lt; / RTI &gt;
KR1020120050360A 2012-05-11 2012-05-11 Intergrated circuit KR20130126321A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160049830A (en) * 2014-10-28 2016-05-10 에스케이하이닉스 주식회사 Calibration circuit and calibration apparatus including the same
US10860258B2 (en) 2015-12-24 2020-12-08 SK Hynix Inc. Control circuit, memory device including the same, and method
US11036396B2 (en) 2016-04-19 2021-06-15 SK Hynix Inc. Media controller and data storage apparatus including the same
US11082043B2 (en) 2014-10-28 2021-08-03 SK Hynix Inc. Memory device
USRE49496E1 (en) 2015-07-30 2023-04-18 SK Hynix Inc. Semiconductor device
US11755255B2 (en) 2014-10-28 2023-09-12 SK Hynix Inc. Memory device comprising a plurality of memories sharing a resistance for impedance matching

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160049830A (en) * 2014-10-28 2016-05-10 에스케이하이닉스 주식회사 Calibration circuit and calibration apparatus including the same
US10897253B2 (en) 2014-10-28 2021-01-19 SK Hynix Inc. Calibration circuit and calibration apparatus including the same
US11082043B2 (en) 2014-10-28 2021-08-03 SK Hynix Inc. Memory device
US11755255B2 (en) 2014-10-28 2023-09-12 SK Hynix Inc. Memory device comprising a plurality of memories sharing a resistance for impedance matching
USRE49496E1 (en) 2015-07-30 2023-04-18 SK Hynix Inc. Semiconductor device
US10860258B2 (en) 2015-12-24 2020-12-08 SK Hynix Inc. Control circuit, memory device including the same, and method
US11347444B2 (en) 2015-12-24 2022-05-31 SK Hynix Inc. Memory device for controlling operations according to different access units of memory
US11036396B2 (en) 2016-04-19 2021-06-15 SK Hynix Inc. Media controller and data storage apparatus including the same

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