KR20130089266A - Memory device refresh commands on the fly - Google Patents

Abstract

On-the-fly transitions from one memory device refresh rate to another memory device refresh rate are provided. Control logic associated with the memory device detects a condition for converting the currently applied refresh rate to a different refresh rate. In response to the condition, the refresh rate is dynamically switched. Switching does not require changing the mode register. Thus, the refresh rate for the memory device can be dynamically changed on the fly.

Description

On-the-Fly Memory Device Refresh Instructions {MEMORY DEVICE REFRESH COMMANDS ON THE FLY}

<Related Case>

This application claims the benefit of priority of US Provisional Application No. 61 / 420,269, filed December 6, 2010.

<Field>

Embodiments of the present invention generally relate to changing the refresh rate of a memory device, specifically the memory device, on the fly.

<Copyright Notice / Permission>

Portions of the specification of this patent document may contain copyrighted material. The copyright owner does not object to anyone copying this patent document or this patent specification when it appears in the patent office's patent files or records, but otherwise owns all copyrights. This copyright notice applies to all data as described below and in the accompanying drawings, as well as to any software described below: Copyright © 2010, Intel Corporation, All Rights Reserved.

Memory devices are commonly used in computing devices. Dynamic random access memory (DRAM) is generally used as working memory in computing devices. Working memory is often volatile (loss of state when power to the system is lost) and provides temporary storage for data and programs (code) to be accessed and executed by the system processor (s).

There are a number of DRAM types and variations (an example of which is synchronous DRAM (SDRAM)). Since DRAM is dynamic, it requires continuous or regular refreshing of the data bits stored in the memory device. Refreshing is generally controlled by a memory controller, which periodically accesses data bits in the memory device.

Each memory cell in a DRAM is typically comprised of a single transistor and a single capacitor, and is referred to as dynamic because its data is lost and invalidated due to various leakage current paths to peripheral cells and the substrate. Thus, to keep the data in the cells valid, each memory cell is refreshed periodically. The data in the DRAM cell array is refreshed each time data is read from the cell array into the sense amplifiers and then rewritten in the cell. Unread memory is refreshed by a specific refresh operation.

The memory controller is responsible for periodically performing refresh maintenance operations on the memory cell array. Every row in the memory array needs to be refreshed before the data in the row is lost. During the self-refresh mode, the DRAM device is responsible for the performance of the refreshes.

The refresh cycle time (tRFC) of a DRAM continues to increase with DRAM density and begins to affect isochronous bandwidth and worst-case latency. Isochronous bandwidth refers to bandwidth guarantees on the memory subsystem.

The following description includes the description of the drawings with illustrations given as examples of implementations of embodiments of the invention. The drawings are to be understood as illustrative and not restrictive. As used herein, references to one or more "embodiments" are to be understood to describe particular features, structures, or features included in at least one implementation of the present invention. Thus, the expressions "in one embodiment" or "in an alternative embodiment" described herein describe various embodiments and implementations of the present invention, and all do not necessarily refer to the same embodiment. However, they are also not necessarily mutually exclusive.
1 is a block diagram of one embodiment of a system having a memory device having a dynamic change in refresh rate based on controls from a memory controller.
2 is a timing diagram of one embodiment of a system with on-the-fly refresh rate switching.
3 is a block diagram of one embodiment of a system having a memory device with on-the-fly refresh rate control.
4 is a flow diagram of one embodiment of a process for dynamically switching refresh rates for memory devices and issuing catch-up refresh instructions.
5 is a flow diagram of one embodiment of a process for switching refresh rates using bank group address bits.
Description of certain details and implementations, including a description of drawings that may show some or all of the embodiments described below, as well as a description of other potential embodiments or implementations of the inventive concepts provided herein. This leads to. An overview of embodiments of the present invention is provided below, followed by a more detailed description with reference to the drawings.

On-the-fly transitions from one memory device refresh rate to another memory device refresh rate are provided. Different refresh rates may have different associated refresh cycle times tRFC. Thus, on-the-fly switching allows the system to dynamically adjust the refresh cycle time according to the use of the device and the needs of refreshing the memory elements. In addition, the on-the-fly transitions allow shorter alternatives to the system to increase the standard tRFC of memory devices with increasing density. Dynamic adjustment of the refresh rate allows the system to make performance decisions that reduce the impact on isochronous bandwidth and worst-case latency.

Control logic associated with the memory device detects a condition for switching from the currently applied refresh rate to another refresh rate. In response to the condition, the refresh rate is dynamically switched. Switching does not require changing the mode register. In one embodiment, each of the selected refresh rates is a separate refresh mode in the mode register. The mode register may have certain modes that enable dynamic switching between different rates (and therefore can also be regarded as on-the-fly switching between different modes but without modification of the mode register). Thus, the refresh rate for the memory device can be dynamically changed on the fly.

Typically the implementation of a memory subsystem includes memory resources that store data, and an associated memory controller that controls access to the memory resources. The memory controller can also manage the refresh of memory resources. In one embodiment, the memory device is DRAM compatible with dual data rate (DDR) standards. Reference is now made to DRAM as an example, which should be understood as any memory device in accordance with any embodiment described herein that supports switching between different refresh rates.

Certain memory implementations, such as those supporting DDR version 4 (DDR4), may perform memory refresh at different speeds or rates, such as 1x, 2x, and 4x. Such various memory refresh rates can be selected using the mode register. Although various refresh rates may be selectable, the selection is typically intended for initialization of the system and is expected to be constant throughout the operation of the memory device. Therefore, the refresh rate set by the refresh mode is traditionally considered to be fixed or constant. As described herein, memory refresh rates may be dynamically selected or may be selected “on the fly”.

For simplicity of explanation and clarity of terminology, reference is made herein to transitions between different refresh 'rates' rather than between different refresh 'modes'. It can be said that the transition is made between different refresh modes, but the use of a refresh 'mode' may imply a transition of refresh rate through the mode register. Rather, as described herein, on-the-fly rate switching can be accomplished without changing the mode register settings. Thus, switching of the refresh 'rate' will be referred to to clarify that mode register settings do not need to be changed to switch rates. It will be understood that different terminology may be used to describe the dynamic transition between different refresh rates. Thus, to the extent that refresh mode switching can be used to account for switching refresh rates without changing the mode register setting, such term may be equivalent to that described herein.

As referred to herein, “on the fly” selection refers to dynamic selection during active operation of the memory device. Thus, the device does not need to be in a suspended or inactive state to change the refresh rate of the device. In addition, the mode register for the memory controller does not need to be changed during system runtime to switch between different refresh rates. As used herein, "refresh rate" refers to a specific convention to be used to refresh a memory device. Different rates refer to protocols with different refresh protocols, specifically different average times between refreshes, and / or different durations of implementing a refresh command as described in more detail below. Again, according to the above description, "refresh mode" can be defined similarly, but generally refers to the mode as set by the corresponding memory mode register.

Reference is made herein to various refresh timing parameters including tREF, tREFI and tRFC. These parameters can be briefly described as follows.

tREF = refresh cycle or refresh interval. To ensure data integrity in rows of DRAM (e.g., 64K rows), a refresh command (e.g., 64K refresh instructions) is executed for each row for all memory banks within the tREF period. As of the date of draft specification, a typical value for devices is about 64 milliseconds.

tREFI = average time between refresh commands. The implementation of tREFI may change (as described herein), but mainstream DRAMs tend to have a standard tREFI of about 7.8 microseconds. Traditionally, tREFI can be calculated as tREF divided by the number of rows to ensure that all rows are refreshed within the refresh period. However, as DRAM density increases, more recent implementations include refreshing multiple rows per refresh command to achieve a desired tREFI average time between refresh commands.

tRFC = Time to refresh when the refresh command is issued. This is also the time interval between the REF (refresh) and REF instructions for different rows in the same bank, typically on the order of 100 or 200 nanoseconds. TRFC is less than tRC (time to read an instruction) as the column access gates are not turned on. At the end of tRFC, a REF or ACT (activate) command may be provided to the bank just refreshed. As DRAM density increases (from 256Mbit to 512Mbit to 1Gbit ...) over time, memory tends to have more rows, which will also increase refresh overhead, including tRFC.

In one embodiment, the refresh interval tREFI is associated with the corresponding refresh cycle time tRFC. Thus, the refresh rate may be related to the refresh cycle time. Shorter tREFIs (ie, more frequent refreshes) are associated with shorter tRFCs. However, the 2x value for tREFI does not necessarily reduce tRFC by half due to the fixed overhead of staggering associated with tRFC. If a shorter tREFI is used, the total time spent on refreshing is longer and also affects the instruction bandwidth. Command bandwidth refers to the bandwidth for control channels for managing memory access.

As described herein, the memory may issue refresh on the fly. The memory controller has an option to specify the refresh type as part of the instruction encoding. Thus, the memory controller may implement, for example, a 2x or 4x value for tREFI when there is more traffic for memory access or access is made by an entity with higher sensitivity for memory access bandwidth, and the traffic is more The tREFI value can be reduced when less or when latency is considered to be insignificant.

Control of the dynamic switching of refresh rates is based on some kind of trigger. In one embodiment, the trigger is based on timing, such as switching according to a schedule, or disabling the use of the accelerated refresh rate for more than a predetermined period or more than the number of instructions. In one embodiment, the trigger may trigger a large amount of access traffic (which may be answered at an accelerated refresh rate to reduce the overhead of refreshing during many accesses) or a later refresh rate to ensure that the minimum refresh is met. Less based on traffic at the memory device, such as access traffic. Thus, lower and / or higher traffic thresholds can be set to trigger the refresh rate transition. The threshold may be the depth of the request buffer, the number of requests per time period, or the period of delay expected (eg, how long the command can be in the buffer) between the issuance of the command and its completion.

In one embodiment, the memory controller may issue a series of refresh instructions to perform a refresh clean-up or catch up. For example, as described above, acceleration refresh is not expected to be able to refresh all memory resources of a memory device in the same number of cycles as can be achieved at a non-acceleration refresh rate. Thus, using an acceleration or fast refresh rate instead of a standard or default rate means that certain memory elements may be approaching a critical time for updating to avoid data loss. The series of refresh instructions can cause the memory device to be updated. It can be understood that the series of instructions is a series of instructions for refresh without an access request.

In one embodiment, the series of “catch up” instructions are always refresh instructions according to the slowest possible refresh cycle time (eg, 1 × refresh rate). Use of a default or standard refresh rate allows more refreshing per instruction to be achieved. Thus, refresh catchup may be achieved at an acceleration rate, but may have more overhead because more instructions are required. For example, issuance of instructions at 1x refresh rate has less instruction overhead compared to 2x or 4x because only one instruction is needed, not two or four, respectively. Switching between refresh modes allows the same task to be accomplished in the system more efficiently.

1 is a block diagram of one embodiment of a system having a memory device having a dynamic change in refresh rate based on controls from a memory controller. System 100 represents any of a variety of computing devices that may include a memory device with dynamic refresh rate switching. Such computing devices may include servers, desktops, laptops, mobile devices, smartphones, gaming devices, and the like. System 100 includes a memory 120, which is a memory device according to any embodiment described herein, and one or more memory resources 124 that represent resources in which data is stored for memory 120. ).

Memory controller 110 includes standard logic (hardware and / or software) for controlling access to memory 120 as understood in the art. Memory controller 110 is associated with memory 120 because it controls access to memory 120. In one embodiment, memory controller 110 includes functions (eg, features implemented by the logic of memory controller 110) access manager 112, trigger detector 114, refresh rate selection 116, and the like. Resource selection 118. The illustrated functions are not intended to represent all the functions of the memory controller 110. Memory controller 110 may be implemented with more or fewer functional components than shown.

The access manager 112 allows the memory controller 110 to determine how much access traffic exists for the memory 120. Thus, access manager 112 enables the memory controller to monitor, track, and possibly store information related to the number of accesses to different memory devices in system 100. The access manager 112 can identify traffic to the memory 120.

The trigger detector 114 allows the memory controller 110 to determine the conditions under which the refresh rate should be switched. As mentioned above, the trigger may be based on timing or traffic. The traffic threshold may indicate when the refresh rate can or should be switched. The trigger detector 114 can operate in conjunction with the access manager 112. For example, memory controller 110 may know via access manager 112 what access traffic exists for memory 120, and then whether the amount of such traffic indicates conditions for a change in refresh rate. This can be determined via the trigger detector 114.

The refresh rate selection 116 allows the memory controller 110 to implement and appropriately apply a variety of different refresh rates. In one embodiment, memory controller 110 may include logic to implement a number of different refresh rates associated with different refresh modes. Different refresh rates will send when instructions are sent, how many nops will be issued between instructions, how long memory resources will be occupied for instruction execution, how many instructions can be issued or issued for a particular rate. Should be, or have companion agreements such as other agreements.

In one embodiment, different refresh rates are used to apply to different memory resources 124. Thus, resource selection 118 allows memory controller 110 to appropriately apply the selected refresh rate to specific memory resources. In one embodiment, the application of different rates to different resources is managed using a data structure or table or other such mechanism. As an alternative, different registers may be applied to different resources to manage different refresh rates of different resources.

Clock 102 represents a clock signal to apply to memory 120 and memory controller 110 for memory access commands. Clock 102 may be a main system clock (eg, a clock used to control the processor), a peripheral clock, or some modified (eg, reduced) version of any such clock. It is also possible to implement the clock device especially for memory access. Command issuance and state changes of memory 120 are typically made with reference to clock 102. The refresh rate is made in particular with respect to clock 102, and the acceleration refresh cycle will end in fewer clock cycles than the standard refresh cycle.

Memory 120 includes an operation pipeline 122 that represents a pipeline of instructions from memory controller 110. Access instructions and refresh instructions may be placed in the operation pipeline 122 for execution by the memory 120. In one embodiment, the refresh catchup operation includes a filling operation pipeline 122 with refresh instructions. By filling the pipeline with refresh instructions, the memory controller 110 can effectively prevent other memory access operations or refresh rate transitions until the catchup ends. Instead, the memory controller 110 can actively prevent access operations or refresh rate switching by only disallowing such instructions until the refresh catchup ends.

2 is a timing diagram of one embodiment of a system with on-the-fly refresh mode switching. Timing diagram 200 illustrates one example implementation. Timing diagram 200 illustrates the relative timing for a memory device using variable refresh rates. The memory device receives refresh commands via the command line from the associated memory controller. In one embodiment, the memory device is DRAM compatible with DDR (dual data rate) standards such as DDR4. The associated memory controller or corresponding memory controller for the memory device is a memory controller that controls access to the memory device.

Timing diagram 200 includes an illustration of clock signal 210 and command signal 220. In command signals, the commands may be mixed with "Don't Care" signals, which is the time since no trigger was provided to direct the command (e.g., to set the enable line). It does not matter what the state of the signal lines during.

According to the timing diagram 200, when the memory controller uses a 1x REF command (REF1 in the command signal 220), the refresh cycle time of tRFC1 is used with the refresh interval of tREFI1. When the memory controller uses a 2x REF command (REF2 in command signal 220), the refresh cycle time of tRFC2 is used with the refresh interval of tREFI2. In time breaks, timing diagram 200 does not provide an accurate illustration of the comparison between tREFI1 and tREFI2, but tREFI2 is about half shorter than tREFI1.

In one embodiment, the memory controller issues a second 2x REF instruction (second REF2 after completion of tREFI2) immediately after the first 2x REF instruction. There are different possible options for controlling how often the memory controller can switch between standard (eg 1x) and acceleration (eg 2x or 4x) refresh rates. The timing diagram shows the option constrained to issue two instructions or multiples of two instructions before the memory controller switches back to the 1x rate when using the 2x rate. In general, there may be constraints to issue N instructions or multiples of N instructions before switching from Nx rate to another rate, where N is an integer (i.e. 1 instruction for 1x rate, 2x rate). Two instructions, four at 4x rate, etc.).

A more flexible option is for the memory controller to switch as needed. For example, the memory controller may issue a command with a 1x rate after issuing a single command with a 2x refresh rate. In such an implementation, the memory controller will need to ensure that all refreshes are issued in tREF to refresh all necessary memory elements. If there are no restrictions (such as issuing N instructions or a multiple of N instructions before switching) with respect to changes in refresh rates, the memory device design may also increase in complexity. For example, a memory device may require row address counters with more bits and additional control logic.

Thus, there may be a compromise of the memory controller's flexibility to switch between logic to refresh rates in the memory controller (eg, to monitor and guarantee the issuance of all refreshes). Most examples herein refer to two refresh rates, but the logic will need to be more sophisticated for implementations in which more (eg three) different refresh rates may be used. In one embodiment, the memory controller includes a functional element for calculating and monitoring refresh requests for performing refreshing using instructions having various refresh rates.

In one embodiment, the memory controller uses a 2x or 4x refresh rate when there are many requests in the pipeline. If the refreshes reach a critical threshold, the memory controller can switch to the 1x rate and issue a series of refreshes for the catchup. In one embodiment, DRAM specifications allow for queuing of up to nine refreshes.

3 is a block diagram of one embodiment of a system having a memory device with on-the-fly refresh mode control. Any of any of a variety of computing devices can include a memory device with on-the-fly dynamic refresh rate switching as described herein. System 300 represents any of a number of computing devices that may include dynamic switching of refresh rates. Such computing devices may include servers, desktops, laptops, mobile devices, smartphones, gaming devices, and other devices with memory that require periodic refreshing.

System 300 includes a memory 310, which is a memory device in accordance with any embodiment described herein, and includes one or more memory resources 312-314. Memory resources 312-314 represent resources in which data is stored for memory 310. In one embodiment, the memory resources are separate memory channels, memory banks, memory groups, or other similar separation. The logic required to implement any separation other than the separation of memory channels can prevent any separation greater than the separate channels in many practical implementations.

Memory 310 further includes refresh control 320 representing hardware and / or software logic within memory 310 for implementing refresh operations in response to instructions from memory controller 330. In one embodiment, refresh control 320 includes a pipeline of instructions received from a memory controller. In one embodiment, memory 310 receives and executes only a single command before responding back to memory controller 330, so in this implementation a pipeline of instructions may be implemented in memory controller 330.

Memory controller 330 includes standard logic (hardware and / or software) for controlling access to memory 310 as understood in the art. In addition, the memory controller 330 includes logic for reading and corresponding to refresh rate change triggers generated in the system 300 as described above. Thus, the memory controller includes logic to dynamically switch between different refresh modes of different refresh rates. The memory controller 330 is associated with the memory 310 because it controls the access of the memory 310. Memory controller 330 is shown connected to memory 310 through channel 352, which may be a single line channel or multiple line channels (eg, a bus) or a combination thereof.

In one embodiment, memory controller 330 accesses refresh policy 332 associated with memory 310. In one embodiment, memory controller 330 has a number of different policies depending on the number of memory banks in system 300. Experiments have shown that on-the-fly bursts perform better with a single memory bank full. With multiple banks, memory controller 330 has more opportunities to refresh banks that are not being accessed.

In one embodiment, the DRAM may have the option to refresh by bank group or to refresh all bank groups. In such an implementation, the memory controller 330 may issue a refresh command on-the-fly to select between refresh by bank group and all refresh. The techniques described for switching between standard and accelerated refresh rates also apply to this implementation.

Processor 340 represents the processing resources of system 300. While shown in the singular, it will be understood that the processor 340 may include one or more processor devices, such as or including multiple core devices. Processor 340 accesses memory 310 via bus 354 to perform read and write operations. In one embodiment, the bus 354 may be physically routed through the memory controller 330, but certain functions (refresh) in which access from the processor 340 to the memory 310 exist within the memory controller 330. Are logically separated to indicate the fact that they may not include rate changes, etc.).

4 is a flowchart of one embodiment of a process for dynamically switching refresh modes for memory devices and issuing catchup refresh instructions. Flowcharts as illustrated herein provide examples of sequences of various process actions. Although shown in a particular sequence or order, unless otherwise specified, the order of the actions may be changed. Thus, the implementations shown are to be understood as examples only, and the processes may be performed in a different order, and some actions may be performed in parallel. In addition, one or more actions may be omitted in various embodiments of the present invention, so not all actions are necessary for every implementation. Other process flows are possible.

The memory controller or memory resource control logic detects 402 a refresh rate change trigger. For example, the controller can detect traffic above the threshold, which triggers the controller to use faster refreshes, or detect a lower traffic threshold that allows the controller to use a slower refresh rate. In one embodiment, the data request type (eg, the type of data requested) may trigger a refresh rate change. For example, a request for data of a type with guaranteed bandwidth can trigger the use of a higher refresh rate.

In one embodiment, different refresh rates are applied to different memory resources. The controller can select 404 a memory resource to apply the refresh rate change to. In another embodiment, the refresh rates are equally applied to all memory resources, for example based on the memory structure or configuration, thus eliminating the need for resource selection. The controller switches 406 the refresh rate for the selected memory resource. Subsequently, refresh instructions are issued for the selected memory resource until another refresh rate is selected.

In one embodiment, the system monitors 412 the refresh traffic to determine whether all refreshes will be completed within the time required to ensure the validity of the data stored in the memory resources. Typically the controller monitors the refresh traffic. If the timing threshold for completing all refreshes has not been reached (414), the system continues to monitor (412) the refresh traffic.

When the timing threshold for completing refreshes is reached (414), the controller issues (416) a series of refresh instructions for the catchup. The controller issues commands within the time needed to ensure the validity of the data, but can issue commands without much spare time. Thus, a series of instructions may need to temporarily occupy memory resources along with the refresh operations. It may affect memory access performance, but it is necessary to guarantee data validity. The controller can prevent the refresh rate change during the refresh catchup (418). As mentioned above, prevention of the refresh rate change can be achieved directly by not issuing an instruction, and / or can be performed more manually by loading the instructions into the memory pipeline.

5 is a flow diagram of one embodiment of a process for switching refresh modes using bank group address bits. In one embodiment, a mode register is used 502 to set and determine what refresh rates are supported for memory resources. The mode register can be set by the system BIOS (basic input / output system, typically for system initialization) or by the controller. Some of the modes may be fixed modes, which require a setting in the mode register to be changed to change the refresh rate (e.g., to obtain a corresponding different refresh rate no matter which refresh mode is selected). Must be changed to another refresh mode in the register).

If the on-the-fly refresh rate change is not supported by the refresh mode (504), the controller follows the fixed rate refresh mode (506) and cannot dynamically issue refresh rate changes during operation of the memory device. If an on-the-fly refresh rate change is supported by the refresh mode (504), the controller follows the default / acceleration rate convention (508). The default refresh rate is the rate which is the standard rate for memory resources. As described herein, such a rate may be referred to as 1x. The acceleration rate or rates are factors of the standard rate and may be different for different implementations.

In one embodiment, the controller determines 510 whether to apply the default or acceleration rate. This determination may be made based on a policy for a particular memory resource (eg, based on traffic and / or validity assurance). In one embodiment, the controller sets one or more bank group address bits to identify the selected refresh rate (512). The controller sets tRFC and tREFI according to the selected refresh rate (514).

In one embodiment, the refresh described herein is applied in a DDR4 implementation. The table below provides an example of the mode register settings defined for DDR4.

On-the-fly mode can be enabled through the available options in the corresponding mode register. Control bits in the register can be used to control the refresh mode of the associated memory resource. Control bit Ax may instruct the system to use the on-the-fly mode instead of the fixed refresh mode. In addition, one or more of the other control bits may be used to determine which values of tREFI are available. It will be appreciated that more bits may be used to enable more refresh modes than shown. In one embodiment, the number of modes may be limited to reduce the complexity of memory checking and verification. As an example, the table above shows on-the-fly options for switching between 1x and 2x and other options for switching between 1x and 4x. In other implementations, other options may also be used (such as switching between any of 1x, 2x, and 4x). For example, any combination of different refresh cycle times of 1x, 2x, and 4x may be issued, where 1x is standard time, 2x is standard time divided by 2, and 4x is standard time divided by 4. It's time. Thus, the example of the table is not limited.

Normal mode (fixed 1x) is a legacy mode (eg, average refresh interval of 7.8 microseconds). Fixed 2x and 4x rates may also be supported. In the 2x refresh mode, refreshes are issued twice as fast as the average refresh interval (eg, at 3.9 microseconds (7.8 usec / 2)). In one embodiment, in 2x refresh mode, the DRAM will internally refresh only half of the number of rows that it has refreshed in 1x refresh mode. In the 4x refresh mode, refreshes are issued four times faster than the average refresh interval (eg, at 1.95 microseconds (7.8 usec / 4)). The implementation of a 1x, 2x or 4x fixed refresh mode is controlled by bits Ay and Az, which represent two bits in a mode register (eg, a register stored in DRAM and / or in a memory controller).

The switching is controlled by the memory controller and can be changed based on the traffic observed by the controller, for example. In one embodiment, the refresh command is a specific command encoding issued by the memory controller. An example of an instruction table for issuing refresh instructions is as follows.

As shown, in one embodiment, a specific pin (BG0 or bank group 0) may be used to specify the type of encoding (e.g., using 1x for BG0 = 0 and for BG0 = 1). Use 2x or 4x depending on the chosen implementation). When the refresh "on the fly 1x / 2x" option is selected using the mode register, the bank group address bit BG0 is used to distinguish between 1x and 2x instructions. Thus, a reference to the mode register may indicate which refresh modes are available, and other control bits may indicate which refresh rate (or which dynamic refresh mode) is selected.

In one embodiment, when BG0 = L, the DRAM executes the refresh using 1x tRFC, and when BG0 = H, the DRAM performs the refresh using the corresponding tRFC value associated with 2x refresh. If the refresh " on the fly 1x / 4x " option is selected instead, BG0 = H can cause the DRAM to perform a refresh using the corresponding tRFC value associated with the 4x refresh. Alternates between high (H) and low (L) logic levels can also be made.

Various operations or functions are described herein, which can be described or defined as software code, instructions, configuration and / or data. The content may be a direct executable file ("object" or "executable" form), source code or difference code ("delta" or "patch" code). The software content of the embodiments described herein may be provided through a product that stores the content, or through a method of operating a communication interface to transmit data via the communication interface. A machine readable medium or computer readable medium may cause a machine to perform the functions or operations described, for example, a writable / non-writable storage medium (eg, read only memory (ROM), random access memory). (RAM), magnetic disk storage media, optical storage media, flash memory devices or other storage media) or through a transmission medium (e.g., optical, digital, electrical, acoustic signals or other radio signals) Any mechanism for providing (ie, storing and / or transmitting) information in a form that can be accessed by a computing device, electronic system or other device. The communication interface includes any mechanism that interfaces with any of wired, wireless, optical or other media to communicate with other devices such as memory bus interfaces, processor bus interfaces, internet connections, disk controllers. The communication interface may be configured by providing configuration parameters and / or transmitting signals to prepare the communication interface to provide a data signal describing the software content.

The various components described herein can be means for performing the operations or functions described. Each component described herein includes software, hardware or a combination thereof. The components may be implemented as software modules, hardware modules, special purpose hardware (eg, custom hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs, etc.), embedded controllers, wired circuits, and the like.

In addition to those described herein, various changes may be made thereto without departing from the scope of the disclosed embodiments and implementations. Accordingly, the examples and examples in this specification should be construed as illustrative rather than limiting. The scope of the invention should be determined with reference only to the following claims.

Claims (21)

Detecting a refresh rate trigger; And
In response to detecting the refresh rate trigger, dynamically switching from one refresh rate to another during the active operation of the memory device in a memory device.
Lt; / RTI &gt;
Each refresh rate indicates a rate for refreshing dynamic storage elements of the memory device,
Wherein said one refresh rate and said other refresh rate are different. The method of claim 1, wherein detecting the trigger comprises:
Detecting a threshold amount of traffic for the memory device. The method of claim 1, wherein each refresh rate comprises a different refresh cycle time or approximate period between refresh instructions. The method of claim 1, wherein the different refresh rates include 1x rate, 2x rate, and 4x rate, 1x rate has standard cycle time, 2x rate has cycle time divided by 2, and 4x rate Wherein the standard cycle time is divided by four. 2. The method of claim 1, wherein dynamically switching further comprises setting an active refresh rate for the memory device using command bits independent of a mode register. The method of claim 1,
Issuing a series of refresh instructions to perform a refresh catch-up for the memory device. 7. The method of claim 6, wherein issuing the series of refresh instructions
Issuing a series of refresh instructions with the slowest available cycle time. Memory resources for storing data; And
Memory resource control logic coupled to the memory resources
Wherein the control logic is
Detect the refresh rate trigger,
In response to detecting the refresh rate trigger, dynamically switches from one refresh rate to another during an active operation of the memory resources,
Wherein each refresh rate indicates a rate for refreshing dynamic storage elements of a memory device, wherein the one refresh rate and the other refresh rate are different. 9. The apparatus of claim 8, wherein the memory resource control logic detects a threshold amount of traffic for the memory device, and wherein the threshold amount acts as a refresh rate trigger. 9. The apparatus of claim 8, wherein each refresh rate comprises a different refresh cycle time or approximate period between refresh instructions. The method of claim 8, wherein the different refresh rates include 1x rate, 2x rate, and 4x rate, 1x rate has a standard cycle time, 2x rate has a cycle time divided by the standard cycle time by 2, and 4x rate Is a cycle time divided by four. 9. The method of claim 8, wherein the memory resource control logic is
And dynamically converts refresh rates by setting an active refresh rate for the memory device using command bits independent of a mode register. 9. The apparatus of claim 8, wherein the memory resource control logic also issues a series of refresh instructions to perform a refresh catchup for the memory device. 14. The apparatus of claim 13, wherein the memory resource control logic issues a series of refresh instructions with the slowest available cycle time. Memory device-the memory device
Memory resources for storing data; And
Memory resource control logic coupled to the memory resources
Wherein the control logic detects a refresh rate trigger and, in response to detecting the refresh rate trigger, dynamically switches from one refresh rate to another during an active operation of the memory resources, each refresh rate being: Indicate a rate for refreshing dynamic storage elements of the memory device, wherein the one refresh rate and the other refresh rate are different, and wherein the refresh rate trigger is associated with access request traffic to the memory resources; And
A multi-core processor coupled to the memory device to generate memory access requests for data stored in the memory device
/ RTI &gt; 16. The system of claim 15, wherein the memory resource control logic detects a threshold amount of traffic for the memory device, and the threshold amount acts as a refresh rate trigger. 16. The system of claim 15, wherein each refresh rate comprises a different refresh cycle time or approximate period between refresh instructions. The method of claim 15, wherein the different refresh rates include 1x rate, 2x rate, and 4x rate, 1x rate has a standard cycle time, 2x rate has a cycle time divided by the standard cycle time by 2, and 4x rate Is a cycle time divided by four. 16. The system of claim 15, wherein the memory resource control logic is
A system for dynamically switching refresh rates by setting an active refresh rate for the memory device using command bits independent of a mode register. 16. The system of claim 15, wherein the memory resource control logic also issues a series of refresh instructions to perform a refresh catchup for the memory device. 21. The system of claim 20, wherein the memory resource control logic issues a series of refresh instructions with the slowest available cycle time.

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