KR20130085118A

KR20130085118A - Semiconductor device with otp memory cell

Info

Publication number: KR20130085118A
Application number: KR1020120006032A
Authority: KR
Inventors: 김태훈; 김성묵
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2012-01-19
Filing date: 2012-01-19
Publication date: 2013-07-29

Abstract

PURPOSE: A semiconductor device which includes an OTP memory cell is provided to be unnecessary for additional buffer memory, thereby increasing the operation efficiency in a system. CONSTITUTION: A first MOS transistor (M1) receives a bias enable signal from a first gate and receives a first bias voltage to one side. A second MOS transistor (M2) receives a first gate signal from a second gate and one side is connected to the other side of the first MOS transistor. A third MOS transistor (M3) receives the second gate signal from a third gate and one side is connected to the other side of the second MOS transistor.

Description

Semiconductor device including OTP memory cell {SEMICONDUCTOR DEVICE WITH OTP MEMORY CELL}

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a one-time programmable memory cell.

A semiconductor memory device is a memory device that stores data and can be read out when needed. Semiconductor memory devices can be roughly divided into random access memory (RAM) and read only memory (ROM). ROM is nonvolatile memory that does not lose its stored data even when its power supply is interrupted. The ROM includes PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically EPROM), and Flash Memory Device. RAM is a so-called volatile memory that loses its stored data when the power is turned off. RAM includes Dynamic RAM (DRAM) and Static RAM (SRAM). In addition, semiconductor memory devices that replace DRAM capacitors with nonvolatile materials are emerging. Ferroelectric RAM (FRAM) using a ferroelectric capacitor, magnetic RAM (MRAM) using a tunneling magneto-resistive (TMR) film.

A memory block having an OTP memory cell capable of one programming mode stores trimming information, security ID, chip ID, calibration data, etc. of an integrated circuit, or redundancy of main memory. ) It is used as a memory for storing information. As systems using integrated circuits become increasingly sophisticated, complicated to operate, and require high-capacity memory devices, the operation speed of the OTP memory cell blocks to be disposed is increasingly required.

The present invention provides a memory device having an OTP memory cell capable of high-speed data access.

The present invention provides a cell array comprising at least one OTP memory cell; A reference signal providing unit providing a reference signal; And a data output unit including a comparison circuit by comparing the data line signal provided to the cell array with the reference signal, wherein the OPT memory cell receives a bias enable signal as a first gate and a first bias to one side. A first MOS transistor receiving a voltage; A second MOS transistor receiving a first gate signal through a second gate and having one side connected to the other side of the first MOS transistor; And an OTP memory cell receiving a second gate signal through a third gate and having a third MOS transistor connected at one side thereof to the other side of the second MOS transistor.

According to the present invention, an OTP memory cell capable of high-speed data access can be easily implemented.

1 is a circuit diagram showing an OTP memory cell shown for explaining the present invention.
FIG. 2 is a circuit diagram showing after programming of the OTP memory cell shown in FIG.
3 is a block diagram illustrating a semiconductor memory device having an OTP memory cell according to an embodiment of the present invention.
4 is a circuit diagram illustrating an OTP memory cell according to an embodiment of the present invention.
Fig. 5 is a circuit diagram showing after programming of the OTP memory cell shown in Fig. 4;
FIG. 6 is a circuit diagram illustrating a comparator included in the reference signal providing unit of FIG. 3. FIG.
FIG. 7 is a waveform diagram showing a driving voltage provided in the programming mode of the OTP memory cell shown in FIG.
FIG. 8 is a waveform diagram showing a driving voltage provided in the read mode of the OTP memory cell shown in FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

The present invention relates to an OTP memory cell, wherein the OTP memory cell can electrically program data only once, and once programmed data is preserved even without power.

1 is a circuit diagram showing an OTP memory cell shown for explaining the present invention.

As shown in FIG. 1, an OTP memory cell includes a first MOS transistor M0 and a second MOS transistor M1. The gate terminal of the first MOS transistor M0 is connected to the first word line WP, and the gate terminal of the second MOS transistor M1 is connected to the second word line WR. One side of the first MOS transistor M0 is in a floating state, and the other side thereof is connected to the resistor node A. One side of the second MOS transistor M1 is also connected to the resistance node A. FIG. The other side of the second MOS transistor M2 is connected to the bit line BL. For reference, one side of the first MOS transistor M0 is floated because it does not affect the OTP memory cell storing and outputting data.

In general, a gate end of a MOS transistor is formed by stacking a conductive film on an insulating film. In the programming mode, the insulating layer at the gate terminal of the first MOS transistor MO is destroyed. The second MOS transistor M1 serves as a switch for selecting an OTP memory cell.

FIG. 2 is a circuit diagram showing after programming of the OTP memory cell shown in FIG. 2, a programming mode of the OTP memory cell shown in FIG. 1 will be described. First, a body voltage of the first and second MOS transistors M0 and M1 is applied with a ground voltage.

The high voltage VPP is applied to the first word line WP, and the first voltage VPP / is a half level voltage of a smaller voltage, for example, the high voltage VPP, to the second word line VR. 2) is applied. In addition, a ground voltage is applied to the bit line BL. The high voltage (VPP) is a voltage made using a power supply voltage provided from the outside. The high voltage VPP is a voltage high enough to break the insulating film constituting the gate pattern of the first word line WP. For example, assuming that the power supply voltage is 1.2V, the high voltage VPP may be 6V higher than that.

Since the gate of the second MOS transistor M1 is applied with the first voltage VPP / 2, the gate of the second MOS transistor M1 is turned on, whereby the ground voltage is applied to the resistance node A. FIG. Since the high voltage VPP is applied to the gate terminal of the first MOS transistor M0, and the ground voltage is applied to one side, that is, the resistance node A, the insulating layer constituting the gate pattern of the first word line WP. It is destroyed. A current path is generated between the gate terminal of the first word line WP and the resistance node A, which is represented by a resistor Rf. In order to reliably destroy the insulating layer constituting the gate pattern of the first MOS transistor M0 at the programming node, the thin MOS transistor having the relatively thin insulating layer of the gate pattern is configured as the first MOS transistor M0. . In addition, the high voltage VPP maintains a voltage higher than a voltage capable of destroying the insulating layer constituting the gate pattern of the first MOS transistor MO, thereby increasing the reliability of programming.

In the read mode, the power supply voltage VDD is applied to the first word line WP, and the power supply voltage VDD is also applied to the second word line WR. The bit line BL is precharged with a ground voltage. At this time, if the insulating film constituting the gate pattern of the first MOS transistor M0 is destroyed, the voltage level of the bit line BL is increased. The bit line sense amplifier (not shown) connected to the bit line BL detects this. The bit line sense amplifier senses by comparing the reference voltage and the voltage level of the bit line BL.

If the insulating layer constituting the gate pattern of the first MOS transistor M0 is not broken, the voltage level of the bit line BL does not rise and maintains the precharged voltage. In the read mode, the data applied to the bit line BL may be sensed by the bit line sense amplifier connected to the bit line BL to determine data '0' or '1'.

However, the OTP memory cell shown in FIG. 2 has the following problems.

First, the system has to wait a lot of time to utilize the data stored in the OTP memory cell. The data access timing of the OTP memory cell discussed so far may be about 200 ns. Assume that the above-described OTP memory cell is used in a system having an operating clock of 100 MHz. The system then has to wait a lot of time to utilize the data stored in the OTP memory cell. In order to read data of an OTP memory cell in real time, an additional buffer memory such as an SRAM or a register is required.

Secondly, the structure of the OTP memory cell shown in Fig. 1 has a problem that the portion to be broken when the gate insulating film is broken down during programming is not constant. When programmed, the body of the first MOS transistor is a ground voltage, one side of which is floating, and the other side of the resistance node A receives a ground voltage. Therefore, the portion where the gate insulating film is destroyed is more likely to be a portion closer to the resistive node A, but in some cases, it may be the center region of the gate insulating film. As the breakdown position of the gate insulating film becomes random, the resistance value of the resistor Rf shown in FIG. 2 varies in magnitude. Therefore, in the case of using the above-described OTP memory cell, for stable data access, the OPT cell should be designed on the assumption that the resistance value of the resistor Rf shown in FIG. 2 is the highest.

As such, the OTP memory cell shown in FIG. 1 has many limitations in reducing the data access timing. To overcome this problem, the present invention proposes a semiconductor device having an OTP memory cell capable of data access at high speed.

3 is a block diagram illustrating a semiconductor memory device including an OTP memory cell according to an embodiment of the present invention.

As shown in FIG. 3, the semiconductor device 100 including an OTP memory cell includes an address control unit 110, a control logic 120, a column decoder 130, and a cell array 140 including a low decoder wordline driver. ), A data output unit 150 and a reference signal providing unit 160. The row decoder provided in the address control unit 110 is for decoding a row address, and the word line driver is for driving a word line selected according to the decoding result of the row decoder. The control logic 120 controls the address control unit 110, the data output unit 150, and the column decoder 130 according to an externally provided command. The column decoder 130 is for decoding the column address. The data output unit 150 outputs a signal selected by a column address among a plurality of signals provided from the cell array 140 to the outside. Cell array 140 includes a plurality of OTP memory cells.

The reference signal providing unit 160 is for providing a reference signal for sensing a signal provided by each cell in the cell array. The sensing circuit provided in the data output unit 150 compares the reference signal provided by the reference signal providing unit 160 with a signal provided by one cell in the cell array to detect what data is stored in the cell. do. The signal provided by the cell is provided through the bit line.

The semiconductor device shown in FIG. 3 may be configured as one device independently, or may be included in another memory device or semiconductor device. For example, it may serve to store trimming information, security ID, chip ID, calibration data, or the like of the integrated circuit, or to store redundancy information of the main memory.

4 is a circuit diagram illustrating a semiconductor device including an OTP memory cell according to an embodiment of the present invention. FIG. 5 is a circuit diagram showing after the OTP memory cell shown in FIG. 4 is programmed.

Referring to FIG. 4, the first MOS transistor M1 receives the bias enable signal BIAS_EN as the first gate G1 and receives the bias voltage PGM_BIAS to one side. ), A second MOS transistor M2 and a third gate G3 that receive a first gate signal WLP through a second gate G2, and whose one side is connected to the other side of the first MOS transistor M1. The second MOS transistor M3 is provided with a second gate signal WLR, and one side is connected to the other side of the second MOS transistor M2. That is, three MOS transistors form one OTP cell. have. The insulating film of the second gate G2 is destroyed by the programming mode.

In programming mode, the bias voltage PGM_BIAS is applied with a predetermined level of voltage. For example, it may have a voltage of 1 ~ 2V. In order to destroy the insulating layers of the second gate G2 and the fifth gate G5, a high voltage higher than the bias voltage PGM_BIAS is applied to the first gate signal WLP. The second gate signal WLR and the bias enable signal BIAS_EN are maintained at a turn-on voltage to turn on the first and third MOS transistors M1 and M3 and the fourth and sixth MOS transistors M4 and M6. . When the insulating film of the second gate G2 is destroyed, one side of the gate 2 and the MOS transistor M2 and a current path are generated (see Rf in FIG. 5).

6 is a circuit diagram illustrating a comparison circuit included in the reference signal providing unit of FIG. 3.

Referring to FIG. 6, the reference signal providing unit 160 compares a bit line BL provided from a cell of a cell array with a reference signal RL, and outputs a signal OUT corresponding to the result. A circuit 161 is provided. The comparison circuit 161 may use an operational amplifier circuit or a differential amplifier circuit. The comparison circuit 161 may be provided as many as the number of memory cells included in the cell array. Each comparison circuit may be configured to receive a common input of a reference signal RL to one side, and to receive a bit line BL provided from a cell of a corresponding cell array.

7 and 8 are waveform diagrams showing the operation of the semiconductor device shown in FIG. In detail, FIG. 7 is a waveform diagram illustrating a program operation, and FIG. 8 relates to a read operation. In particular, the case where the gate pattern insulating film of the MOS transistor M2 is destroyed in the case of FIGS. 7 and 8 will be described.

Referring to FIG. 7, in the programming mode, a bias (PGM_BIAS) is applied with a voltage of 1 to 2V. A voltage of 6 to 8 V, which is a high voltage VPP, is applied to the first gate signal WLP, and half of the high voltage VPP is applied to the second gate signal WLR. 2.8V is applied to the bias enable signal BIAS_EN. The ground voltage is applied to the bit line BL.

The gate pattern is usually formed by stacking an insulating film and a conductive film. Here, the gate insulating film refers to an insulating film disposed under the conductive film of the gate pattern. Therefore, when the high voltage VPP and the ground voltage applied to both ends of the gate insulating film of the second MOS transistor M2 are applied, the insulating film is destroyed. However, since the turn-on voltage of 1/2 level of the high voltage VPP is applied to the gate of the third MOS transistor M3, the insulating film is not destroyed.

The other end of the first MOS transistor M1 and the second MOS transistor M2 is configured to generate a hot carrier in a channel region of the first or second MOS transistors M1 and M2 so as to generate a predetermined bias voltage BIAS. Is applied. The bias voltage PGM_BIAS has a lower level than the high voltage VPP. For example, as described above, when the driving voltage is 1.2V, the high voltage VPP may have a value ranging from 6V to 8V, and the bias voltage PGM_BIAS may be in a range of 1 to 2V. In this case, the high voltage VPP may be such that the gate insulating films of the first and second MOS transistors M1 and M2 can be destroyed. For operating margin, a voltage 5-10% higher than the voltage that can destroy the gate insulating film can be applied.

FIG. 8 is a waveform diagram illustrating a driving voltage provided in a read mode of the OTP memory cell shown in FIG. 4.

Referring to FIG. 8, in the read mode, the driving voltage Vread is applied to the first and second gate signals WLP and WLR, and the ground voltage VSS, which is the deactivation voltage, is applied to the bias enable signal BIAS_EN. The bit line BL is precharged with the precharge voltage Precharge 0V. The bias voltage PGM_BIAS does not matter what voltage is applied, which is assumed to be floated here.

If the gate insulating film of the MOS transistor M2 is destroyed, a current path is generated between the gate G2 and the resistance node N (see Rf). Therefore, the voltage level of the bit line BL is gradually increased. If the insulating film of the gate is not broken, the voltage level of the bit line does not rise. Data stored in the OTP memory cell can be read by the presence or absence of the current provided from the bit line BL.

The comparison circuit 161 compares the bit line BL and the reference signal RL and outputs an output signal OUT depending on whether the level of the bit line BL is higher or lower than the reference signal RL.

For example, when the gate insulating film of the second MOS transistor M2 is destroyed and the voltage of the bit line BL is increased, the comparison circuit 161 outputs a high level output signal OUT, When the gate insulating layer is not destroyed and the voltage of the bit line BL is not increased, the comparison circuit 161 outputs the low level output signal OTU. If the signal output from the comparison circuit 161 is high level, it may be read as data '1', and if it is low level, it may be read as data '0'. Therefore, the voltage level of the reference signal RL should be lower than the level at which the gate insulating film of the second MOS transistor M2 is destroyed and the voltage of the bit line BL can rise.

The OTP memory cell according to the present embodiment is characterized in that the bias voltage PGM_BIAS is applied in the program mode. When the bias voltage is applied to one side of the MOS transistor M1 while the high voltage is applied to the gate, current flows to one side and the other end of the MOS transistor M2, and a hot carrier is applied to the channel region of the MOS transistor M2. Electrons are injected into the gate. The injected high energy electrons create a high energy hole in the gate. The generated holes are then tunneled back to the channel. This hole helps to destroy the gate insulating film. Therefore, this mechanism can reduce the time that the gate insulating film is destroyed, thereby reducing the time for storing data in the program mode.

In addition, the portion where the gate insulating film is destroyed by the holes generated in this operation is fixed toward one side edge of the channel. Since the portion where the gate insulating film is destroyed is fixed constantly, the resistance value of the resistor Rf generated by the destruction of the gate insulating film can be maintained at the lowest value among possible resistance values. When the resistance value of the resistor generated by the gate insulating film breakdown becomes constant, the speed of changing the voltage of the bit line BL in the read mode can also be kept constant. In addition, since the speed of changing the voltage of the bit line BL can be relatively increased, the data access time of the OTP cell can be increased.

As described so far, unlike the OTP cell shown in FIG. 1, the OTP cell according to the present embodiment can lower the resistance value of the resistance generated by the gate insulating film that is destroyed. This can increase the read time of the data. In addition, since the bias voltage BGM_BIAS is provided, the rate at which the gate insulating film is destroyed can be increased, and the write time can be reduced. Therefore, the access time of the OTP memory cell according to the present embodiment can be significantly reduced than that shown in Fig. 1, and the additional buffer memory is unnecessary when the OTP memory cell according to the present embodiment is used in the system. The efficiency of the operation can be improved.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, I will understand. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the scope of the appended claims, as well as the appended claims.

Claims

A cell array having at least one OTP memory cell;
A reference signal providing unit providing a reference signal; And
A data output unit including at least one comparison circuit by comparing the data line signal provided to the cell array with the reference signal,
The OPT memory cell
A first MOS transistor configured to receive a bias enable signal through a first gate and receive a first bias voltage to one side;
A second MOS transistor receiving a first gate signal through a second gate and having one side connected to the other side of the first MOS transistor; And
A third MOS transistor receiving a second gate signal through a third gate and having one side connected to the other side of the second MOS transistor
A semiconductor device comprising an OTP memory cell having a.

The method of claim 1,
And an OTP memory cell, wherein the insulating film at the second gate end is destroyed by a programming mode.

The method of claim 1,
In the programming mode, the first bias voltage is applied with a predetermined level of voltage, and the high voltage higher than the first bias voltage is applied to the first gate signal to destroy the insulating layer of the second gate. And a bias enable signal include an OTP memory cell, wherein a turn-on voltage is applied to turn on the first and third MOS transistors.

The method of claim 3, wherein
And a hot carrier in a channel corresponding to the second gate by the first bias voltage and the first gate signal in the programming mode.

The method of claim 3, wherein
And said turn-on voltage is one half of said high voltage.

The method of claim 3, wherein
In the read mode, the first bias voltage is a ground voltage is applied, the first gate signal and the second gate signal is a semiconductor device including an OTP memory cell characterized in that the turn-on voltage is applied.

The method of claim 1, wherein
And the comparison circuit comprises an OTP memory cell or an OTP memory cell.

The method of claim 1,
And the data output unit includes a plurality of comparison circuits, wherein the plurality of comparison circuits share the reference signal in common.