KR20130079853A - Non-volatile memory device and memory system comprising the same - Google Patents

Non-volatile memory device and memory system comprising the same Download PDF

Info

Publication number
KR20130079853A
KR20130079853A KR1020120000592A KR20120000592A KR20130079853A KR 20130079853 A KR20130079853 A KR 20130079853A KR 1020120000592 A KR1020120000592 A KR 1020120000592A KR 20120000592 A KR20120000592 A KR 20120000592A KR 20130079853 A KR20130079853 A KR 20130079853A
Authority
KR
South Korea
Prior art keywords
read
read mode
page
memory device
voltage
Prior art date
Application number
KR1020120000592A
Other languages
Korean (ko)
Inventor
심동교
권오석
윤현준
박기태
정재용
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020120000592A priority Critical patent/KR20130079853A/en
Priority to US13/527,641 priority patent/US8861276B2/en
Publication of KR20130079853A publication Critical patent/KR20130079853A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Landscapes

  • Read Only Memory (AREA)

Abstract

In an embodiment, a nonvolatile memory device may include a memory cell array connected to a plurality of bit lines and a plurality of word lines, a page buffer circuit configured to sense memory cells connected to a selected word line through the plurality of bit lines; A voltage generator for providing a read voltage to the selected word line, and control logic to control the page buffer circuit and the voltage generator to sense memory cells connected to the selected word line in accordance with a first read mode or a second read mode. The number of memory cells sensed simultaneously in the first read mode and the second read mode is different, and the voltage generator provides a read voltage for the same data state differently according to the number of sensed memory cells.

Figure P1020120000592

Description

A nonvolatile memory device and a memory system including the same {NON-VOLATILE MEMORY DEVICE AND MEMORY SYSTEM COMPRISING THE SAME}

The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile memory device and a memory system including the same.

The semiconductor memory device may be classified into a volatile semiconductor memory device and a non-volatile semiconductor memory device. The volatile semiconductor memory device has a drawback that the read and write speed is fast but the stored contents disappear when the power supply is interrupted. On the other hand, the nonvolatile semiconductor memory device preserves its contents even if the power supply is interrupted. Therefore, the nonvolatile semiconductor memory device is used to store contents to be stored regardless of whether power is supplied or not.

Nonvolatile semiconductor memory devices include, but are not limited to, a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM) Erasable programmable read-only memory (EEPROM), and the like.

A representative example of the nonvolatile memory device is a flash memory device. The flash memory device may be a computer, a mobile phone, a PDA, a digital camera, a camcorder, a voice recorder, an MP3 player, a personal digital assistant (PDA), a handheld PC, a game machine, a fax machine, a scanner, ) Are widely used as audio and video data storage media for information devices such as digital cameras.

In recent years, as the high integration demand for memory devices increases, multi-bit memory devices storing multiple bits in one memory cell have become popular.

Disclosure of Invention An object of the present invention is to provide a nonvolatile memory device implemented with an ABL (All Bit Line) and a read method thereof that can improve the performance of a read operation.

According to an embodiment of the present invention, a nonvolatile memory device may include a memory cell array connected to a plurality of bit lines and a plurality of word lines, and memory cells connected to a selected word line through the plurality of bit lines. A page buffer circuit for sensing, a voltage generator for providing a read voltage to the selected word line, and the page buffer circuit and the voltage to sense memory cells connected to the selected word line according to a first read mode or a second read mode. Control logic for controlling a generator, wherein the number of memory cells sensed simultaneously in the first read mode and the second read mode is different, wherein the voltage generator is configured to measure the read voltage for the same data state to the number of memory cells sensed. Provide differently according.

According to an aspect of the present invention, there is provided a nonvolatile memory device having an all-bit line structure, and applying a full page read command or a partial page read command for a selected page to the nonvolatile memory device. And a memory controller, wherein the nonvolatile memory device generates different read voltages for the same data state according to the read command.

According to an exemplary embodiment of the present invention, a high-speed read operation may be performed during a partial page read operation of an all-bit line nonvolatile memory device, and reliability of read data may be improved.

1 is a block diagram illustrating a configuration of a nonvolatile memory device according to the present invention.
FIG. 2 is a diagram illustrating the structure of the cell array and page buffer circuit shown in FIG. 1.
3 is a diagram illustrating a thermal addressing method according to an embodiment of the present invention.
4 is a diagram illustrating voltages in a full page read mode and a partial page read mode according to an exemplary embodiment of the present invention.
5 are waveform diagrams showing levels of read voltages applied in a full page read mode and a partial page read mode, respectively.
6 is a block diagram illustrating a memory cell array of FIG. 1.
FIG. 7 is a perspective view illustrating one of the memory blocks of FIG. 6.
8 is a block diagram illustrating a nonvolatile memory device according to another exemplary embodiment of the present invention.
FIG. 9 is a timing diagram illustrating input / output characteristics of the nonvolatile memory device of FIG. 8.
10 is a block diagram illustrating a nonvolatile memory device according to another embodiment of the present invention.
FIG. 11 is a flowchart illustrating an operation of a nonvolatile memory device of FIG. 10.
12 is a block diagram illustrating a solid state drive according to an exemplary embodiment of the present invention.
13 is a block diagram illustrating a data storage device in accordance with some embodiments of the inventive concept.
14 is a block diagram illustrating a memory card in accordance with an embodiment of the disclosure.
15 is a schematic block diagram of a flash memory device and a computing system including the same according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. The same elements will be referred to using the same reference numerals. Similar components will be referred to using similar reference numerals. The circuit configuration of the flash memory device according to the present invention to be described below and the read operation performed by the present invention are just examples, and various changes and modifications can be made without departing from the technical spirit of the present invention.

1 is a block diagram illustrating a non-volatile memory device 100 in accordance with an embodiment of the present invention. Referring to FIG. 1, the nonvolatile memory device 100 includes a cell array 110, a row decoder 120, a page buffer circuit 130, an input / output buffer 140, a control logic 150, and a voltage generator 160. ).

The cell array 110 is connected to the row decoder 120 through word lines WLs or select lines SSL and GSL. The cell array 110 is connected to the page buffer circuit 130 through bit lines BL0 to BLn-1. The cell array 110 includes a plurality of NAND Cell Strings. Each cell string may form a channel in a vertical or horizontal direction. In the cell array 110, a plurality of word lines may be stacked in a vertical direction. The cell array 110 according to the embodiment of the present invention has an all bit line (ABL) structure. The All Bit Line (ABL) structure is a structure in which one page buffer is connected to one bit line to simultaneously program memory cells connected to the selected word line.

The row decoder 120 may select any one of the memory blocks of the cell array 110 in response to the address ADD. The row decoder 120 may select any one of the word lines of the selected memory block. The row decoder 120 transfers the voltage from the voltage generator 160 to the word line of the selected memory block. In the program operation, the row decoder 120 transfers the program voltage Vpgm and the verify voltage Vvfy to the selected word line and the pass voltage Vpass to the unselected word line Unselected WL. In the read operation, the row decoder 120 transmits the selected read voltage Vrd to the selected word line WL and the unselected read voltage Vread to the unselected word line WL.

The page buffer circuit 130 operates as a write driver or as a sense amplifier depending on the mode of operation. In a program operation, the page buffer circuit 130 transfers a bit line voltage corresponding to data to be programmed into a bit line of the cell array 110. In a read operation, the page buffer circuit 130 senses data stored in a selected memory cell through a bit line. The page buffer circuit 130 latches the sensed data and delivers the detected data to the input / output buffer 140. The page buffer circuit 130 includes a plurality of page buffers connected to respective bit lines.

The page buffer circuit 130 according to an embodiment of the present invention is connected to the cell array 110 having an all bit line structure. The page buffer circuit 130 may read all of the selected page data at once. This read mode is called full page read mode. The page buffer circuit 130 may select and read a portion of the selected page during the read operation. This read mode is called a partial page read mode. In the partial page read mode, the page buffer circuit 130 may ground the bit line of unselected memory cells. Through this ground, shielding may be provided to a bit line of selected memory cells. The partial page read mode is further subdivided into a half page read mode that reads half of the memory cells included in the selected page, and a quarter page read mode that reads in quarter page units. Can be. In an embodiment of the present invention, the half page read mode will be used as an example of the partial page read mode.

The input / output buffer 140 transfers the write data input during the program operation to the page buffer circuit 130. The input / output buffer 140 outputs read data provided from the page buffer circuit 130 to the outside during a read operation. The input / output buffer 140 transmits an input address or command to the control logic 150 or the row decoder 120.

The control logic 150 controls the page buffer circuit 130 and the voltage generator 160 in response to the command CMD and the address ADD transmitted from the input / output buffer 140. The control logic 150 controls the page buffer circuit 130 and the voltage generator 160 to sense the selected memory cells in different ways according to the read mode in order to compensate for the sensing noise during the read operation.

For example, the control logic 150 controls the page buffer circuit 130 and the voltage generator 160 to sense the selected memory cells in a coarse-fine sensing method in the full page read mode. In addition, the control logic 150 controls the page buffer circuit 130 and the voltage generator 160 to sense selected memory cells in a sensing method different from a coarse-fine sensing method in the partial page read mode. do.

Here, the coarse-fine sensing method refers to a method of sensing two consecutively selected memory cells with different read voltages in order to reduce sensing noise. That is, a coarse sensing operation of sensing selected memory cells at a level lower than a target level is performed first. Only off-cells are selected among the cells sensed by the coarse sensing. A fine sensing operation in which the selected off-cells are sensed at the target level is performed. The data sensed and latched by fine sensing is output as the final read data. In the all bit line structure, some on-cells are selected by coarse sensing. In fine sensing, since the on cells selected in the coarse sensing are excluded, the common source line noise CSL noise may be reduced.

The control logic 150 controls the page buffer circuit 130 and the voltage generator 160 to sense the selected memory cells by providing only one read voltage for one data state in the partial page read mode. In the partial page read mode, the control logic 150 will control the page buffer circuit 130 so that unselected bit lines are grounded.

The voltage generator 160 generates various types of word line voltages to be supplied to the respective word lines and a voltage to be supplied to the bulk (for example, the well region) in which the memory cells are formed, under the control of the control logic 150 Occurs. The word line voltages to be supplied to the respective word lines include the program voltage Vpgm, the pass voltage Vpass, the selected and unselected read voltages Vrd and Vread, and the like. The voltage generator 160 may generate the selection line voltages V SSL and V GSL provided to the selection lines SSL and GSL during read and program operations.

In particular, the voltage generator 160 provides a read voltage at a level different from that of the read voltage provided in the full page read mode in the partial page read mode. That is, in the partial page read mode, the read voltage is generally provided at the same level as the read voltage provided during the fine sensing operation. However, the voltage generator 160 of the present invention may provide a read voltage having a level higher than that of the read voltage provided in the fine sensing operation in the partial page read mode.

In the partial page read mode, the number of selected memory cells is relatively smaller than in the full page read mode. Thus, in the partial page read mode, the common source line noise (CSL Noise) is less than in the full page read mode. Therefore, in the partial page read mode, the level of the read voltage provided may be higher than the read voltage during fine sensing for the same data state. This setting ensures high data reliability even in partial page read mode.

The nonvolatile memory device 100 described above may provide different read voltage levels for selected memory cells according to a read mode. According to the sensing method, the nonvolatile memory device 100 of the present invention may compensate for common source line noise and increase a read speed.

2 is a block diagram illustrating the cell array 110 and the page buffer circuit 130 of FIG. 1. Referring to FIG. 2, the even-numbered bit lines are assigned to the continuous column address, and the odd-numbered bit lines are also assigned to the continuous column address.

A plurality of bit lines BL0 to BLn-1 may be formed in the cell array 110. In the column address of the cell array 110 according to the present invention, even-numbered bit lines and odd-numbered bit lines have discontinuous values. That is, the even and odd bit lines are addressed to have discontinuous column addresses with each other. For example, when one page is 8KB in size, even-numbered bit lines BL0, BL2, BL4, ... may be addressed with column addresses 0, 1, 2, ..., respectively. The odd bit lines BL1, BL3, BL5,... May be addressed with column addresses 4096, 4097, 4098,...

The page buffer circuit 130 includes page buffers PB0 to PBn-1 connected to each of the bit lines BL0 to BLn-1. The page buffers PB0 to PBn-1 write data to the selected memory cell through the bit lines BL0 to BLn-1, or sense the written data. In particular, the page buffer circuit 130 of the present invention may include ground transistors GTR0 to GTRn-1 that may ground non-selected bit lines under the control of the control logic 150. If a column address corresponding to the partial page read mode is provided, the control logic 150 will activate one of the control signals DIS_E and DIS_O to ground the unselected bit lines.

Here, the ground transistors GTR0 to GTRn-1 are illustrated as being formed in the page buffer circuit 130, but the present invention is not limited thereto. Ground transistors GTR0 to GTRn-1 may be formed outside the page buffer circuit 130.

The control logic 150 outputs control signals DIS_E and DIS_O for grounding unselected bit lines according to the full page read mode or the partial page read mode. In full page read mode, control logic 150 deactivates control signals DIS_E and DIS_O. On the other hand, in the partial page read mode (eg, half page read mode), the control logic 150 will activate any of the control signals DIS_E and DIS_O to connect the unselected bit lines to ground. . The control logic 150 may determine whether to activate the control signals DIS_E and DIS_O with reference to the command or the address ADD.

Through the above structure, the non-selected bit lines of the nonvolatile memory device 100 are grounded in the partial page read mode. Thus, shielding can be provided for the selected bit line. In addition, according to the above-described column address structure, the data sensed in the partial page read mode may be immediately output to the outside.

3 is a diagram illustrating an example of an addressing method for bit lines. Referring to FIG. 3, a column addressing scheme in an all bit line structure in which 8 KB size pages are programmed at a time will be described as an example.

The even-numbered bit lines BL0, BL2, BL4, ..., BL8186, BL8188, BL8190 are addressed to column addresses 0, 1, 2, ..., 4093, 4094, 4095, respectively. The odd bit lines BL1, BL3, BL5,..., BL8187, BL8189, and BL8191 are addressed to column addresses 4096, 4097, 4098,..., 8189, 8190, and 8191, respectively. In the partial page read mode in which even-numbered bit lines are selected, data sensed through the even-numbered bit lines may constitute a plurality of consecutive sectors. Therefore, data sensed by even-numbered bit lines may be output regardless of whether the odd-numbered bit lines are sensed.

Here, it has been described that such an addressing scheme is applied only to bit lines of the main region that can be selected from the outside through addressing, but the present invention is not limited thereto. That is, the read of the bit lines to the spare area may be controlled in the same manner as in the main area. The partial page read mode may be applied to the bit lines of the spare area, and the unselected bit lines may be controlled to be grounded. That is, the bit lines of the spare area may include a first spare bit line corresponding to even-numbered bit lines and a second spare bit line corresponding to odd-numbered bit lines. .

In the spare area, meta data, flag bits, and the like corresponding to control information of data of the main area are stored. Accordingly, the data sensed through the first spare bit line (Sparre 1st Half) may provide sufficient control information for the main data sensed through the even-numbered bit lines BL0, BL2, BL4, ..., BL8186, BL8188, and BL8190. It must be configured to provide. In addition, the data sensed through the second spare bit line (Sparre 2nd Half) is sufficient control information for the main data sensed through the odd bit lines BL1, BL3, BL5, ..., BL8187, BL8189, BL8191. It must be configured to provide.

In the program operation, control information about main data corresponding to even-numbered bit lines may be programmed in memory cells of the spare area corresponding to the first spare bit line. In addition, control information on main data corresponding to odd bit lines may be programmed in memory cells corresponding to the second spare bit line.

4 is a view for explaining the read voltage of the present invention. Referring to FIG. 4, in the full page read mode, the voltage generator 160 generates read voltages Vrd1_C, Vrd1_F, Vrd2_C, Vrd2_F, Vrd3_C, and Vrd3_F for coarse-fine sensing. In the half page read mode, the voltage generator 160 generates read voltages Vrd1_H, Vrd2_H, and Vrd3_H. Hereinafter, in order to explain the read operation of the present invention, a 2-bit MLC will be described as an example.

(a) shows the read voltages provided during the first page (1st page, or MSB page) read operation. Read voltages Vrd2_C and Vrd2_F for coarse-fine sensing for reading the first page in the full page read mode will be provided. However, in the half page read mode, a read voltage Vrd2_H for reading the first page will be provided. The read voltage Vrd2_H provided in the half page read mode is relatively higher than the read voltages Vrd2_C and Vrd2_F provided in the full page read mode.

(b) shows the read voltages provided in the second page read operation. Read voltages Vrd1_C, Vrd1_F, Vrd3_C, and Vrd3_F for coarse-fine sensing for reading the second page in the full page read mode will be provided. In the half page read mode, read voltages Vrd1_H and Vrd3_H for reading the second page will be provided. The read voltage Vrd1_H provided in the half page read mode is relatively higher than the read voltages Vrd1_C and Vrd1_F provided in the full page read mode. The read voltage Vrd3_H provided in the half page read mode is relatively higher than the read voltages Vrd3_C and Vrd3_F provided in the full page read mode.

In the full page read mode and the half page read mode, the threshold voltage level measurement due to the difference of the common source line noise (CSL Noise) may vary. For example, the threshold voltage may be measured high for the same program state by common source line noise in the half page read mode. However, this error can be compensated for by the read voltages Vrd1_H, Vrd1_H, and Vrd3_H set in the half page read mode of the present invention. As a result, relatively high read voltages Vrd2_H, Vrd2_H, and Vrd3_H may be provided in the half page read mode, thereby providing an error rate that is similar or equivalent to that in the full page read mode.

5 is a waveform diagram schematically illustrating a word line voltage in a read mode according to the present invention. Referring to FIG. 5, the waveform of the word line voltage provided to read a second page (2nd page, or LSB page) in the full page read mode and the partial page read mode is different from each other.

First, in a full page read mode, a read voltage for coarse-fine sensing is applied to the selected word line. During the time period t0 to t1, a sensing operation for identifying the erase state E0 and the program state P1 is performed. Read voltages Vrd1_C and Vrd1_F for coarse sensing and fine sensing are sequentially applied to the selected word line (eg, WL <1>). The word line selected in the time periods t1 to t2 is discharged. During the time period t2 to t3, a sensing operation for identifying the program state P2 and the program state P3 is performed. Read voltages Vrd3_C and Vrd3_F for coarse sensing and fine sensing are sequentially applied to the selected word line (eg, WL <1>).

In the partial page read mode, a read voltage for fine sensing is applied to the selected word line. During the time period t0 to t1, a sensing operation for identifying the erase state E0 and the program state P1 is performed. A fine read voltage Vrd1_H for fine sensing is applied to the selected word line (eg, WL <1>). The word line selected in the time periods t1 to t2 is discharged. During the time period t2 to t3, a sensing operation for identifying the program state P2 and the program state P3 is performed. A fine read voltage Vrd3_H for fine sensing is applied to the selected word line (eg, WL <1>). The read voltage Vrd1_H provided in the partial page read mode is higher than the read voltage Vrd1_F provided in the full page read mode. The read voltage Vrd3_H provided in the partial page read mode is higher than the read voltage Vrd3_F provided in the full page read mode.

Here, although the waveform in the second page read operation is illustrated as an example, it will be appreciated that the waveform may be applied to the first page read mode. That is, the read voltage Vrd2_H provided in the partial page read mode in the first page read operation is higher than the read voltage Vrd2_F provided in the full page read mode. The waveform or pulse width in the partial page read mode may vary depending on the purpose.

6 is a block diagram illustrating the memory cell array 110 of FIG. 1. Referring to FIG. 6, the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block BLK has a three-dimensional structure (or a vertical structure). For example, each memory block BLK includes structures extending along the first to third directions x, y, and z. For example, each memory block BLK may include a plurality of NAND Cell Strings extending along the third direction z.

Each of the NAND cell strings is connected to a bit line BL, a string select line SSL, a ground select line GSL, word lines WL, and a common source line CSL. That is, each memory block includes a plurality of bit lines BL, a plurality of string select lines SSL, a plurality of ground select lines GSL, a plurality of word lines WL, and a common source line CSL. Will be connected to). The memory blocks BLK1 to BLKz are described in more detail with reference to FIG. 7.

FIG. 7 is a perspective view illustrating one of the memory blocks BLK1 to BLKz of FIG. 6. Referring to FIG. 7, the memory block BLKi includes structures extending along the first to third directions x, y, and z.

In order to form the memory block BLKi, a substrate 111 is first provided. For example, the substrate 111 may be formed as a P-well formed by implanting a Group 5 element such as boron (B, Boron). Alternatively, the substrate 111 may be formed into a pocket P-well provided in the N-well. Hereinafter, it is assumed that the substrate 111 is a P-well. However, the substrate 111 is not limited to the P-well.

On the substrate 111, a plurality of doped regions 311 ˜ 314 are formed along the first direction x. For example, the plurality of doped regions 311 to 314 may be formed of an n-type conductor different from the substrate 111. Hereinafter, it is assumed that the first to fourth doping regions 311 to 314 have n types. However, the first to fourth doped regions 311 to 314 are not limited to having an n-type.

On the region of the substrate 111 between the first and second doped regions 311 and 312, a plurality of insulating materials 112 extending along the first direction are sequentially along the third direction z. Is provided. For example, the plurality of insulating materials 112 may be formed to be spaced apart by a certain distance along the third direction z. Illustratively, the insulating materials 112 will comprise an insulating material such as silicon oxide.

On the substrate 111 between the first and second doped regions 311 and 312, a pillar 113 disposed sequentially in the second direction and penetrating the insulating materials 112 along the third direction is formed. Is formed. Illustratively, the pillar 113 will be connected to the substrate 111 through the insulating materials 112. Here, the pillar 113 is also formed on the upper portion of the substrate between the second and third doped regions 312 and 313 and the upper portion of the substrate between the third and fourth doped regions 313 and 314.

Illustratively, each pillar 113 will comprise a plurality of materials. For example, the surface layer 114 of each pillar 113 may comprise a silicon material having a first type. For example, the surface layer 114 of each pillar 113 will comprise a silicon material having the same type as the substrate 111. In the following, it is assumed that the surface layer 114 of each pillar 113 includes p-type silicon. However, the surface layer 114 of each pillar 113 is not limited to include p-type silicon.

The inner layer 115 of each pillar 113 is comprised of an insulating material. For example, the inner layer 115 of each pillar 113 may comprise an insulating material such as silicon oxide. For example, the inner layer 115 of each pillar 113 may include an air gap.

In an area between the first and second doped regions 311 and 312 an insulating layer 116 is provided along the exposed surfaces of the insulating materials 112, the pillars 113, and the substrate 111. In exemplary embodiments, the insulating layer 116 provided on the exposed surface of the last insulating material 112 on the third direction z side along the third direction z may be removed.

Illustratively, the thickness of the insulating film 116 may be less than one-half the distance between the insulating materials 112. That is, between the insulating film 116 provided on the lower surface of the first insulating material of the insulating materials 112 and the insulating film 116 provided on the upper surface of the second insulating material below the first insulating material, 112 and the insulating film 116 may be disposed.

In the region between the first and second doped regions 311 and 312, the first conductive materials 211 to 291 are provided on the exposed surface of the insulating film 116. For example, a first conductive material 211 extending along the second direction y is provided between the insulating material 112 adjacent to the substrate 111 and the substrate 111. More specifically, a first conductive material 211 extending in the first direction x is provided between the insulating film 116 of the lower surface of the insulating material 112 adjacent to the substrate 111 and the substrate 111. do.

Between the insulating film 116 of the upper surface of the specific insulating material among the insulating materials 112 and the insulating film 116 of the lower surface of the insulating material disposed on the specific insulating material, a first conductive material extending along the first direction is formed. Is provided. In exemplary embodiments, a plurality of first conductive materials 221 to 281 extending in the first direction are provided between the insulating materials 112. Illustratively, the first conductive materials 211-291 may be metallic materials. Illustratively, the first conductive materials 211-291 may be conductive materials such as polysilicon or the like.

In the region between the second and third doped regions 312 and 313, the same structure as the structure on the first and second doped regions 311 and 312 will be provided. For example, in the region between the second and third doped regions 312 and 313, a plurality of insulating materials 112 extending in the first direction, sequentially disposed along the first direction, and arranged in the third direction. Accordingly, a plurality of pillars 113 penetrating through the plurality of insulating materials 112, a plurality of insulating materials 112, and an insulating layer 116 provided on the exposed surface of the plurality of pillars 113. A plurality of first conductive materials 212 to 292 extending along one direction are provided.

In the region between the third and fourth doped regions 313 and 314, the same structure as the structure on the first and second doped regions 311 and 312 will be provided. For example, in the region between the third and fourth doped regions 312 and 313, a plurality of insulating materials 112 extending in the first direction, sequentially disposed along the first direction, and arranged in the third direction. Accordingly, a plurality of pillars 113 penetrating through the plurality of insulating materials 112, a plurality of insulating materials 112, and an insulating layer 116 provided on the exposed surface of the plurality of pillars 113. A plurality of first conductive materials 213 to 293 extending along one direction are provided.

Drains 321 are provided on the plurality of pillars 113, respectively. In exemplary embodiments, the drains 321 may be silicon materials doped with a second type. For example, the drains 321 may be silicon materials doped with n type. Hereinafter, it is assumed that the drains 321 include n type silicon. However, the drains 321 are not limited to include n type silicon. In exemplary embodiments, the width of each of the drains 321 may be larger than the width of the corresponding pillar 113. For example, each of the drains 321 may be provided in a pad form on an upper surface of the corresponding pillar 113.

On the drains 321, second conductive materials 331 ˜ 333 extending in the third direction are provided. The second conductive materials 331 ˜ 333 are sequentially disposed along the first direction. Each of the second conductive materials 331 to 333 is connected to the drains 321 of the corresponding region. In exemplary embodiments, the drains 321 and the second conductive material 333 extending in the third direction may be connected through contact plugs, respectively. Illustratively, the second conductive materials 331-333 will be metal materials. Illustratively, the second conductive materials 331 - 333 will be conductive materials such as polysilicon or the like.

8 is a block diagram illustrating a memory system according to an example embodiment. Referring to FIG. 8, the memory system 200 of the present invention includes a memory controller 210 and a nonvolatile memory device 220. In particular, the memory controller 210 may select a read mode of the nonvolatile memory device 220 through a command.

The memory controller 210 controls the nonvolatile memory device 220. The memory controller 210 provides a read command corresponding to the full page read mode or the partial page read mode to the nonvolatile memory device 220. When the selected page is accessed according to the full page read mode, the memory controller 210 may provide the full page read command FPRD_CMD to the nonvolatile memory device 220. On the other hand, when the selected page is accessed according to the partial page read mode, the memory controller 210 transmits the partial page read command PPRD_CMD to the nonvolatile memory device 220.

The nonvolatile memory device 220 accesses memory cells with reference to the read command FPRD_CMD or PPRD_CMD from the memory controller 210. If the command provided from the memory controller 210 corresponds to the full page read mode, the nonvolatile memory device 220 senses all the memory cells of the selected page. In this case, the memory cells of the selected page may be read by a coarse-fine sensing method. In contrast, when a command provided from the memory controller 210 corresponds to a partial page read mode, the nonvolatile memory device 220 senses some memory cells of the selected page. In this case, the selected memory cells are sensed at different levels from the read voltage provided in the coarse-fine sensing mode. That is, the read voltage provided in the partial page read mode may be provided at a level higher than that provided in the full page read mode in order to sense the same data state.

9 is a timing diagram illustrating an example of a read command of FIG. 8. 9, a command input sequence in a full page read mode and a command input sequence in a partial page read mode are shown, respectively.

In the full page read mode, the memory controller 210 may provide a general page read command to the nonvolatile memory device 220. For example, the memory controller 210 may provide a command / address sequence (00h-Address-30h) to the nonvolatile memory device 220. Then, the nonvolatile memory device 220 selects a page corresponding to an address and senses it in a coarse-fine manner. The nonvolatile memory device 220 may latch the sensed full page data and output the full page data after a predetermined cycle.

On the other hand, in the partial page read mode, the memory controller 210 may provide a partial page read command PPRD_CMD to the nonvolatile memory device 220. For example, the memory controller 210 may provide a command / address sequence (00h-Address-40h) to the nonvolatile memory device 220. Then, the nonvolatile memory device 220 selects a page corresponding to an address and performs a partial page read operation. The read voltage provided in the partial page read mode may be provided at a level higher than that provided in the full page read mode in order to sense the same data state. The nonvolatile memory device 220 may latch the sensed partial page data and output the partial page data after a predetermined cycle.

In the partial page read mode, the sensed partial page data may be output to the outside immediately after being latched. Therefore, partial page data on which sensing is completed may be output before sensing of one entire page is completed. Therefore, the output time of the partial page data may be output almost without difference from the output time of the full page data, or may be output faster. This is because in the partial page read mode, only one sensing of one data state is performed by the read voltage. That is, the output time of the partial page data may be advanced by reducing the sensing time.

10 is a block diagram illustrating a memory system according to another example embodiment of the disclosure. Referring to FIG. 10, the memory system 300 of the present invention includes a memory controller 310 and a nonvolatile memory device 320. The memory controller 310 can set the read mode of the nonvolatile memory device 320 through a Set feature command.

The memory controller 310 may set a set feature of the nonvolatile memory device 320. In response to the full page read mode, the memory controller 310 may provide a general page read command to the nonvolatile memory device 320. On the other hand, when the read request corresponds to the partial page read request, the memory controller 310 transfers a set feature command to the nonvolatile memory device 320 to switch to the set feature corresponding to the partial page read mode. When setting of the set feature is completed, the memory controller 310 may transmit a read command and an address to the nonvolatile memory device.

The nonvolatile memory device 320 sets various parameters for performing the read mode with reference to the set feature command from the memory controller 310. In the default state before the set feature command is provided, the read mode of the nonvolatile memory device 320 has a set feature corresponding to the full page read mode. However, if a set feature command is provided, the nonvolatile memory device 320 is adjusted with settings for performing a partial page read mode. In addition, the setting of the nonvolatile memory device 320 may be adjusted to a default state by a command for returning the set feature to the setting for the full page read mode.

FIG. 11 is a flowchart schematically illustrating an operation of the memory system of FIG. 10. Referring to FIG. 11, the nonvolatile memory device 320 (see FIG. 10) performs a read command from the memory controller 310 with reference to a set feature value set therein. Here, it is assumed that the read mode of the nonvolatile memory device 320 is set by the set feature command.

In operation S110, the nonvolatile memory device 320 receives a read command from the memory controller 310.

In operation S120, the nonvolatile memory device 320 checks a read mode already set in order to perform a read command. The nonvolatile memory device 320 determines whether the set feature previously set is a full page read mode or a partial page read mode. If the set feature set corresponds to the full page read mode (or default state), the procedure moves to step S130. On the other hand, if the set feature is in the partial page read mode, the procedure moves to step S140.

In operation S130, the nonvolatile memory device 320 senses and outputs memory cells corresponding to the input address according to the full page read mode. According to the full page read mode, the nonvolatile memory device 320 senses selected memory cells in a coarse-fine manner. Read voltages (eg, Vrd1_C, Vrd1_F, Vrd2_C, Vrd2_F, Vrd3_C, Vrd3_F) for coarse-fine sensing in the full page read mode will be provided. When the nonvolatile memory device 320 outputs the sensed data, the requested data read is terminated.

In operation S140, the nonvolatile memory device 320 senses and outputs memory cells corresponding to the input address according to the partial page read mode. When sensing the memory cells selected according to the partial page read mode, read voltages (eg, Vrd1_H, Vrd2_H, and Vrd3_H) higher than the full page read operation mode may be provided as the read voltage.

The data of the page selected according to the read operation of the nonvolatile memory device 320 may be sensed and output according to the full page read mode or the partial page read mode.

12 is a block diagram illustrating a user device including a solid state disk (SSD) according to an exemplary embodiment of the present invention. Referring to FIG. 12, a user device 1000 includes a host 1100 and an SSD 1200. The SSD 1200 includes an SSD controller 1210, a buffer memory 1220, and a non-volatile memory device 1230.

The SSD controller 1210 provides a physical connection between the host 1100 and the SSD 1200. That is, the SSD controller 1210 provides interfacing with the SSD 1200 in response to the bus format of the host 1100. In particular, the SSD controller 1210 decodes the instruction provided from the host 1100. [ Depending on the decoded result, the SSD controller 1210 accesses the non-volatile memory device 1230. The bus format of the host 1100 is Universal Serial Bus (USB), Small Computer System Interface (SCSI), PCI express, ATA, Parallel ATA (PATA), Serial ATA (SATA), and Serial Attached SCSI (SAS). Etc. may be included.

The SSD controller 1210 decodes a read request from the host 1100 and selects one of a partial page read mode and a full page read mode. The SSD controller 1210 may control the nonvolatile memory device 1230 to access the memory cells according to the corresponding read mode. For example, the SSD controller 1210 may control the nonvolatile memory device 1230 to set a specific read command (eg, a partial page read command) or a set feature.

In the buffer memory 1220, write data provided from the host 1100 or data read from the nonvolatile memory device 1230 are temporarily stored. When data existing in the nonvolatile memory device 1230 is cached at the time of the read request of the host 1100, the buffer memory 1220 supports the cache function of providing the cached data directly to the host 1100 . Generally, the data transfer rate by the host 1100 in the bus format (e.g., SATA or SAS) is much faster than the transfer rate of the memory channel of the SSD 1200. That is, when the interface speed of the host 1100 is much higher, performance degradation caused by speed difference can be minimized by providing a buffer memory 1220 of a large capacity.

The buffer memory 1220 may be provided to a synchronous DRAM (DRAM) to provide sufficient buffering in the SSD 1200 used as a large capacity auxiliary storage device. However, it will be apparent to those skilled in the art that the buffer memory 1220 is not limited to the disclosure herein.

The nonvolatile memory device 1230 is provided as a storage medium of the SSD 1200. For example, the non-volatile memory device 1230 may be provided as a NAND-type Flash memory having a large storage capacity. The nonvolatile memory device 1230 may provide a read voltage level higher than that of the fine sensing mode for the same data state in the partial page read mode. Through this setting, the nonvolatile memory device 1230 may provide high data reliability even in the partial page read mode. The nonvolatile memory device 1230 may be composed of a plurality of memory devices. In this case, each memory device is connected to the SSD controller 1210 on a channel-by-channel basis. Although the nonvolatile memory device 1230 has been described as a storage medium by way of example of a NAND flash memory, it may be composed of other nonvolatile memory devices. For example, PRAM, MRAM, ReRAM, FRAM, NOR flash memory, or the like may be used as a storage medium, and a memory system in which heterogeneous memory devices are mixed can be applied. The nonvolatile memory device may be configured substantially the same as that described in FIG. 1.

13 is a block diagram illustrating a memory system 2000 according to another embodiment of the inventive concept. Referring to FIG. 13, a memory system 2000 according to the present invention may include a memory controller 2200 and a nonvolatile memory 2100.

The nonvolatile memory 2100 may be configured to be substantially the same as the nonvolatile memory device 100 of FIG. 1. Therefore, a detailed description of the nonvolatile memory 2100 will be omitted. The nonvolatile memory device 1230 may provide a read voltage level higher than that of the fine sensing mode for the same data state in the partial page read mode. Through this setting, the nonvolatile memory device 1230 may provide high data reliability even in the partial page read mode.

The memory controller 2200 may be configured to control the non-volatile memory 2100. The SRAM 2230 can be used as a working memory of the CPU 2210. The host interface 2220 may have a data exchange protocol of the host connected to the memory system 2000. The error correction circuit 2240 provided in the memory controller 2200 can detect and correct an error included in the read data read from the nonvolatile memory 2100. The memory interface 2260 may interface with the nonvolatile memory 2100 of the present invention. The CPU 2210 can perform all control operations for data exchange of the memory controller 2200. [ Although not shown in the figure, the memory system 2000 according to the present invention may further be provided with a ROM (not shown) for storing code data for interfacing with a host.

The memory controller 2100 may be configured to communicate with an external (eg, host) via one of a variety of interface protocols such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI, and IDE, and the like. .

The memory controller 2100 decodes a read request from the host and selects one of a partial page read mode and a full page read mode. The memory controller 2100 may control the nonvolatile memory 2100 to access memory cells according to a corresponding read mode. For example, the memory controller 2100 may control the nonvolatile memory 2100 to set a specific read command (eg, a partial page read command) or a set feature.

The memory system 2000 according to the present invention may be implemented as a computer, a portable computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital camera, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, various user devices constituting a home network, &Lt; / RTI &gt;

14 is a block diagram illustrating a data storage device 3000 according to another exemplary embodiment. Referring to FIG. 14, the data storage device 3000 according to the present invention may include a flash memory 3100 and a flash controller 3200. The flash controller 3200 can control the flash memory 3100 based on control signals received from outside the data storage device 3000. [

In addition, the configuration of the flash memory 3100 is substantially the same as the nonvolatile memory device 100 shown in FIG. 1, and the flash memory of the present invention has a stack flash structure in which arrays are stacked in multiple layers, and a flash structure without source-drain. , Pin-type flash structure, and three-dimensional flash structure. The flash memory 3100 may provide a read voltage level higher than that of the fine sensing mode for the same data state in the partial page read mode. Through this setting, the flash memory 3100 may provide high data reliability even in the partial page read mode.

The flash controller 3200 decodes a read request from the host and selects one of a partial page read mode and a full page read mode. The flash controller 3200 may control the flash memory 3100 to access memory cells according to a corresponding read mode. For example, the flash controller 3100 may control the flash memory 3100 to set a specific read command (eg, a partial page read command) or a set feature.

The data storage device 3000 of the present invention can constitute a memory card device, an SSD device, a multimedia card device, an SD card, a memory stick device, a hard disk drive device, a hybrid drive device, or a universal serial bus flash device. For example, the data storage device 3000 of the present invention can configure a card that meets industry standards for using a user device such as a digital camera, a personal computer, and the like.

FIG. 15 is a diagram illustrating a schematic configuration of a flash memory device 4100 and a computing system 4000 including the same. 15, a computing system 4000 in accordance with the present invention includes a memory 4300 electrically coupled to a bus 4400, a memory controller 4200, a modem 4300 such as a baseband chipset, , A microprocessor 4500, and a user interface 4600. [

The configuration of the flash memory device 4100 shown in FIG. 15 is substantially the same as that of the nonvolatile memory device 100 shown in FIG. 1, and the flash memory of the present invention has a stack flash structure in which arrays are stacked in multiple layers. The drainless flash structure, the pin-type flash structure, and the three-dimensional flash structure can be configured.

The flash memory device 4100 may include a cell array formed of an all-bit line structure. In addition, the partial page reading mode may be additionally performed. In the partial page read mode, the flash memory device 4100 may be configured to ground an unselected bit line and perform only fine sensing on the selected bit line. The flash memory device 4100 may provide a read voltage level higher than that of the fine sensing mode for the same data state in the partial page read mode. Through this setting, the flash memory device 4100 may provide high data reliability even in the partial page read mode.

When the computing system according to the present invention is a mobile device, a battery 4700 for supplying the operating voltage of the computing system may additionally be provided. Although not shown in the drawing, an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further provided in the computing system according to the present invention. The memory controller 4200 and the flash memory device 4100 may configure, for example, an SSD (Solid State Drive / Disk) that uses a nonvolatile memory to store data.

The nonvolatile memory device and / or memory controller according to the present invention may be mounted using various types of packages. For example, the flash memory device and / or the memory controller according to the present invention can be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) Linear Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-Level Fabricated Package (WFP) WSP), and the like.

The embodiments have been disclosed in the drawings and specification as described above. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

110: cell array 120: row decoder
130: page buffer circuit 140: input and output buffer
150: control logic 160: voltage generator
210, 310: memory controller 220, 320: nonvolatile memory device
1100: Host 1200: SSD
1210: SSD controller 1220: buffer memory
1230 nonvolatile memory device 2100 flash memory
2200: memory controller 2210: CPU
2220: host interface 2230: SRAM
2240: ECC 2260: Memory Interface
3100: flash memory 3200: flash interface
4100: flash memory 4200: memory controller
4300: modem 4400: system bus
4500: Microprocessor 4600: User Interface
4700: Battery

Claims (10)

A memory cell array connected to a plurality of bit lines and a plurality of word lines;
A page buffer circuit configured to sense memory cells connected to a selected word line through the plurality of bit lines;
A voltage generator for providing a read voltage to the selected word line; And
Control logic to control the page buffer circuit and the voltage generator to sense memory cells connected to the selected word line in accordance with a first read mode or a second read mode,
The number of memory cells sensed simultaneously in the first read mode and the second read mode is different, and the voltage generator provides different read voltages for the same data state according to the number of sensed memory cells. The method of claim 1,
And in the first read mode, the voltage generator provides a first read voltage and a second read voltage higher than the first read voltage to the selected word line to identify any data state. 3. The method of claim 2,
And when the second read voltage is provided, the page buffer circuit selects and senses memory cells identified as off-cells by the first read voltage. 3. The method of claim 2,
And in the second read mode, the voltage generator generates a read voltage higher than the second read voltage to identify any one of the data states. The method of claim 1,
And the page buffer circuit grounds bit lines corresponding to an unselected column among memory cells connected to the selected word line in the second read mode. The method of claim 1,
The page buffer circuit,
And sensing memory cells corresponding to even and odd columns in the first read mode, and sensing memory cells corresponding to any one of even and odd columns in the second read mode. The method of claim 1,
The first read mode or the second read mode is selected by setting a read command or a set feature. A nonvolatile memory device having an all bit line structure; And
A memory controller configured to apply a full page read command or a partial page read command for the selected page to the nonvolatile memory device,
The nonvolatile memory device may generate different read voltages for the same data state according to the read command. The method of claim 8,
And a level of a read voltage generated by the nonvolatile memory device when the partial page read command is provided is higher than a level of a read voltage generated when the full page read command is provided for the same data state. The method of claim 8,
The nonvolatile memory device performs at least two sensing operations by different read voltages in order to identify a data state in response to the full page read command, and in response to the partial page read command. A memory system that performs one sensing operation with a single read voltage to identify a data state.
KR1020120000592A 2011-06-21 2012-01-03 Non-volatile memory device and memory system comprising the same KR20130079853A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020120000592A KR20130079853A (en) 2012-01-03 2012-01-03 Non-volatile memory device and memory system comprising the same
US13/527,641 US8861276B2 (en) 2011-06-21 2012-06-20 Nonvolatile memory device, memory system comprising same, and method of operating same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120000592A KR20130079853A (en) 2012-01-03 2012-01-03 Non-volatile memory device and memory system comprising the same

Publications (1)

Publication Number Publication Date
KR20130079853A true KR20130079853A (en) 2013-07-11

Family

ID=48992167

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020120000592A KR20130079853A (en) 2011-06-21 2012-01-03 Non-volatile memory device and memory system comprising the same

Country Status (1)

Country Link
KR (1) KR20130079853A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9524781B2 (en) 2013-12-11 2016-12-20 Samsung Electronics Co., Ltd. Nonvolatile memory device and operating method thereof
KR20170102659A (en) * 2016-03-02 2017-09-12 삼성전자주식회사 Non-volatile Memory Device including page buffer and Operating Method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9524781B2 (en) 2013-12-11 2016-12-20 Samsung Electronics Co., Ltd. Nonvolatile memory device and operating method thereof
KR20170102659A (en) * 2016-03-02 2017-09-12 삼성전자주식회사 Non-volatile Memory Device including page buffer and Operating Method thereof

Similar Documents

Publication Publication Date Title
KR101792870B1 (en) Non-volatile memory device and read method thereof
CN107093465B (en) Data storage device including voltage search unit
KR101891164B1 (en) Flash memory device including program scheduler
US8861276B2 (en) Nonvolatile memory device, memory system comprising same, and method of operating same
KR101686590B1 (en) Flash memory system and wl interleaving method thereof
KR101809202B1 (en) Non-volatile memory device and read method thereof
US8804422B2 (en) Nonvolatile memory device and related method of operation
KR101734204B1 (en) Flash memory device and system including program sequencer and program method thereof
US8990483B2 (en) Nonvolatile memory device, memory system, and program method therof
US8942046B2 (en) Method of programming a 3-dimensional nonvolatile memory device based on a program order of a selected page and a location of a string selection line
KR101810640B1 (en) Nonvolatile memory device and memory system and read method thereof
US9230659B2 (en) Nonvolatile memory device capable of reducing a setup/precharge speed of a bitline for reducing peak current and related programming method
KR102128825B1 (en) Non-volatile memory device and operation method thereof
KR102245822B1 (en) Storage device comprising non-volatile memory device and programing method thereof
US11681616B2 (en) Address scheduling methods for non-volatile memory devices with three-dimensional memory cell arrays
US9576668B2 (en) Semiconductor device and operating method thereof
US20130039130A1 (en) Program method of nonvolatile memory device
KR20130060795A (en) Nonvolatile memory device and operating method thereof
KR20130036851A (en) Memory system comprising a non-volatile memory device and operating method thereof
US20160104540A1 (en) Non-volatile memory device and operating method thereof
KR20110096414A (en) Nonvolatile memory device and read method thereof
KR20140011667A (en) Storage device comprising non-volatile memory chips and control method thereof
KR102157875B1 (en) Non-volatile memory device and memory system including the same
KR20160057186A (en) Semiconductor memory system and operating method thereof
KR20130079853A (en) Non-volatile memory device and memory system comprising the same

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination