KR20130072853A - Package and memory package - Google Patents

Package and memory package Download PDF

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Publication number
KR20130072853A
KR20130072853A KR1020110140458A KR20110140458A KR20130072853A KR 20130072853 A KR20130072853 A KR 20130072853A KR 1020110140458 A KR1020110140458 A KR 1020110140458A KR 20110140458 A KR20110140458 A KR 20110140458A KR 20130072853 A KR20130072853 A KR 20130072853A
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KR
South Korea
Prior art keywords
parallel
chip
package
communication interface
master chip
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KR1020110140458A
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Korean (ko)
Inventor
최준기
정충만
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에스케이하이닉스 주식회사
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Priority to KR1020110140458A priority Critical patent/KR20130072853A/en
Publication of KR20130072853A publication Critical patent/KR20130072853A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices

Abstract

PURPOSE: A package and a memory package thereof are provided to minimize the number of through silicone vias (TSVs), thereby securing stable communications between chips. CONSTITUTION: A master chip (100) communicates with the outside of a memory package. A slave chip (200) communicates with the master chip. The transmission channel is positioned between the master chip and the slave chip. A serial-parallel conversion unit (210) receives a serially arranged command, a serially arranged address, and a serially arranged data; and converts the serially arranged command, the serially arranged address, and the serially arranged data into an arranged command, an address arranged in parallel, and data arranged in parallel. A parallel-serial conversion unit (220) converts the arranged output data of the slave chip into serially arranged output data, and then transmits the serially arranged output data to a third communication interface. [Reference numerals] (110) Input unit; (140) Output unit; (210,130) Serial-parallel conversion unit; (220,120) Parallel-serial conversion unit; (230) Internal circuit

Description

Packages and Memory Packages {PACKAGE AND MEMORY PACKAGE}

The present invention relates to a package and a memory package composed of a plurality of chips.

Multi chip package (MCP) is a package chip composed of a plurality of chips, which can combine necessary memory according to application products and contributes to space efficiency of mobile devices such as mobile phones. There are a number of ways to manufacture the multi-chip package, one of which is a 3D stacking (3D stacking) method of stacking a plurality of chips in a vertical direction and using a plurality of TSV (Through Silicon Vias: TSV) Interconnect the chips. Since the multi-chip package by stacking in the three-dimensional stacking method does not need a metal wire for interconnecting the chips, the multi-chip package can be miniaturized, increased in speed, and reduced in power, thereby increasing demand.

have. However, when using TSV (Through Silicon Vias), a signal distortion occurs. The greater the number of through-silicon vias (TSVs), the higher the probability of distortion of the signal and the higher the defective rate of the package due to the inter-chip interconnection process. Hereinafter, an example of a package applied to a memory system will be described.

1 is a diagram illustrating a memory package including a plurality of stacked chips, in which the stacked plurality of chips are connected through a through silicon via (TSV).

The memory package may include a master chip 10 and a slave chip 20. The master chip 10 and the slave chip 20 are connected through through silicon vias (TSVs).

The master chip 10 is generally located at the bottom of the memory package and receives commands, addresses, data, etc. from a memory controller (not shown) and transfers the data to the slave chip 20 or transfers the output data of the slave chip 20 to the memory. Transfer to a controller (not shown).

The slave chip 20 stores or outputs data using commands and addresses transmitted through the master chip 10.

Meanwhile, FIG. 1 illustrates one through silicon via (CMD_TSV) for transmitting a command, one through silicon via for address transmission (ADD_TSV), and one through silicon via for transmitting data (DQ_TSV) for convenience of description. In this case, each of the address and data may be composed of a plurality of bits. In this case, a plurality of through silicon vias for transmitting a command (CMD_TSV), a plurality of through silicon vias for transmitting addresses (ADD_TSV), and a plurality of through silicon vias for transmitting data (DQ_TSV) ) Is required. As described above, when the through silicon vias TSV_CMD, TSV_ADD, and TSV_DQ are used, signal distortion may occur. As the number of through silicon vias TSV_CMD, TSV_ADD, TSV_DQ increases, the probability that the signal distortion occurs may be increased. The higher the probability of failure of a package.

The present invention is to solve the above-mentioned problems of the prior art, and provides a package capable of transmitting a signal to another chip while minimizing the number of through-silicon vias (TSVs).

The package according to an embodiment of the present invention, the master chip in communication with the outside; A slave chip in communication with the master chip; And a transmission channel between the master chip and the slave chip, wherein the master chip may perform parallel-serial conversion of signals input in parallel from the outside to the transmission channel.

In addition, the memory package according to an embodiment of the present invention, the master chip in communication with the outside; A slave chip in communication with the master chip; And a transmission channel between the master chip and the slave chip, wherein the master chip may perform parallel-serial conversion of commands, addresses, and data input in parallel from the outside to the transmission channel.

According to an exemplary embodiment of the present invention, the number of through silicon vias (TSVs) is minimized to ensure stable communication between chips and to reduce a defective rate of a package due to the chip-to-chip connection process.

1 illustrates a package including stacked multiple chips, wherein the stacked multiple chips are connected through through silicon vias.
2 illustrates a memory package according to an embodiment of the present invention.
FIG. 3 is a flowchart illustrating a process of transmitting a signal (command, address, data) from a master chip 100 of the memory package shown in FIG. 2 to a slave chip 200.
FIG. 4 is a flowchart illustrating a process of transmitting output data of the slave chip 200 from the slave chip 200 of the memory package shown in FIG. 2 to the master chip 100.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

2 is a diagram illustrating a memory package according to an exemplary embodiment of the present invention.

The memory package may include a master chip 100 and a slave chip 200.

The master chip 100 communicates with the outside of the memory package (eg, a controller (not shown)). In detail, the master chip 100 may include an input unit 110, a parallel-to-serial converter 120, a serial-to-parallel converter 130, an output unit 140, a plurality of first communication interfaces CMD_CH1A, and a plurality of first It may include a two communication interface (ADD_CH1A), a plurality of third communication interface (DQ_CH1A, DQ_CH2A). 2 illustrates a case in which the master chip 100 includes one first communication interface CMD_CH1A, one second communication interface ADD_CH1A, and two third communication interfaces DQ_CH1A and DQ_CH2A. Illustrated.

The input unit 110 receives the commands CMD1 and CMD2 composed of a plurality of bits, the addresses ADD1 and ADD2 composed of a plurality of bits, and the data DQ1 and DQ2 composed of a plurality of bits in parallel from the outside of the memory package. In FIG. 2, for convenience of description, the input unit 110 includes commands CMD1 and CMD2 composed of two bits, addresses ADD1 and ADD2 composed of two bits, and data DQ1 and DQ2 composed of two bits. The case of receiving input from the above is illustrated. In detail, the input unit 110 receives a command consisting of two bits CMD1 and CMD2 from the outside of the memory package in synchronization with the first clock CLK1 and transmits the same to the parallel-serial converter 120. As a result, each of the first command bit CMD1 and the second command bit CMD2 is mounted on each of the first-first node ND1-1 and the first-second node ND1-2, and aligned in parallel. The input unit 110 receives the addresses ADD1 and ADD2 composed of two bits from the outside of the memory package in synchronization with the first clock CLK1 and transfers them to the parallel-serial converter 120. As a result, each of the first address bit ADD1 and the second address bit ADD2 is mounted on each of the first to third nodes ND1-3 and ND1-4 and arranged in parallel. The input unit 110 receives data DQ1 and DQ2 composed of two bits from the outside of the memory package in synchronization with the first clock CLK1 and transmits the data to the parallel-serial converter 120. As a result, each of the first data bit DQ1 and the second data bit DQ2 is mounted on the first-5 node ND1-5 and the first-6 node ND1-6 and aligned in parallel.

The parallel-to-serial converter 120 converts the commands CMD1 and CMD2 arranged in parallel, the addresses ADD1 and ADD2 arranged in parallel, and the data DQ1 and DQ2 arranged in parallel to serially convert the first through the first through the same. Transmission is performed on each of the third communication interfaces CMD_CH1A, ADD_CH1A, and DQ_CH1A. In detail, the parallel-serial converter 120 arranges the commands CMD1 and CMD2 arranged in parallel in series in synchronization with the second clock CLK2 and transmits the serial commands to the first communication interface CMD_CH1A. Here, the second clock CLK2 is a signal whose frequency is M times the frequency of the first clock CLK1 (wherein M is an integer of 1 or more). Hereinafter, for convenience of description, a case where the frequency of the second clock CLK2 is twice the frequency of the first clock CLK1 will be described as an example. As a result, the first command bit CMD1 and the second command bit CMD2 are serially loaded on the second node ND2-3, and the commands CMD1, which are serially aligned with the first communication interface CMD_CH1A, are displayed. CMD2) is transmitted. The parallel-to-serial converter 120 arranges the addresses ADD1 and ADD2 arranged in parallel in series in synchronization with the second clock CLK2 and transmits the serially aligned addresses ADD_CH1A to the second communication interface ADD_CH1A. As a result, the first address bit ADD1 and the second address bit ADD2 are serially loaded on the second node ND2-2, and the addresses ADD1, serially aligned with the second communication interface ADD_CH1A, are provided. ADD2) is transmitted. The parallel-to-serial converter 120 arranges the data DQ1 and DQ2 arranged in parallel and serially synchronizes the data DQ1 and DQ2 to the third communication interface DQ_CH1A. As a result, the first data bit DQ1 and the second data bit DQ2 are loaded in series in the second-first node ND2-1, and the data DQ1, which are serially aligned in the third communication interface DQ_CH1A, are loaded. DQ2) is transmitted.

The first communication interface CMD_CH1A transmits serially aligned commands CMD1 and CMD2 to the slave chip 200. In detail, the first communication interface CMD_CH1A transmits serially aligned commands CMD1 and CMD2 to the first communication interface CMD_CH1B of the slave chip 200, and the first communication interface CMD_CH1A of the master chip 100. ) And each of the first communication interface CMD_CH1B of the slave chip 200 may be designed as a wired communication interface. In this case, the commands CMD1 and CMD2 aligned in series may be used as the first communication interface (CMD_CH1B) of the master chip 100. It is transmitted from the CMD_CH1A to the first communication interface CMD_CH1B of the slave chip 200 by wire. In addition, each of the first communication interface CMD_CH1A and the first communication interface CMD_CH1B of the master chip 100 may be designed as a wireless communication interface such as a wireless antenna, and in this case, the commands CMD1 and CMD2 serially aligned. Is wirelessly transmitted from the first communication interface CMD_CH1A of the master chip 100 to the first communication interface CMD_CH1B of the slave chip 200.

The second communication interface ADD_CH1A transmits serially aligned addresses ADD1 and ADD2 to the slave chip 200. In detail, the second communication interface ADD_CH1A transmits serially aligned addresses ADD1 and ADD2 to the second communication interface ADD_CH1B of the slave chip 200. The second communication interfaces ADD_CH1A and ADD_CH1B are wired communication. In this case, the serially aligned addresses ADD1 and ADD2 are transmitted by wire from the second communication interface ADD_CH1A of the master chip 100 to the second communication interface ADD_CH1B of the slave chip 200. do. Also, the second communication interfaces ADD_CH1A and ADD_CH1B may be designed as a wireless communication interface such as a wireless antenna. In this case, the serially aligned addresses ADD1 and ADD2 may correspond to the second communication interface ADD_CH1A of the master chip 100. ) Is wirelessly transmitted to the second communication interface ADD_CH1B of the slave chip 200.

The third communication interface DQ_CH1A and DQ_CH2A transmits serially aligned data DQ1 and DQ2 to the slave chip 200 or receives output data of the serially aligned slave chip 200 from the slave chip 200. . In FIG. 2, for convenience of description, the data DQ1 and DQ2 having the third communication interface DQ_CH1A arranged in series are transmitted to the third communication interface DQ_CH1B of the slave chip 200, and the third communication interface ( The case where the DQ_CH2A receives output data of the serially arranged slave chips 200 from the third communication interface DQ_CH2B of the slave chip 200 is illustrated. Meanwhile, the third communication interfaces DQ_CH1A, DQ_CH1B, DQ_CH2A, and DQ_CH2B may be designed as wired communication interfaces, and in this case, the serially aligned data DQ1 and DQ2 may be the third communication interface DQ_CH1A of the master chip 100. Is transmitted to the third communication interface DQ_CH1B of the slave chip 200 by wire, and the output data of the serially aligned slave chip 200 is transferred from the third communication interface DQ_CH2B of the slave chip 200 to the master chip ( 100 is transmitted to the third communication interface DQ_CH2A by wire. In addition, the third communication interface DQ_CH1A, DQ_CH1B, DQ_CH2A, DQ_CH2B may be designed as a wireless communication interface such as a wireless antenna, and in this case, the serially aligned data DQ1 and DQ2 may be used as the third communication of the master chip 100. The output data of the slave chip 200 which is wirelessly transmitted from the interface DQ_CH1A to the third communication interface DQ_CH1B of the slave chip 200 and serially aligned is output to the third communication interface DQ_CH2B of the slave chip 200. Is transmitted wirelessly to the third communication interface DQ_CH2A of the master chip 100.

The serial-parallel converter 130 receives output data of the serially arranged slave chips 200 from the third communication interface DQ_CH2A and converts the output data in parallel. For example, if the output data of the slave chip 200 aligned in series with the seventh node ND7 includes two bits, the serial-to-parallel conversion unit 130 of the slave chip 200 aligned in series is provided. One bit of the output data is loaded on the eighth-node ND8-1, and the remaining one bit is loaded on the eighth-node ND8-2, so that the output of the slave chips 200 aligned in series. It can be designed to convert data in parallel.

The output unit 140 outputs the output data of the slave chips 200 arranged in parallel by the serial-parallel conversion unit 130 to the outside of the memory package.

The slave chip 200 communicates with the master chip 100. In detail, the slave chip 200 includes a plurality of first communication interfaces CMD_CH1B, a plurality of second communication interfaces ADD_CH1B, a plurality of third communication interfaces DQ_CH1B, DQ_CH2B, a parallel-to-parallel converter 210, It may include a serial converter 220 and the internal circuit 230. In FIG. 2, for convenience of description, the slave chip 200 includes one first communication interface CMD_CH1B, one second communication interface ADD_CH1B, and two third communication interfaces DQ_CH1B and DQ_CH2B. Illustrated.

The first communication interface CMD_CH1B receives serially aligned commands CMD1 and CMD2 from the first communication interface CMD_CH1A of the master chip 100, and transmits the commands CMD1 and CMD2 to the serial-to-parallel converter 210. As described above, the first communication interface CMD_CH1B may be designed as a wired communication interface to transmit a signal by wire. In addition, the first communication interface CMD_CH1B may be designed as a wireless communication interface such as a wireless antenna to transmit a signal wirelessly.

The second communication interface ADD_CH1B receives serially aligned addresses ADD1 and ADD2 from the second communication interface ADD_CH1A of the master chip 100, and transmits the addresses ADD1 and ADD2 to the serial-to-parallel converter 210. As described above, the second communication interface ADD_CH1B may be designed as a wired communication interface to transmit a signal by wire. In addition, the second communication interface ADD_CH1B may be designed as a wireless communication interface such as a wireless antenna to transmit a signal wirelessly.

The third communication interfaces DQ_CH1B and DQ_CH2B receive serially aligned data DQ1 and DQ2 from the third communication interface DQ_CH1A of the master chip 100, or output data of the serially aligned slave chips 200. To the third communication interface DQ_CH2A of the master chip 100. In detail, the third communication interface DQ_CH1B receives serially aligned data DQ1 and DQ2 from the third communication interface DQ_CH1A of the master chip 100 and transmits the data DQ1 and DQ2 to the serial-to-parallel converter 210. The third communication interface DQ_CH2B transmits output data of the slave chip 200 arranged in series by the parallel-serial conversion unit 220 to the third communication interface DQ_CH2A of the master chip 100. As described above, the third communication interfaces DQ_CH1B and DQ_CH2B may be designed as wired communication interfaces to transmit signals by wires. In addition, the third communication interfaces DQ_CH1B and DQ_CH2B may be designed as a wireless communication interface such as a wireless antenna to transmit a signal wirelessly.

The serial-to-parallel conversion unit 210 serially arranges commands CMD1 and CMD2 and serially aligned addresses from the first communication interface CMD_CH1B, the second communication interface ADD_CH1B, and the third communication interface DQ_CH1B. (ADD1, ADD2) and serially aligned data (DQ1, DQ2) are input and converted in parallel. In detail, the serial-to-parallel converter 210 converts the commands CMD1 and CMD2 arranged in series in parallel so that the first command bit CMD1 is loaded on the 4-1 node ND4-1, and the second command bit. The CMD2 may be designed to be mounted on the fourth-2 node ND4-2. The serial-to-parallel converter 210 converts the serially aligned addresses ADD1 and ADD2 in parallel so that the first address bit ADD1 is loaded on the fourth-3 node ND4-3 and the second address bit ( ADD2) may be designed to be mounted on the fourth-4 node ND4-4. The serial-to-parallel converter 210 converts the serially aligned data DQ1 and DQ2 in parallel so that the first data bit DQ1 is loaded on the fourth-5 node ND4-5 and the second data bit ( DQ2) may be designed to be mounted on the fourth to sixth nodes ND4-6.

The internal circuit 230 includes commands CMD1 and CMD2, addresses ADD1 and ADD2, and data DQ1 and DQ2 arranged in parallel to the 4-1 to 4-6 nodes ND4-1 to ND4-6. Takes input and performs a specific action.

The parallel-serial converter 220 converts the output data of the slave chips 200 arranged in parallel and serially and transmits them to the third communication interface DQ_CH2B. The output data of the slave chip 200 is data output from the internal circuit 230 of the slave chip 200 and is a signal output to the outside of the memory package through the master chip 100. In more detail, the parallel-serial converter 220 arranges the output data of the slave chips 200 input in parallel and serially synchronizes the output data of the slave chips 200 to the third communication interface DQ_CH2B. As a result, output data of the serially arranged slave chips 200 is loaded on the sixth node ND6, and output data of the serially arranged slave chips 200 is transmitted to the third communication interface DQ_CH2B.

3 is a flowchart illustrating a process of transmitting a signal (command, address, data) from the master chip 100 of the memory package shown in FIG. 2 to the slave chip 200.

The input unit 110 of the master chip 100 is a command (CMD1, CMD2) consisting of two bits, an address (ADD1, ADD2) consisting of two bits and two bits in synchronization with the first clock CLK1. The configured data DQ1 and DQ2 are received in parallel (S10). Accordingly, the two-bit commands CMD1 and CMD2 are loaded in parallel in the first-first node ND1-1 and the first-second node ND1-2, and the first-three node ND1-3 And the first to fourth nodes ND1-4 are loaded with two bits of addresses ADD1 and ADD2 in parallel, and the first to fifth nodes ND1-5 and the first to sixth nodes ND1-6. The data DQ1 and DQ2 composed of two bits are loaded in parallel (S10).

The parallel-to-serial converter 120 synchronizes the commands CMD1 and CMD2 arranged in parallel, the addresses ADD1 and ADD2 arranged in parallel, and the data DQ1 and DQ2 arranged in parallel to the second clock CLK2. The solution is converted to serial (S20). Therefore, the first command bit CMD1 and the second command bit CMD2 are loaded in series on the second node ND2-3, and the first address bit is loaded on the second node ND2-2. The ADD1 and the second address bit ADD2 are loaded in series, and the first data bit DQ1 and the second data bit DQ2 are loaded in series in the second-first node ND2-1. (S20).

The serially aligned commands CMD1 and CMD2 are transmitted to the first communication interface CMD_CH1B of the slave chip 200 through the first communication interface CMD_CH1A. The serially aligned addresses ADD1 and ADD2 are transmitted to the second communication interface ADD_CH1B of the slave chip 200 through the second communication interface ADD_CH1A. The serially aligned data DQ1 and DQ2 are transmitted to the third communication interface DQ_CH1B of the slave chip 200 through the third communication interface DQ_CH1A (S30).

Serially aligned commands CMD1 and CMD2 input to the first communication interface CMD_CH1B of the slave chip 200, and serially aligned addresses ADD1 input to the second communication interface ADD_CH1B of the slave chip 200. , ADD2, and serially aligned data DQ1 and DQ2 input to the third communication interface DQ_CH1B of the slave chip 200 are transferred to the serial-to-parallel converter 210. The serial-parallel conversion unit 210 converts the commands CMD1 and CMD2 that are serially aligned, the addresses ADD1 and ADD2 that are serially aligned, and the data DQ1 and DQ2 that are serially aligned in parallel (S40). Accordingly, the first command bit and the second command bit CMD1 and CMD2 are loaded in parallel in the 4-1 node ND4-1 and the 4-2 node ND4-2, and the 4-3 node. The first and second address bits ADD1 and ADD2 are loaded in parallel to the ND4-3 and the fourth-4 node ND4-4, and the fourth and fifth nodes ND4-5 and the fourth and fourth node. The sixth node ND4-6 carries the first and second data bits DQ1 and DQ2 in parallel (S40).

Commands CMD1 and CMD2 arranged in parallel, addresses ADD1 and ADD2 arranged in parallel, and data DQ1 and DQ2 arranged in parallel are input to the internal circuit 230 (S50). The internal circuit 230 performs a specific operation using the input commands CMD1 and CMD2, the addresses ADD1 and ADD2 and the data DQ1 and DQ2.

As a result, when the signals (commands CMD1 and CMD2, addresses ADD1 and ADD2, and data DQ1 and DQ2) input in parallel from the outside of the memory package are transmitted from the master chip 100 to the slave chip 200. For example, if the signals are transmitted to the slave chip 200 in parallel, six communication interfaces are required, but according to an embodiment of the present invention, three communication interfaces CMD_CH1A, ADD_CH1A, and DQ_CH1A are required. When the communication interface is designed to include through silicon vias (TSVs), according to an embodiment of the present invention, the number of through silicon vias (TSVs) can be minimized to ensure stable communication between chips and a connection process between chips. This can reduce the defective rate of the package.

4 is a flowchart illustrating a process of transmitting output data of the slave chip 200 from the slave chip 200 of the memory package shown in FIG. 2 to the master chip 100.

The parallel-to-serial conversion unit 220 of the slave chip 200 aligns the output data of the slave chip 200 input in parallel from the internal circuit 230 in series in synchronization with the second clock CLK2 (S70). . Therefore, the output data of the slave chips 200 arranged in series is loaded on the sixth node ND6 (S70).

Output data of the serially aligned slave chip 200 is transmitted to the third communication interface DQ_CH2A of the master chip 100 through the third communication interface DQ_CH2B (S80).

Output data of the serially aligned slave chip 100 input to the third communication interface DQ_CH1B of the master chip 100 is transferred to the serial-to-parallel converter 130. The serial-parallel conversion unit 130 converts the output data of the serially aligned slave chips 100 in parallel (S85). Therefore, the output data of the slave chip 100 is loaded in parallel to the 8-1nd node ND8-1 and the 8-2nd node ND8-2 (S85).

The output unit 140 outputs the output data of the slave chip 100 loaded on the eighth-node ND8-1 and the eighth-node ND8-2 to the outside (S90).

As a result, according to the embodiment of the present invention, since the output data of the slave chip 200 are serially converted and transmitted to the master chip 100, the output data of the slave chip 200 is transmitted to the master chip 100 in parallel. The number of communication interfaces DQ_CH2B and DQ_CH2A can be reduced. When the communication interface is designed to include through silicon vias (TSVs), according to an embodiment of the present invention, the number of through silicon vias (TSVs) can be minimized to ensure stable communication between chips and a connection process between chips. This can reduce the defective rate of the package.

Meanwhile, in FIG. 2, for convenience of description, the memory package according to the present invention includes commands CMD1 and CMD2 composed of two bits, addresses ADD1 and ADD2 composed of two bits, and data DQ1 and DQ2 composed of two bits. Although the case of inputting in parallel from the outside of the memory package has been exemplified, this is only an example, and the memory package according to the present invention includes a command consisting of A bits (where A is an integer greater than or equal to 1), and B (where B is greater than or equal to 1). It can be designed to receive data composed of an address consisting of bits) and C bits (where C is an integer of 1 or more) in parallel from the outside of the memory package.

Meanwhile, for the convenience of description, the case where the frequency of the second clock CLK2 used in the parallel-to-serial converter 120 and 220 is twice the frequency of the first clock CLK1 has been described. The frequency of the second clock CLK2 may be M times the frequency of the first clock CLK1. In this case, the M signals are aligned in series on the same line by the parallel-to-serial converters 120 and 220. For example, the second clock CLK2 including six bits of the commands CMD1 to CMD6 is input in parallel from the outside of the memory package in synchronization with the first clock CLK1 and used by the parallel-serial converter 120. If the frequency of is equal to four times the frequency of the first clock CLK1, the first to fourth command bits CMD1 to CMD4 are connected to the same line (hereinafter, 'first line') by the parallel-to-serial converter 120. It is serially aligned and sent to the slave chip 200 via a communication interface corresponding to the first line. The remaining fifth and sixth command bits CMD5 to CMD6 are serially aligned on the same line (hereinafter, referred to as 'second line') and transmitted to the slave chip 200 through a communication interface corresponding to the second line.

Meanwhile, FIG. 2 illustrates a case in which the package according to the present invention is applied to a memory system, but this is only an example and the package according to the present invention may be used in various types of integrated circuit systems as well as the memory system.

The package according to the present invention described above is as follows. The package according to the present invention may include a master chip 100 communicating with the outside of the package, a slave chip 200 communicating with the master chip 100, and a signal transmission channel between the master chip 100 and the slave chip 200. Can be. The master chip 100 performs parallel-serial conversion of signals input in parallel from the outside of the package and transfers them to the signal transmission channel. The signal transmission channel may be designed to transmit the serially aligned signal to the slave chip 200 by wire or wirelessly to the slave chip 200. The slave chip 200 internally converts the serially aligned signals received through the signal transmission channel in parallel. On the other hand, when the slave chip 200 transmits its output data to the outside of the package, the slave chip 200 converts its output data arranged in parallel to the signal transmission channel and transmits the output data to the signal transmission channel. 100 receives the output data of the serially arranged slave chip 200 through the signal transmission channel.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

100: master chip 200: slave chip
110: input unit 120: bottle-serial conversion unit
130: serial-parallel conversion unit 140: output unit
210: serial-parallel conversion unit 230: internal circuit
220: bottle-serial converter

Claims (10)

A master chip in communication with the outside;
A slave chip in communication with the master chip; And
A transmission channel between the master chip and the slave chip,
The master chip performs parallel-serial conversion of signals input in parallel from the outside to be transmitted to the transmission channel.
package.
The method of claim 1,
The slave chip converts the serially aligned signals received through the transmission channel in parallel.
package.
The method of claim 1,
The transmission channel transmits a serially aligned signal received from the master chip to the slave chip by wire.
package. The method of claim 1,
The transmission channel wirelessly transmits a serially aligned signal received from the master chip to the slave chip.
package.
The method of claim 1,
Signals input in parallel from the outside of the package are signals arranged in N signal lines in synchronization with the first clock, where N is an integer of 2 or more,
The master chip aligns the signals arranged on the N signal lines in series in synchronization with a second clock whose frequency is M times the first clock, where M is an integer of 1 or more, and outputs the serially aligned signals. Transmitted on the transmission channel
package.
A master chip in communication with the outside;
A slave chip in communication with the master chip; And
A transmission channel between the master chip and the slave chip,
The master chip performs parallel-serial conversion of commands, addresses, and data input in parallel from the outside to be transmitted to the transmission channel.
Memory package.
The method according to claim 6,
The transmission channel transmits serially aligned commands, addresses, and data received from the master chip to the slave chip by wire.
Memory package.
The method according to claim 6,
The transmission channel wirelessly transmits serially aligned commands, addresses, and data received from the master chip to the slave chip.
Memory package.
The method according to claim 6,
The slave chip
Converting serially aligned addresses, commands, and data received through the transmission channel in parallel
Memory package.
The method according to claim 6,
The slave chip performs parallel-serial conversion of its output data arranged in parallel and transmits the same to the transmission channel.
Memory package.
KR1020110140458A 2011-12-22 2011-12-22 Package and memory package KR20130072853A (en)

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