KR20130072061A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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Publication number
KR20130072061A
KR20130072061A KR1020110139608A KR20110139608A KR20130072061A KR 20130072061 A KR20130072061 A KR 20130072061A KR 1020110139608 A KR1020110139608 A KR 1020110139608A KR 20110139608 A KR20110139608 A KR 20110139608A KR 20130072061 A KR20130072061 A KR 20130072061A
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KR
South Korea
Prior art keywords
clock
enable signal
common output
signal
outputting
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Application number
KR1020110139608A
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Korean (ko)
Inventor
심종주
변상연
장동욱
김재헌
Original Assignee
에스케이하이닉스 주식회사
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Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110139608A priority Critical patent/KR20130072061A/en
Publication of KR20130072061A publication Critical patent/KR20130072061A/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

A semiconductor integrated circuit using a multi-phase clock signal, the method comprising: an enable signal generator configured to delay a common output control signal by a predetermined period to generate a common output enable signal; And a plurality of clock alignment units for outputting a plurality of differential clock signals having different phases in phase order in response to the common output enable signal, wherein each of the plurality of clock alignment units respectively outputs a common output enable signal. A synchronization unit for outputting in synchronization with any one of the differential clock signals; And an output control unit for outputting each differential clock signal in response to the common output enable signal output from the synchronization unit.

Description

[0001] SEMICONDUCTOR INTEGRATED CIRCUIT [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly to semiconductor integrated circuits, and more particularly, to semiconductor integrated circuits using multi-phase clock signals.

In general, a high speed clock signal is required for a computer, various communication systems, electronic communication devices, and the like to transmit and receive data at high speed. However, data transmission and reception using a high-speed clock signal has a problem of lowering electromagnetic interference (EMI) characteristics of a communication system. Therefore, in recent years, data is transmitted using a clock signal slower than a high speed clock signal, and a high speed clock signal is generated again using a phase locked loop (PLL) when the received data is restored, or By generating a multi-phase clock signal using a delay / phase locked loop (D / PLL) for a data transmission system of the present invention, a method of synchronizing a clock signal with received data and restoring data is used. have.

On the other hand, Figure 1 is a block diagram showing a circuit for the limited transfer of the multi-phase clock signal.

Referring to FIG. 1, the semiconductor integrated circuit 10 may include first to fourth differential clock signals IN000 / IN180, IN045 / IN225, IN090 / IN270, and IN135 that have different phases in response to the common output control signal ENIN. And first to fourth clock output units 11, 13, 15, and 17 for outputting IN315. Here, the common output control signal ENIN is an asynchronous signal, and the first to fourth differential clock signals IN000 / IN180, IN045 / IN225, IN090 / IN270, and IN135 / IN315 are clock generation circuits (eg, DLL, PLL, etc.). Is a multi-phase clock signal.

2 illustrates an internal configuration of the first clock output unit 11 illustrated in FIG. 1. Here, since the first to fourth clock output units 11 all have the same internal configuration, only the first clock output unit 11 will be representatively described below for convenience of description.

Referring to FIG. 2, the first clock output unit 11 may include a first positive clock signal IN000 input through the first positive input terminal IN and a common output control signal input through the first input terminal EN. A first NAND gate NAND1 for performing an AND logic operation on the ENIN, a first inverter INV1 for inverting the output of the first NAND gate NAND1, and outputting the same through the first positive output terminal OUT; The second NAND gate NAND2 for performing a negative AND operation on the common output control signal ENIN input through the first input terminal EN and the first sub clock signal IN180 input through the first sub input terminal INB. ) And a second inverter INV2 for inverting the output of the second NAND gate NAND2 and outputting the same through the first sub output terminal OUTB. The first clock output unit 11 configured as described above outputs the first differential clock signals IN000 / IN180 from a time point when the common output control signal ENIN is activated at a logic high level.

Hereinafter, the operation of the semiconductor integrated circuit 10 configured as described above will be described with reference to FIG. 2.

3 is a timing diagram illustrating the operation of the semiconductor integrated circuit 10 according to the related art.

Referring to FIG. 3, the first to fourth clock output units 11, 13, 15, and 17 may collectively answer the first to fourth differential clock signals OUT000 / OUT180, in response to the common output control signal ENIN. OUT045 / OUT225, OUT090 / OUT270, OUT135 / OUT315) are output. That is, the first to fourth clock output units 11, 13, 15, and 17 may output the first to fourth differential clock signals OUT000 / OUT180 and OUT045 only when the common output control signal ENIN is activated to a logic high level. / OUT225, OUT090 / OUT270, OUT135 / OUT315) are output.

However, the semiconductor integrated circuit 10 according to the related art glitch when outputting the first to fourth differential clock signals OUT000 / OUT180, OUT045 / OUT225, OUT090 / OUT270, and OUT135 / OUT315 having different phases. ) Occurs frequently. 3, the second to fourth differential clock signals CLK045 / CLK225, CLK090 / CLK270, among the first to fourth differential clock signals OUT000 / OUT180, OUT045 / OUT225, OUT090 / OUT270, and OUT135 / OUT315, respectively. CLK135 / CLK315) shows that glitches occur in the initial output period. This is because the output timing is collectively determined by the common output control signal ENIN. In this case, circuits using the first to fourth differential clock signals OUT000 / OUT180, OUT045 / OUT225, OUT090 / OUT270, and OUT135 / OUT315 may malfunction due to glitches. In addition, since the start phase is not sequentially when the first to fourth differential clock signals OUT000 / OUT180, OUT045 / OUT225, OUT090 / OUT270, and OUT135 / OUT315 are output due to the generated glitch, the first to fourth differential clock signals Phase information is lost in a system using (OUT000 / OUT180, OUT045 / OUT225, OUT090 / OUT270, OUT135 / OUT315) at the same time, resulting in a problem that cannot guarantee normal system operation.

The present invention provides a semiconductor integrated circuit for outputting a multi-phase clock signal in phase order.

According to an aspect of the present invention, the present invention provides a semiconductor integrated circuit including a clock phase alignment circuit for sequentially aligning a plurality of clock signals having different phases, wherein the clock phase alignment circuit is configured to a common output enable signal. In response, each of the plurality of clock signals is output in a phase order from a predetermined interval.

According to another aspect of the invention, the present invention includes an enable signal generation unit for generating a common output enable signal by delaying the common output control signal by a predetermined period; And a plurality of clock alignment units for outputting a plurality of clock signals having different phases in phase order in response to the common output enable signal, wherein each of the plurality of clock alignment units includes a common output enable signal for each clock. A synchronization unit for outputting in synchronization with the signal; And an output control unit for outputting each clock signal in response to the common output enable signal output from the synchronization unit.

According to another aspect of the invention, the present invention includes an enable signal generation unit for generating a common output enable signal by delaying the common output control signal by a predetermined period; And a plurality of clock alignment units for outputting a plurality of differential clock signals having different phases in phase order in response to the common output enable signal, wherein each of the plurality of clock alignment units respectively outputs a common output enable signal. A synchronization unit for outputting in synchronization with any one of the differential clock signals; And an output controller for outputting respective differential clock signals in response to the common output enable signal output from the synchronization unit.

By controlling the multi-phase clock signal to be output in the order of phase after the predetermined interval, it is possible to prevent the malfunction of the system using the multi-phase clock signal and to use the phase information of the multi-phase clock signal without loss. It also has the effect of contributing to improved performance.

1 is a block diagram of a semiconductor integrated circuit according to the prior art.
FIG. 2 is a diagram illustrating an internal configuration of the first clock output unit illustrated in FIG. 1.
3 is a timing diagram illustrating an operation of a semiconductor integrated circuit according to the related art.
4 is a block diagram illustrating a semiconductor integrated circuit in accordance with an embodiment of the present invention.
5 is a diagram illustrating an internal configuration of the enable signal generator shown in FIG. 4.
FIG. 6 is a diagram illustrating an internal configuration of the first clock alignment unit illustrated in FIG. 4.
7 is a timing diagram illustrating an operation of a semiconductor integrated circuit according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

2 is a block diagram illustrating a semiconductor integrated circuit in accordance with an embodiment of the present invention.

Referring to FIG. 2, the semiconductor integrated circuit 100 may have a different phase from an enable signal generator 110 for generating a common output enable signal by delaying the common output control signal ENIN by a predetermined period. The first to fourth differential clock signals IN000 / IN180, IN045 / IN225, IN090 / IN270, and IN135 / IN315 are sequentially aligned, but in response to the common output enable signal ENABLE, the first to fourth differential clock signals And a clock phase alignment circuit 120 for outputting OUT000 / OUT180, OUT045 / OUT225, OUT090 / OUT270, and OUT135 / OUT315 in phase order from a predetermined interval.

Here, the clock phase alignment circuit 120 may include first to fourth differential clock signals OUT000 / OUT180, OUT045 / OUT225, OUT090 / OUT270, and OUT135 / OUT315 having different phases in response to the common output enable signal ENABLE. ) Are first to fourth clock alignment units 121, 123, 125, and 127 for outputting the phases in order of phase.

3 is a diagram illustrating an internal configuration of the enable signal generator 110.

Referring to FIG. 3, the enable signal generator 110 may include a frequency of an internal clock signal CLK—the first to fourth differential clock signals IN000 / IN180, IN045 / IN225, IN090 / IN270, and IN135 / IN315. Shifting unit (DFF1, DFF2, DFF3, DFF4) for shifting the common output control signal (ENIN) a predetermined number of times and outputting it as a common output enable signal (ENABLE) in response to the same clock signal or a divided clock signal. It includes. In other words, the enable signal generation unit 110 generates a common output enable signal ENABLE by synchronizing the common output control signal ENIN, which is an asynchronous signal, with the internal clock signal CLK, but generates a common output enable signal ( First to fourth D-flip flops DFF1, DFF2, DFF3, and DFF4 for delaying and outputting the ENABLE by a predetermined period. In this case, the predetermined section may be changed according to the design, and accordingly, the number of D-flip flops may also be changed.

In addition, FIG. 4 illustrates an internal configuration of the first clock alignment unit 121 included in the clock phase alignment circuit 120. Hereinafter, since the first to fourth clock alignment units 121, 123, 125, and 127 are all configured in the same manner, only the first clock alignment unit 121 is representatively described for convenience of description.

Referring to FIG. 4, the first clock alignment unit 121 is configured to output the common output enable signal ENABLE in synchronization with the first positive clock signal IN000 input through the first positive input terminal IN. An output control unit 121B for outputting the first differential clock signal OUT000 / OUT180 in response to the first synchronization unit 121A and the first common output enable signal QENABLE1 synchronized by the first synchronization unit 121A. ).

Here, the first synchronization unit 121A may include the first inverter INV1 and the first inverter INV1 for inverting and outputting the first positive clock signal IN000 input through the first positive input terminal IN. And a fifth D-flip flop DFF5 for outputting a first common output enable signal QENABLE1 in synchronization with the output.

In addition, the first output control unit 121B may perform a first NAND operation on the logical AND operation of the synchronized common output enable signal ENABLE and the first positive clock signal IN000 input through the first positive input terminal IN. A second inverter INV2 for outputting the first positive clock signal OUT000 from which glitches are removed through the first positive output terminal OUT by inverting the output of the gate NAND1 and the first NAND gate; , The third inverter INV3 for inverting and outputting the synchronized common output enable signal ENABLE, the first sub-clock signal input through the output of the third inverter INV3 and the first sub-input terminal INB. The first NOR gate signal NOR1 for negating the OR 180 and the first sub clock signal OUT180 in which the glitch is removed through the first sub output terminal OUTB by inverting the output of the first NOR gate NOR1. ) And a fourth inverter (INV4) for outputting.

Hereinafter, an operation of the semiconductor integrated circuit 100 according to the embodiment of the present invention having the above configuration will be described with reference to FIG. 5.

5 is a timing diagram illustrating the operation of the semiconductor integrated circuit 100 according to an embodiment of the present invention.

Referring to FIG. 5, when the common output control signal ENIN is activated to a logic high level, the enable signal generator 110 is an internal clock signal CLK and an internal clock signal CLK output enable signal ENABLE. Output At this time, the enable signal generator 110 delays the interval corresponding to one cycle (1tCK) or more of the first to fourth differential clock signals IN000 / IN180, IN045 / IN225, IN090 / IN270, and IN135 / IN315. Output the common output enable signal (ENABLE).

Then, in response to the common output enable signal ENABLE, the clock phase alignment circuit 120 first to fourth differential clock signals OUT000 / OUT180, OUT045 / OUT225, OUT090 / OUT270, and OUT135 / after the delayed period. OUT315) is output in the order of phase. In other words, the first to fourth clock alignment units 121, 123, 125, and 127 included in the clock phase alignment circuit 120 may remove the glitch in response to the common output enable signal ENABLE. The first to fourth differential clock signals OUT000 / OUT180, OUT045 / OUT225, OUT090 / OUT270, and OUT135 / OUT315 are output. Here, the glitch refers to a glitch that is undesirably generated in the initial generation period when the first to fourth differential clock signals IN000 / IN180, IN045 / IN225, IN090 / IN270, and IN135 / IN315 are generated (see FIG. 3).

Meanwhile, the operations of the first to fourth clock alignment units 121, 123, 125, and 127 will be described in more detail as follows. In this case, since the operations of the first to fourth clock alignment units 121, 123, 125, and 127 are all the same, only operations of the first clock alignment unit 121 are representatively described for convenience of description. The first synchronizer 121A outputs the first common output enable signal ENABLE by synchronizing the common output enable signal ENABLE with the first positive clock signal IN000, and the first output controller 121B outputs the first common output enable signal ENABLE. In response to the first common output enable signal ENABLE output from the first synchronizer 121A, the first differential clock signal OUT from which glitches are removed is output.

According to the exemplary embodiment of the present invention, there is an advantage in that a plurality of differential clock signals having different phases can be accurately output in phase order.

The technical idea of the present invention has been specifically described according to the above embodiments, but it should be noted that the embodiments described above are for explanation purposes only and not for the purpose of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

100: semiconductor integrated circuit 110: enable signal generator
120: clock phase alignment circuit 121: first clock alignment unit
121A: first synchronizer 121B: first output controller
123 to 127: second to fourth clock alignment units

Claims (5)

A semiconductor integrated circuit comprising a clock phase alignment circuit for sequentially aligning a plurality of clock signals having different phases,
And the clock phase alignment circuit outputs each of the plurality of clock signals in phase order from a predetermined interval in response to a common output enable signal.
An enable signal generator for generating a common output enable signal by delaying the common output control signal by a predetermined period; And
A plurality of clock alignment units for outputting a plurality of clock signals having different phases in order of phase in response to the common output enable signal,
Each of the plurality of clock alignment units,
A synchronization unit for outputting the common output enable signal in synchronization with each clock signal; And
An output control unit for outputting each clock signal in response to a common output enable signal output from the synchronization unit
Semiconductor integrated circuit comprising a.
An enable signal generator for generating a common output enable signal by delaying the common output control signal by a predetermined period; And
A plurality of clock alignment units for outputting a plurality of differential clock signals having different phases in order of phase in response to the common output enable signal;
Each of the plurality of clock alignment units,
A synchronization unit for outputting the common output enable signal in synchronization with any one of the respective differential clock signals; And
An output control unit for outputting each differential clock signal in response to a common output enable signal output from the synchronization unit
Semiconductor integrated circuit comprising a.
The method according to claim 2 or 3,
The common output control signal is an asynchronous signal,
And the enable signal generation unit generates the common output enable signal synchronized with an internal clock signal.
5. The method of claim 4,
And the enable signal generator includes a shifting unit configured to output the common output enable signal by shifting the common output control signal a predetermined number of times in response to the internal clock signal.
KR1020110139608A 2011-12-21 2011-12-21 Semiconductor integrated circuit KR20130072061A (en)

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KR1020110139608A KR20130072061A (en) 2011-12-21 2011-12-21 Semiconductor integrated circuit

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KR1020110139608A KR20130072061A (en) 2011-12-21 2011-12-21 Semiconductor integrated circuit

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