KR20130071975A - Semiconductor memory device and operating method thereof - Google Patents

Abstract

PURPOSE: Semiconductor memory device and operation method thereof are provided to improve performance of a semiconductor device by improving a parameter of signal inputted through a pad and internal clock signal. CONSTITUTION: A first address latching unit (520) receives a scheduled number of bank addresses and latches the addresses in a normal operation mode, and successively receives bank addresses with a number of address pins less than a scheduled number and latches the addresses in a test operation mode. A second address latching unit (530) receives a scheduled number of cell addresses and latches the addresses in a normal operation mode, and successively receives the cell addresses with a number of address pins less than a scheduled number and latches the addresses in a test operation mode. A mode control unit (510) resets an output signal of the first address latching unit in a test operation mode and controls normal operation mode and test operation mode of the first and second address latching units in response to the output signal. [Reference numerals] (510) Mode control unit; (520) First address latching unit; (530) Second address latching unit; (540) Command latching unit; (550) Command decoding unit; (560) Mode selecting unit; (570) Address decoding unit

Description

Semiconductor memory device and its operation method {SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF}

The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device which reduces the number of pins used in a test operation mode.

In general, a semiconductor memory device including DDR Double Data Rate Synchronous DRAM (SDRAM) receives an address from an external chipset and performs a data access operation of a memory cell in response to the received address. The address may be divided into a row address and a column address of a memory cell to be accessed, and are input at different times through the same address pad. In the case of the address pad, the address pin and the address pin are connected to each other by a metal wiring, and thus, the address pad and the address pin are almost identical in this specification.

Meanwhile, as the degree of integration of a semiconductor memory device increases, the number of memory cells increases, which means that the number of memory banks that are a collection of memory cells increases. Therefore, the address must include information for accessing the memory bank as well as information for accessing the memory cells. In other words, the address includes both the cell address for accessing the memory cell and the bank address for accessing the memory bank.

On the other hand, the semiconductor memory device undergoes various test operation modes before commercialization, and detects a semiconductor memory device in which a failure occurs through the test operation mode. In general, in a test operation mode, a semiconductor memory device receives a predetermined number of probe pins from test equipment, and receives various types of information through the probe pins to perform a predetermined test operation mode. The number of probe pins allocated to one semiconductor memory device is closely related to the number of semiconductor memory devices capable of performing tests in one test device. That is, the fewer pins the semiconductor memory device should use in the test operation mode, the greater the number of semiconductor memory devices that can be tested in one test equipment, which shortens the test time and lowers the cost. it means.

1 is a block diagram illustrating a part of a configuration of a conventional semiconductor memory device.

Referring to FIG. 1, a semiconductor memory device may include a mode controller 110, an address latching unit 120, a command latching unit 130, a command decoding unit 140, a mode setting unit 150, and an address. The decoding unit 160 is provided.

The mode controller 110 generates a test enable signal EN_TM in response to the signal PCKE buffering the clock enable signal CKE and the test entry signal NTR. The address latching unit 120 latches the signal PBA [3: 0] buffering the zeroth to third bank address signals BA [3: 0], and the zeroth to thirteenth cell address signals A [ 13: 0]) is latched by multiplexing the signal PA [13: 0] buffered according to the test enable signal EN_TM. The multiplexing operation and the latching operation of the address latching unit 120 will be described later. The zeroth to third bank address signals TLBA [3: 0] and the seventh cell address signal TLA [7] output from the address latching unit 120 are input to the mode setting unit 150, and the 0th to third bank address signals TLBA [3: 0] are input to the mode setting unit 150. The thirteenth cell address signal TLA [13: 0] is input to the address decoding unit 160.

On the other hand, the command latching unit 130 is for latching the signal PCMD buffering the command signal CMD, and is applied to the internal clock signal ICLK buffering the positive clock signal CK and the sub clock signal CKB. In response, the signal PCMD buffering the command signal CMD is latched. Subsequently, the command decoding unit 140 generates the MRS enable signal EN_MRS by decoding the latched command signal LCMD output from the command latching unit 130. Here, the command decoding unit 140 generates a plurality of internal command signals by decoding the latched command signal LCMD. The MRS enable signal EN_MRS is one of the plurality of internal command signals, and the MRS enable signal EN_MRS is a signal that is activated when a mode register set (MRS) is set.

Next, the mode setting unit 150 may include the 0th to 3rd bank address signals TLBA [3: 0], the 7th cell address signal TLA [7], and the command outputted from the address latching unit 120. The MRS mode signals NMRS, EMRS0, EMRS1, ... EMRS15 and the test entry signal NTR are generated in response to the MRS enable signal EN_MRS output from the decoder 140. Finally, the address decoding unit 160 decodes the 0 th to 13 th cell address signals TLA [13: 0] output from the address latching unit 120, and the decoded signals are used for the data access operation. .

FIG. 2 is a circuit diagram for describing a partial configuration of the mode setting unit 150 of FIG. 1.

1 and 2, the mode setting unit 150 may include the 0 to 3rd bank address signals TLBA [0], TLBA [1], and TLBA [2 when the MRS enable signal EN_MRS is activated. ], TLBA [3] and a logic gate so as to be activated according to the seventh cell address signal TLA [7]. That is, when the MRS enable signal EN_MRS is activated with logic 'high', all of the zero to third bank address signals TLBA [0], TLBA [1], TLBA [2], and TLBA [3] are all present. When the logic 'low' and the seventh cell address signal TLA [7] becomes logic 'high', the test entry signal NTR transitions from logic 'low' to logic 'high' and is activated. Thereafter, the activated test entry signal NTR is input to the mode controller 110 and used as a signal for activating the test enable signal EN_TM.

3 is an operation waveform diagram for describing the circuit operation of FIGS. 1 and 2.

1 to 3, the operations of (A), (B), and (C) of the semiconductor memory device will be described.

First, (A) is an operation waveform when entering the test operation mode.

When the command signal CMD is set to a value MRS for enabling the test operation of the mode register set, the MRS enable signal EN_MRS (Fig. 2) is activated with logic 'high'. On the other hand, when all of the zero through third bank address signals BA [3: 0] become logic 'low' and the seventh cell address signal A [7] becomes logic 'high', the test entry signal ( NTR) is activated from logic 'low' to logic 'high'. On the other hand, when the clock enable signal CKE is activated with logic 'low', the test enable signal EN_TM transitions from logic 'low' to logic 'high' in response to the buffered signal PCKE. . The test enable signal EN_TM goes logic 'high' to indicate that the test operation mode has been entered.

Next, (B) is an operation waveform when the test operation mode is performed.

When the test operation mode is entered, the semiconductor memory device may enter odd-numbered cell address signals A [13, 11, 9, 7, 5, 3, 0 through 13th cell address signals A [13: 0]. 1]) using even-numbered cell address signals A [12, 10, 8, 6, 4, 2, 0] and odd-numbered cell address signals A [13, 11, 9, 7, 5, 3, 1]) is input to perform circuit operation. That is, even-numbered cell address signals A [12, 10, 8, 6, ... are inputted to the cell address pins to which odd-numbered cell address signals A [13, 11, 9, 7, 5, 3, 1] are input. 4, 2, 0]) and odd bit cell address signals A [13, 11, 9, 7, 5, 3, 1] are sequentially input, and the address latching unit 120 multiplexes and latches them. After that, the transfer to the address decoding unit 160. Therefore, the semiconductor memory device receives the 0 th to 13 th cell address signals A [13: 0] through the 14 cell address pins in the normal operation mode, and receives the 0 th through 7 cell address pins in the test operation mode. The thirteenth cell address signal A [13: 0] is divided and received.

As shown in (B) of FIG. 3, '7F', which is first input as an odd bit cell address signal A [13, 11, 9, 7, 5, 3, 1], represents an internal clock signal ICLK. In response to the falling edge, the even-numbered cell address signal TLA [12, 10, 8, 6, 4, 2, 0] is latched, and the input '0' is an odd-bit cell address signal. (TLA [13, 11, 9, 7, 5, 3, 1]).

Finally, (C) is the normal operation waveform in the test operation mode.

First, after the command signal CMD is set to a value ACT for enabling an active operation during a normal operation, the first to third bank address signals BA [3: 0] for accessing a desired memory cell and the like. The 0th to 13th cell address signals A [13: 0] are input. In the case of (C), as in the case of (B), '0' first input as an odd bit cell address signal A [13, 11, 9, 7, 5, 3, 1] is an even bit cell address. Latched with signal A [12, 10, 8, 6, 4, 2, 0], and then input '7F' is an odd bit of cell address signal A [13, 11, 9, 7, 5, 3 , 1]).

FIG. 4 is a table for explaining input / output results in the test operation mode of the waveform diagram of FIG. 3.

As shown in FIGS. 3 and 4, the first value input as an odd bit cell address signal A [13, 11, 9, 7, 5, 3, 1] is a falling edge of the internal clock signal ICLK. In response to the even-numbered cell address signals A [12, 10, 8, 6, 4, 2, 0], and odd-numbered cell address signals A [13, 11, 9, 7, 5, 3, 1]) latches an odd bit of cell address signal A [13, 11, 9, 7, 5, 3, 1] in response to the rising edge of the internal clock signal ICLK. do. In this case, since the 0 th to third bank address signals BA [3: 0] are used to generate the test entry signal NTR of FIG. 2, they are not separately input like the cell address signals. That is, the four bank address pins to which the 0 to third bank address signals BA [3: 0] are input have the same number used in the normal operation mode and the test operation mode.

On the other hand, if the number of pins used in the test operation mode is reduced, it will be possible to increase the competitiveness of the semiconductor memory device due to the shortening of the test time and the cost reduction effect.

An embodiment of the present invention is to provide a semiconductor memory device that can reduce the number of pins used in the test operation mode.

A method of operating a semiconductor memory device according to an exemplary embodiment of the present invention may include: performing an access operation in response to first and second addresses input from first and second address input terminals in a normal operation mode; Resetting an output terminal corresponding to the first address and entering a test operation mode in response to the reset output terminal; Latching the first and second addresses sequentially input from the second address input terminal in the test operation mode; And performing a predetermined test operation in response to the first and second addresses.

Preferably, the method further includes performing an access operation in response to the third and fourth cell addresses input from the third and fourth address input terminals in the normal operation mode, and from the fourth address input terminal in the test operation mode. The third and fourth cell addresses may be sequentially input.

The semiconductor memory device according to another embodiment of the present invention receives and latches a predetermined number of bank addresses in a normal operation mode, and sequentially receives the bank addresses with fewer address pins than a predetermined number in a test operation mode. A first address latching portion for calling; A second address latching unit configured to receive and latch a predetermined number of cell addresses in the normal operation mode, and to receive and latch the cell addresses with fewer address pins than the predetermined number in the test operation mode; A mode control unit for resetting an output signal of the first address latching unit in the test operation mode, and controlling the normal operation mode and the test operation mode in response to the output signal; And an operation performing unit configured to perform a predetermined operation in response to output signals of the first and second address latching units in the normal operation mode and the test operation mode.

Preferably, the first address latching unit includes: a plurality of latching units for sequentially receiving and latching the bank addresses in the test operation mode; And a multiplexing unit for sequentially transferring the bank addresses to the plurality of latching units.

A semiconductor memory device according to another embodiment of the present invention is disposed in a first region corresponding to an area in which a plurality of first address input terminals are disposed, and for latching bank addresses input from the plurality of first address input terminals. A first address latching unit; And a second address latching unit disposed in a second area corresponding to an area in which a plurality of second address input terminals are disposed, and latching a cell address input from the plurality of second address input terminals.

Preferably, the first clock transmission line for transmitting an internal clock signal to the first address latching unit; And a second clock transfer line for transferring the internal clock signal to the second address latching unit.

The first address latching unit may be disposed to correspond to the center of the plurality of first address input terminals in the first area.

The semiconductor memory device according to the embodiment of the present invention reduces the number of pins used in the test operation mode, thereby reducing test time and thereby reducing costs.

By reducing the test time and the resulting cost, the semiconductor memory device can be more competitive.

1 is a block diagram illustrating a part of a configuration of a conventional semiconductor memory device.
FIG. 2 is a circuit diagram for describing a partial configuration of the mode setting unit 150 of FIG. 1.
3 is an operation waveform diagram for describing the circuit operation of FIGS. 1 and 2.
FIG. 4 is a table for explaining input / output results in the test operation mode of the waveform diagram of FIG. 3.
5 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to an embodiment of the present invention.
FIG. 6 is a block diagram illustrating the first address latching unit 510 of FIG. 5.
FIG. 7 is an operation waveform diagram for describing the circuit operation of FIGS. 5 and 7.
FIG. 8 is a table for explaining input / output results in the test operation mode of the waveform diagram of FIG. 7.
9 is a block diagram illustrating an arrangement relationship of some components of a semiconductor memory device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

5 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to an embodiment of the present invention.

 Referring to FIG. 5, a semiconductor memory device may include a mode controller 510, first and second address latching units 520 and 530, a command latching unit 540, a command decoding unit 550, and a mode setting. A unit 560 and an address decoding unit 570 are provided.

The mode controller 510 generates a test enable signal EN_TM in response to the signal PCKE buffering the clock enable signal CKE and the test entry signal NTR. Here, the clock enable signal CKE is a signal for controlling the toggling operation of the positive and negative clock signals CK and CKB. The first address latching unit 520 multiplexes the signals PBA [3: 0] buffered from the 0 to third bank address signals BA [3: 0] according to the test enable signal EN_TM. The second address latching unit 530 multiplexes the signal PA [13: 0] buffering the 0th to 13th cell address signals A [13: 0] according to the test enable signal EN_TM. To latch.

The first and second address latching units 520 and 530 according to an exemplary embodiment of the present invention receive a signal PCKE buffered with a clock enable signal CKE, and respond to 0 and 0 in response to the signal PCKE. The output signal corresponding to the second bank address signal TLBA [2, 0] is reset. As will be described later, the mode setting unit 560 activates the test entry signal NTR in response to the reset signal. It is possible.

The command latching unit 540 latches the signal PCMD buffering the command signal CMD, and responds to the internal clock signal ICLK buffering the positive clock signal CK and the sub clock signal CKB. The signal PCMD buffering the command signal CMD is latched. Here, the command signal CMD means, for example, a las signal, a cas signal, a chip select signal, a write enable signal, and the like.

The command decoding unit 550 decodes the latched command signal LCMD output from the command latching unit 540 to generate an MRS enable signal EN_MRS. Here, the command decoding unit 550 decodes the latched command signal LCMD to generate a plurality of internal command signals. Here, the MRS enable signal EN_MRS is one of the plurality of internal command signals, and the MRS enable signal EN_MRS is a signal that is activated when the mode register set is set.

Subsequently, the mode setting unit 560 may include the zeroth to third bank address signals TLBA [3: 0] and the seventh cell address signal TLA [outputted from the first and second address latching units 520 and 530. 7]) and a plurality of MRS mode signals NMRS, EMRS0, EMRS1, ... EMRS15 and a test entry signal NTR in response to the MRS enable signal EN_MRS output from the command decoding unit 550. do. Finally, the address decoding unit 570 decodes the 0 th to 13 th cell address signals TLA [13: 0] output from the second address latching unit 530, and the decoded signal is subjected to the data access operation. Is used.

FIG. 6 is a block diagram illustrating the first address latching unit 510 of FIG. 5.

Referring to FIG. 6, the first address latching unit 510 includes a synchronization unit 610, a multiplexer 620, and a plurality of latching units 630.

The synchronization unit 610 synchronizes the first and third bank address signals PBA [1, 3] to the multiplexer 620 in response to the internal clock signal ICLK. The multiplexer 620 receives the first and third bank address signals PBA [3, 1] from the zero and second bank address signals PBA [0,2] or the first in response to the test entry signal NTR. The first and third bank address signals PBA [1, 3] are output.

In the exemplary embodiment of the present invention, the zero and second bank address signals PBA [0, 2] are transmitted to the first latching unit 631 in the normal operation mode, and the first and third bank address signals in the test operation mode. (PBA [1,3]) is transferred to the first latching portion 631. Here, the first latching unit 631 is reset in response to the signal PCKE buffering the clock enable signal CKE. That is, for example, a logic 'low', which is a predetermined initial value of the initial section of the test operation, is output. In the embodiment of the present invention, the first latching unit 631 is reset, but it is also possible to reset not only the first latching unit 631 but also the second latching unit 632 depending on the design. Therefore, the output signals of the first and second latching units 631 and 632 become logic 'low' at the time when the signal PCKE buffering the clock enable signal CKE is activated.

Meanwhile, each component of the first address latching unit 510 may vary according to a design. In this case, the synchronization unit 610 synchronizes and outputs an input signal in response to a falling edge of the internal clock signal ICLK. As an example, the first and second latching units 631 and 632 latch and output the input signal in response to the rising edge of the internal clock signal ICLK.

FIG. 7 is an operation waveform diagram for describing the circuit operation of FIGS. 5 and 7.

5 to 7, operation (A), (B) and (C) of the semiconductor memory device will be described.

First, (A) is an operation waveform when entering the test operation mode.

When the command signal CMD is set to a value MRS for enabling the test operation of the mode register set, the MRS enable signal EN_MRS (Fig. 2) is activated with logic 'high'. On the other hand, the zero and second bank address signals BA [2, 0] are reset to logic 'low' in response to the signal PCKE buffering the clock enable signal CKE, and the first and third banks are reset. The address signal BA [3, 1] is inputted with '0' to become logic 'low'. That is, all of the zero through third bank address signals BA [3: 0] become logic 'low'. Subsequently, when the seventh cell address signal A [7] becomes logic 'high', the test entry signal NTR is activated from logic 'low' to logic 'high'. Here, the test enable signal EN_TM becomes logic 'high' in response to the test entry signal NTR, which means that the test operation mode has been entered.

Next, (B) is an operation waveform when the test operation mode is performed.

When the test operation mode is entered, the semiconductor memory device may enter odd-numbered cell address signals A [13, 11, 9, 7, 5, 3, 0 through 13th cell address signals A [13: 0]. 1]) is an odd bit cell address signal A [13, 11, 9, 7, 5, 3, 1] and an even bit cell address signal A [12, 10, 8]. , 6, 4, 2, 0]) and performs the circuit operation. That is, even-numbered cell address signals A [12, 10, 8, 6, 4 are input to the address pins to which odd-numbered cell address signals A [13, 11, 9, 7, 5, 3, 1] are input. , 2, 0] and odd bit cell address signals A [13, 11, 9, 7, 5, 3, 1] are sequentially input, and the second address latching unit 530 multiplexes them. After the call, the data is transmitted to the address decoding unit 570. Therefore, the semiconductor memory device receives the 0 th to 13 th cell address signals A [13: 0] through the 14 cell address pins in the normal operation mode, and receives the 0 th through 7 cell address pins in the test operation mode. The thirteenth cell address signal A [13: 0] is divided and received.

Subsequently, the semiconductor memory device uses an address pin to which odd-numbered bank address signals BA [3, 1] are input from among the zeroth to third bank address signals BA [3: 0]. A circuit operation is performed by receiving the signals BA [3, 1] and even-numbered bank address signals BA [2, 0]. That is, even-numbered bank address signals BA [2, 0] and odd-numbered bank address signals BA [3, 1] are address pins to which odd-numbered bank address signals BA [3, 1] are input. ) Is continuously input, and the first address latching unit 520 latches the multiplexing. Therefore, the semiconductor memory device receives the zero through third bank address signals BA [3: 0] through the four bank address pins in the normal operation mode, and the zero through the two bank address pins in the test operation mode. To third bank address signals BA [3: 0].

That is, in the semiconductor memory device according to the embodiment of the present invention, not only the 0th to 13th cell address signals A [13: 0] but also the 0th to 3rd bank address signals BA [3: 0] are normal. It is possible to use fewer bank address pins in the operating mode.

As shown in FIG. 7B, '1', which is first input as an odd bit bank address signal BA [3, 1], is an even bit bank address in response to a falling edge of the internal clock signal ICLK. The signal BA [2, 0] is latched, and then the input '0' is latched by the odd bit bank address signal BA [3, 1].

Finally, (C) is the normal operation waveform in the test operation mode.

First, after the command signal CMD is set to a value ACT for enabling an active operation during a normal operation, the first to third bank address signals BA [3: 0] for accessing a desired memory cell and the like. The 0th to 13th cell address signals A [13: 0] are input. In the case of (C), as in the case of (B), '0' first input as an odd bit bank address signal BA [3, 1] is an even bit bank address signal BA [2, 0]. Is latched, and then '1' is latched into an odd bit of bank address signal BA [3, 1].

As a result, the semiconductor memory device according to the embodiment of the present invention uses two bank address pins in the test operation mode, and is identical to the latched bank address signal TLBA [3: 0] of FIG. 3 corresponding to the existing technology. It is possible to obtain the latched bank address signal TLBA [3: 0] of FIG. 7 corresponding to an embodiment of the present invention.

FIG. 8 is a table for explaining input / output results in the test operation mode of the waveform diagram of FIG. 7.

As shown in FIG. 7 and FIG. 8, the first value input as the odd bit cell address signal A [13, 11, 9, 7, 5, 3, 1] is the falling edge of the internal clock signal ICLK. In response to the even bit of the cell address signal A [12, 10, 8, 6, 4, 2, 0], the second value of the odd bit in response to the rising edge of the internal clock signal ICLK. Latched to the cell address signal A [13, 11, 9, 7, 5, 3, 1]. Further, the first value input to the odd bit bank address signal BA [3, 1] is converted to the even bit bank address signal BA [2, 0] in response to the falling edge of the internal clock signal ICLK. The second value is latched into an odd bit bank address signal BA [3, 1] in response to the rising edge of the internal clock signal ICLK.

9 is a block diagram illustrating an arrangement relationship of some components of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 9, a semiconductor memory device may include a command latching unit 910, a first address latching unit 920, a second address latching unit 930, a clock pad 940, and a command pad 950. And first and second address pads 960 and 970.

The command latching unit 910 latches a command signal input through the command pad 950 in response to the first internal clock signal ICLK1. The first address latching unit 920 latches and outputs the bank address signal input through the first address pad 960 in response to the second internal clock signal ICLK2. Next, the second address latching unit 930 latches and outputs the cell address signal input through the second address pad 970 in response to the third internal clock signal ICLK3 and outputs TLA [13: 0]. Here, the first to third internal clock signals ICLK1, ICLK2, and ICLK3 are clock signals sourced from an external clock signal input through the clock pad 940 and have different names according to distances transmitted. Accordingly, it can be said that the first to third clock signals ICLK1, ICLK2, and ICLK3 are transmitted to corresponding latching units through different transmission lines.

As shown in the drawing, the first address latching unit 920 is disposed in an area corresponding to an area in which the first address pad 960 is disposed (hereinafter, referred to as a 'first area'), and the second address latching unit The title unit 930 is disposed in an area corresponding to an area in which the second address pad 970 is disposed (hereinafter, referred to as a “second area”). In particular, the first address latching unit 920 is disposed corresponding to the center of the first address pad 960 in the first region, and the second address latching unit 930 is the second address pad 970 of the second region. It is disposed corresponding to the center of the.

The semiconductor memory device according to the embodiment of the present invention may improve the tIS / tIH parameters of the bank address signal and the second internal clock signal ICLK2 input through the first address pad 960 through the arrangement. The tIS / tIH parameter of the cell address signal and the third internal clock signal ICLK3 input through the second address pad 970 may be improved.

As described above, in the semiconductor memory device according to the embodiment of the present invention, it is possible to reduce the test time and cost by reducing the number of pins used in the test operation mode, thereby increasing the competitiveness of the semiconductor memory device. Do. In addition, by improving the parameter between the signal input through the pad and the internal clock signal, it is possible to improve the performance of the semiconductor memory device.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

In addition, the logic gates and transistors exemplified in the above-described embodiments must be implemented in different positions and types according to the polarity of input signals.

510: mode control unit
520: first address latching unit
530: second address latching unit
540 command latching unit
55; Command decoding unit
560: mode setting unit
570: address decoding unit

Claims (20)

Performing an access operation in response to the first and second addresses input from the first and second address input terminals in the normal operation mode;
Resetting an output terminal corresponding to the first address and entering a test operation mode in response to the reset output terminal;
Latching the first and second addresses sequentially input from the second address input terminal in the test operation mode; And
Performing a predetermined test operation in response to the first and second addresses
Wherein the semiconductor memory device is a semiconductor memory device.
The method of claim 1,
And the predetermined test operation comprises the access operation.
The method of claim 1,
And the first and second addresses comprise bank addresses. The method of claim 1,
And performing an access operation in response to the third and fourth cell addresses input from the third and fourth address input terminals in the normal operation mode.
5. The method of claim 4,
And receiving the third and fourth cell addresses sequentially from the fourth address input terminal in the test operation mode.
A first address latching unit configured to receive and latch a predetermined number of bank addresses in a normal operation mode, and sequentially receive and latch the bank addresses with fewer address pins than a predetermined number in a test operation mode;
A second address latching unit configured to receive and latch a predetermined number of cell addresses in the normal operation mode, and to receive and latch the cell addresses with fewer address pins than the predetermined number in the test operation mode;
A mode control unit for resetting an output signal of the first address latching unit in the test operation mode, and controlling the normal operation mode and the test operation mode in response to the output signal; And
An operation performing unit configured to perform a predetermined operation in response to output signals of the first and second address latching units in the normal operation mode and the test operation mode;
And the semiconductor memory device.
The method according to claim 6,
And the operation performing unit comprises a decoding unit for decoding the first and second addresses.
The method according to claim 6,
The first address latching unit,
A plurality of latching units for sequentially receiving and latching the bank addresses in the test operation mode; And
And a multiplexing unit for sequentially transferring the bank addresses to the plurality of latching units.
9. The method of claim 8,
And at least one of the latching units resets an initial section of the test operation to output a predetermined initial value.
9. The method of claim 8,
And the mode controller generates a test entry signal for entering the test operation mode in response to an output signal of the first address latching unit.
The method of claim 10,
And the multiplexer performs a multiplexing operation in response to the test entry signal.
A first address latching unit disposed in a first area corresponding to an area in which a plurality of first address input terminals are arranged, and latching a bank address input from the plurality of first address input terminals; And
A second address latching unit arranged in a second area corresponding to an area in which a plurality of second address input terminals are arranged, for latching a cell address input from the plurality of second address input terminals;
And the semiconductor memory device.
The method of claim 12,
A first clock transfer line for transferring an internal clock signal to the first address latching unit; And
And a second clock transfer line for transferring the internal clock signal to the second address latching unit.
The method of claim 12,
And the first address latching unit is disposed corresponding to a center of the plurality of first address input terminals of the first region.
The method of claim 12,
And the second address latching unit is disposed corresponding to a center of the plurality of second address input terminals of the second area. The method of claim 12,
And the output signal of the first address latching unit is reset in a test operation mode.
The method of claim 12,
And a mode controller configured to generate a test entry signal for entering a test operation mode in response to an output signal of the first address latching unit.
18. The method of claim 17,
And the first and second address latching units multiplex and latch an address input to the address latching unit in response to the test entry signal.
The method of claim 12,
And the plurality of first address input terminals sequentially receive the bank addresses from some address input terminals of the plurality of first address input terminals in a test operation mode.
The method of claim 12,
And the plurality of second address input terminals sequentially receive the cell addresses from some address input terminals of the plurality of second address input terminals in a test operation mode.

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