KR20130070926A - Non volatile memory device and operating method thereof - Google Patents

Non volatile memory device and operating method thereof Download PDF

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Publication number
KR20130070926A
KR20130070926A KR1020110138201A KR20110138201A KR20130070926A KR 20130070926 A KR20130070926 A KR 20130070926A KR 1020110138201 A KR1020110138201 A KR 1020110138201A KR 20110138201 A KR20110138201 A KR 20110138201A KR 20130070926 A KR20130070926 A KR 20130070926A
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South Korea
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program
bit line
memory cells
voltage
memory cell
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KR1020110138201A
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Korean (ko)
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서지현
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에스케이하이닉스 주식회사
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Priority to KR1020110138201A priority Critical patent/KR20130070926A/en
Publication of KR20130070926A publication Critical patent/KR20130070926A/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/14Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/24Bit-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

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Abstract

PURPOSE: A nonvolatile memory device and an operation method thereof are provided to improve the threshold voltage distribution properties of memory cells in a program operation by controlling a bit line voltage. CONSTITUTION: A memory cell block(110) includes memory cells connected to even and odd bit lines. A page buffer unit(120) includes a plurality of page buffers respectively connected to the even and odd bit lines. A control unit(150) controls the page buffer to change a voltage applied to a bit line of a first memory cell into a correction bit line voltage within a program allowable voltage when a program prohibition voltage is applied to a bit line of a second memory cell by completing the program of the first memory cell and the adjacent second memory cell. [Reference numerals] (130) Comparison unit; (140) CAM cell unit; (150) Control unit; (160) Voltage providing unit

Description

Non-volatile memory device and operating method

The present invention relates to a nonvolatile memory device and a method of operating the same, and more particularly, to a nonvolatile memory device and a method of operating the threshold voltage distribution characteristics of the memory cells can be improved.

There is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function that rewrites data at regular intervals. Here, the program refers to an operation of writing data to a memory cell. The NAND flash memory device of the nonvolatile memory device has a large capacity because a plurality of memory cells are connected in series to form a single cell string by sharing drains or sources between adjacent cells. There is an advantage that is suitable for storing information.

1 is a block diagram illustrating a nonvolatile memory device according to the prior art.

Referring to FIG. 1, a nonvolatile memory device includes a memory cell block 10 and a page buffer unit 20.

The memory cell block 10 includes a plurality of strings ST1 to STk, each of which is connected to a plurality of memory cells MC0 to MCn connected between the source line SL and one bit line (eg, BL1). ). The page buffer unit 20 includes a plurality of page buffers PB1 to PBk, and each page buffer is connected to each bit line of the memory cell block 10.

In the conventional method of programming a nonvolatile memory device, program data is temporarily stored in a plurality of page buffers PB1 to PBk, and then the potential of each bit line is controlled according to the program data. Thereafter, a program voltage is applied to the selected word line (eg, WL <0>) of the memory cell block 10, and a pass voltage is applied to the remaining unselected word lines.

Subsequently, when the threshold voltage of the memory cell MC0 connected to the selected word line WL <0> rises above the verify voltage by performing a program verify operation, it is determined as a pass. Thereafter, a program inhibit voltage (for example, VCC) is applied to a bit line connected to the memory cell determined as a pass as a result of a program verifying operation to boost a channel of the corresponding string, and then the program voltage selected as the word line WL <0. Re-apply to &quot;) to program the remaining memory cells that have not yet been programmed.

The program operation of the nonvolatile memory device according to the related art may cause the following problems.

When a program inhibit voltage is applied to a bit line connected to a memory cell determined as a pass as a result of a program verifying operation, a coupling phenomenon occurs due to a potential difference between a string of which a channel is boosted and an adjacent bit line. This causes a problem that the program speed of the memory cell included in the string adjacent to the channel where the channel is boosted increases. As a result, the threshold voltage distribution of the memory cells may be degraded.

An embodiment of the present invention provides a nonvolatile memory device and a method of operating the same in which threshold voltage distribution characteristics of memory cells are improved during a program operation.

In an embodiment, a nonvolatile memory device may include a memory cell block including memory cells connected to an even and odd bit lines, and a page buffer unit including a plurality of page buffers respectively connected to the even and odd bit lines. And a voltage applied to the bit line of the first memory cell when the program inhibit voltage is applied to the bit line of the second memory cell when the second memory cell adjacent to the first memory cell which is not completed the program operation is programmed. And a controller for controlling the page buffer to change from the program allowable voltage to the corrected bit line voltage.

In an operating method of a nonvolatile memory device according to an embodiment of the present invention, after programming memory cells included in a memory cell block using an ABL program, a threshold voltage value of the memory cells is measured. Storing the threshold voltage value, programming the memory cells in an EOBL (Even odd bit line) method, and measuring the threshold voltage value of the memory cells and storing the threshold voltage value as a second threshold voltage value; and Generating and storing data of a correction bit line voltage by using a threshold voltage value and the second threshold voltage value.

A method of operating a nonvolatile memory device according to another embodiment of the present invention includes controlling a potential of bit lines according to program data for storing in memory cells, and applying a program voltage to the memory cells to perform a program operation. Performing a verify operation to check whether the memory cells have been programmed; and if it is determined that the verify operation has failed, detecting memory cells adjacent to a program cell in which the program is not completed; And a program inhibit voltage is applied to a bit line connected to the memory cell in which the program is completed, and a correction bit line voltage stored in the cam cell part in a bit line of cells adjacent to the memory cell in which the program is completed among the memory cells in which the program is not completed. Corrected according to the data Setting a bit line voltage, and applying a new program voltage to which the program voltage is raised and re-starting the program operation.

The present technology improves the threshold voltage distribution characteristic of memory cells during a program operation by controlling the bit line voltage to compensate for coupling by adjacent strings.

1 is a block diagram of a nonvolatile memory device according to the prior art.
2 is a block diagram of a nonvolatile memory device according to the present invention.
3 is a flowchart illustrating a method of setting a correction bit line voltage of a nonvolatile memory device according to the present invention.
4 is a graph illustrating a threshold voltage difference according to a program method.
5 is a flowchart illustrating a program method of a nonvolatile memory device according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

2 is a block diagram of a nonvolatile memory device according to the present invention.

Referring to FIG. 2, the nonvolatile memory device 100 according to the present invention may include a memory cell block 110, a page buffer unit 120, a comparison unit 130, a cam cell unit 140, a controller 150, and The voltage providing unit 160 is included.

The memory cell block 110 includes a plurality of strings ST1 to STk. Since each string has a similar structure, one string is described as an example. The string ST1 includes a source select transistor SST, a plurality of memory cells MC0 to MCn, and a drain select transistor DST connected in series between the source line SL and the bit line BL1. The plurality of memory cells MC0 to MCn are connected to the plurality of word lines WL <n: 0>, respectively.

The page buffer unit 120 includes a plurality of page buffers PB1 to PBk respectively connected to the plurality of bit lines BL1 to BLk of the memory cell block 110. Each page buffer senses and stores a threshold voltage value of a selected memory cell among memory cells connected to a corresponding bit line during a threshold voltage measurement operation. Each page buffer is programmed after the threshold voltage value and the memory cells connected to the even bit line when programmed in the all bit line program (ALB) method, which simultaneously programs the memory cells connected to all the bit lines during the threshold voltage measurement operation. It is preferable to sense and store threshold voltage values when the memory cells are programmed in an even odd bit line program (EOBL) scheme for programming memory cells connected to a bit line.

Each page buffer temporarily stores data for programming in a selected memory cell among memory cells connected to a corresponding bit line during a program operation, and then controls a potential of the corresponding bit line according to the stored data. Also, in each page buffer, the memory cell connected to the adjacent bit line during the program operation is completed and the voltage applied to the bit line is changed from the program allowable voltage (for example, 0V) to the program inhibit voltage (for example, VCC). In this case, it is programmed by applying a correction bit line voltage in which the potential of the bit line corresponding to the page buffer is increased by the correction voltage (ΔV) from the program allowable voltage.

The comparator 130 measures the threshold voltage value V ABL of the memory cell programmed in the ABL method measured by the page buffer unit 120 and the threshold voltage value V of the memory cell programmed in the EOBL method during the threshold voltage measurement operation. EOBL ) is compared to generate correction voltage information DELTA V_DATA.

The cam cell unit 140 stores the correction voltage information ΔV_DATA generated by the comparator 130 and then outputs the stored data as the cam data CAM_DATA to the controller 150 when the program operation is performed.

The controller 150 controls a plurality of page buffer control signals PB_SIGNALS for controlling the page buffer unit 120 and a plurality of voltage provider control signals PM_SIGNALS for controlling the voltage provider 160 during the threshold voltage measurement operation. Create In addition, when a program operation of a memory cell connected to an adjacent bit line is completed during a program operation, and the voltage applied to the bit line is changed from a program allowable voltage (for example, 0V) to a program prohibition voltage (for example, VCC), cam data According to CAM_DATA, the page buffer unit 120 is controlled so that the correction bit line voltage, which is increased by the correction voltage DELTA V, is applied to the bit line according to CAM_DATA.

The voltage provider 160 generates a program voltage Vpgm, a program verify voltage Vpv, and a pass voltage Vpass in response to the plurality of voltage provider control signals PM_SIGNALS output from the controller 150 to generate a memory cell. Applied to selected word lines of a plurality of word lines of block 110.

3 is a flowchart illustrating a method of setting a correction bit line voltage of a nonvolatile memory device according to the present invention.

4 is a graph illustrating a threshold voltage difference according to a program method.

A method of setting a correction bit line voltage of a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. 2 through 4 as follows.

1) ABL program (S310)

After program data is temporarily stored in all page buffers PB1 to PBk of the page buffer unit 120 connected to the memory cell block 110, all bit lines BL1 to BLk of the memory cell block 110 are stored according to the program data. Is set to the program allowable potential level (eg 0V).

Thereafter, a pass voltage and a program voltage are selectively applied to word lines WL <n: 0> of the memory cell block 110 to first test program the memory cells. The first test program operation is performed by an ABL program method of simultaneously programming memory cells connected to all bit lines.

The above-described ABL program is a program operation for setting the correction bit line voltage, and the program data may be set to have the same data value.

2) Threshold voltage value measurement (S320)

After the above-described ABL program operation, the threshold voltage value V ABL of the programmed memory cells is measured using the page buffer unit 120. In this case, the measured threshold voltage value V ABL may be set as an average value after measuring the threshold voltage values of all the memory cells.

3) EOBL Program (S330)

After the above-described step of measuring the threshold voltage value (S320), data programmed in the memory cell block 110 is erased. Thereafter, during the ABL program operation S310, the same test data as the programmed data is second-tested to the memory cell block 110 in the EOBL method. In more detail, first, the same data as the program data programmed during the ABL program operation S310 is temporarily stored in each page buffer PB1 to PBk of the page buffer unit 120. Thereafter, according to the program data stored in the page buffers (PB1, PB3, ...) connected to the even bit lines (BL1, BL3, ...), the corresponding bit line to the program allowable potential level (for example, 0V). Set it. Thereafter, a pass voltage and a program voltage are selectively applied to the word lines WL <n: 0> of the memory cell block 110 to test program the memory cells connected to the even bit line. During a program operation of memory cells connected to an even bit line, a program prohibition voltage (eg, VCC) is applied to an odd bit line.

Thereafter, according to the program data stored in the page buffers (PB2, PB4, ...) connected to the odd bit lines (BL2, BL4, ...), the corresponding bit line to the program allowable potential level (for example, 0V). Set it. Thereafter, a pass voltage and a program voltage are selectively applied to word lines WL <n: 0> of the memory cell block 110 to program memory cells connected to the odd bit line. In the program operation of the memory cells connected to the odd bit line, a program prohibition voltage (eg, VCC) is applied to the even bit line.

4) Threshold voltage value measurement (S340)

After the above-described EOBL program operation, the threshold voltage value V EOBL of the programmed memory cells is measured using the page buffer unit 120. In this case, the measured threshold voltage value V EOBL may be set as an average value after measuring the threshold voltage values of all the memory cells.

5) Correction bit line voltage setting (S350)

The comparator 130 uses the threshold voltage value V ABL of the memory cells after the ABL program operation measured by the page buffer unit 120 and the threshold voltage value V EOBL of the memory cells after the EOBL program operation. The correction bit line voltage data DELTA V_DATA is generated.

The correction bit line voltage data ΔV_DATA is obtained by subtracting the threshold voltage value V EOBL of the memory cells after the EOBL program operation from the difference value ΔV obtained by subtracting the threshold voltage value V ABL of the memory cells after the ABL program operation. Indicates.

Referring to FIG. 4, the threshold voltage value of the memory cells due to the EOBL program operation is higher than the threshold voltage value of the memory cells due to the ABL program operation. The ABL program operation simultaneously programs memory cells connected to the even bit line and the odd bit line, so that there is little influence on interference by adjacent cells. However, since the EOBL program operation programs memory cells connected to the even bit line and memory cells connected to the odd bit line separately, the EOBL program operation is affected by the interference caused by adjacent memory cells when the memory cell is programmed. That is, when programming memory cells connected to the even bit line, a program inhibit voltage is applied to the odd bit line adjacent to the even bit line to boost the channel. As a result, the memory cells connected to the even bit line are affected by the interference by the channel of the adjacent memory cells. Accordingly, the correction bit line voltage data ΔV_DATA represents an interference influence value due to a channel of adjacent memory cells. This interference effect is changed according to the effective field oxide height (EFH) of the memory cell. Therefore, the correction bit line voltage data ΔV_DATA may be used as data for estimating the effective field oxide height of the memory cells included in the memory cell block 110.

6) Store the correction bit line voltage value in the cam cell unit (S360)

The cam cell unit 140 stores the correction bit line voltage data ΔV_DATA generated by the comparator 130. The correction bit line voltage data ΔV_DATA stored in the cam cell unit 140 is used in a program operation described later.

5 is a flowchart illustrating a program method of a nonvolatile memory device according to the present invention.

A program operation of the nonvolatile memory device in which the above-described correction bit line voltage data ΔV_DATA is stored in the cam cell unit 140 will be described with reference to FIGS. 2 and 5 as follows.

1) Read the cam cell part (S510)

The controller 150 reads the correction bit line voltage data ΔV_DATA stored in the cam cell unit 140. The correction bit line voltage is set by the read correction bit line voltage data DELTA V_DATA.

2) Program data input (S520)

Program data for programming the memory cell block 110 is externally input and temporarily stored in the page buffers PB1 to PBk of the page buffer unit 120.

3) Bit line voltage setting according to program data (S530)

Each page buffer PB1 to PBk controls the potential of the corresponding bit line according to the temporarily stored program data.

4) Program voltage application (S540)

The voltage provider 160 generates a program voltage Vpgm and a pass voltage Vpass in response to the voltage provider control signals PM_SIGNALS output from the controller 150 to generate a plurality of voltages connected to the memory cell block 110. It is selectively applied to the word line WL <n: 0>. In this case, the program method uses an ABL program method for simultaneously programming memory cells connected to the even and odd bit lines.

5) Verification operation (S550)

Each page buffer PB1 to PBk senses the potential of the corresponding bit line to determine whether the memory cells have been programmed above the target threshold voltage value. That is, when the memory cell is programmed to have a threshold voltage value greater than or equal to the target threshold voltage value, it is determined as a pass and it is determined as a fail so as to have a threshold voltage value lower than the target threshold voltage value.

If the number of memory cells determined as fail is larger than the number of error correction bits that can be processed by the error correction circuit (ECC), it is determined as a program fail, and the number of memory cells determined as fail is greater than the number of error correction bits. If it is small, it is determined as a program pass.

6) Checking Program Status of Failed Memory Cells and Adjacent Memory Cells (S560)

If it is determined that the program fails as a result of the verification operation described above, the controller 150 detects memory cells in which adjacent memory cells pass among the failed memory cells. That is, the case where the failed memory cell and the passed memory cell are adjacent to each other is detected.

7) Set the bit line voltage to the correction bit line voltage (S570)

If it is detected that the failed memory cell and the passed memory cells are adjacent to each other, the controller 150 sets the bit line voltage of the memory cells adjacent to the pass-through memory cells among the failed memory cells at a program allowable voltage (for example, 0 V). The page buffer unit 120 is controlled to be applied by changing the corrected bit line voltage. In addition, the controller 150 controls the buffer unit 120 to apply the bit line of the memory cells passed from the program permission voltage to the program prohibition voltage (eg, VCC).

The correction bit line voltage may be set based on the correction bit line voltage data ΔV_DATA read by the cam cell unit 140. The correction bit line voltage is preferably higher than the program allowance voltage (0V) and lower than the program prohibition voltage (VCC). The correction bit line voltage may be a difference value ΔV obtained by subtracting the threshold voltage value V ABL from the threshold voltage value V EOBL during the operation of the correction bit line setting operation.

Among the failed memory cells, the pass-through memory cell is applied by changing the bit line voltage of the adjacent memory cells from the program allowable voltage (for example, 0V) to the corrected bit line voltage (ΔV), so that the program inhibit voltage is applied to the adjacent memory cells. Even when applied and an interference phenomenon occurs, the potential of the bit line of the failed memory cell is changed from a program allowable voltage to a corrected bit line voltage, thereby suppressing an increase in the threshold voltage distribution due to the interference phenomenon. In addition, since the corrected bit line voltage data ΔV_DATA can be estimated based on the effective field oxide film height of the memory cells, and the corrected bit line voltage can be set based on the corrected bit line voltage data ΔV_DATA, each nonvolatile memory device has a different effective field oxide film height. In addition, the correction bit line voltage optimized for each nonvolatile memory device can be set.

7) Increase Program Voltage (S580)

After the program voltage Vpgm applied to the selected word line of the memory cell block 110 is set to a new program voltage increased by a step voltage, the program voltage application step S540 is repeated.

According to an exemplary embodiment of the present invention, a correction bit optimized for each chip by applying a bit line potential of a failed memory cell adjacent to a passed memory cell during a program operation by changing from a program allowable voltage (0 V) to a correction bit line voltage. The phenomenon that the threshold voltage distribution of the memory cell is degraded by the line voltage is improved.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.

110: memory cell block 120: page buffer unit
130: comparison unit 140: cam cell unit
150 control unit 160 voltage providing unit

Claims (18)

A memory cell block including memory cells coupled to the even and odd bit lines;
A page buffer unit including a plurality of page buffers respectively connected to the even and odd bit lines; And
When a program inhibit voltage is applied to a bit line of the second memory cell when the second memory cell adjacent to the first memory cell in which the program operation is not completed is applied, the voltage applied to the bit line of the first memory cell is decreased. And a controller for controlling the page buffer to change from a program allowable voltage to a corrected bit line voltage.
The method of claim 1,
The correction bit line voltage is a first threshold voltage value of the memory cells when the memory cell block is programmed in an EOBL (Even odd bit line) method, and the memory cell block is programmed in an ABL (All bit line) program method. The nonvolatile memory device may be set according to a difference between the second threshold voltage values of the memory cells in one case.
3. The method of claim 2,
And the page buffer unit measures and outputs the first threshold voltage value and the second threshold voltage value.
The method of claim 3, wherein
A comparator for generating correction voltage information by comparing the first threshold voltage value with the second threshold voltage value; And
And a cam cell unit for storing the correction voltage information.
The method of claim 4, wherein
And the control unit sets the correction bit line voltage according to the correction voltage information.
The method of claim 4, wherein
And the correction voltage information is changed according to an effective field oxide height of the memory cells included in the memory cell block.
The method of claim 1,
The program operation may be performed by using an all bit line program.
After performing a first test program on the memory cells included in the memory cell block using an ABL program method, measuring threshold voltage values of the memory cells and storing the first threshold voltage values as the first threshold voltage value;
After a second test program of the memory cells using an EOBL (Even odd bit line) method, measuring and storing a threshold voltage value of the memory cells as a second threshold voltage value; And
Generating and storing data of a correction bit line voltage according to a difference between the first threshold voltage value and the second threshold voltage value.
The method of claim 8,
The correction bit line voltage is a voltage for applying to a bit line of memory cells of which memory cells are not programmed, among memory cells adjacent to the programmed memory cell.
The method of claim 8,
The programming of the memory cells in an ABL program method may include programming the memory cells with the same data.
The storing of the first threshold voltage value may include measuring threshold voltage values of the memory cells and storing the average voltage values as the first threshold voltage value.
11. The method of claim 10,
The programming of the memory cells by the EOBL program method may include programming the memory cells with the same data as the ABL program method.
The storing of the second threshold voltage value may include measuring threshold voltage values of the memory cells and storing the average voltage values as the second threshold voltage values as average values thereof.
The method of claim 8,
And after the storing of the first threshold voltage value, erasing the memory cell block.
The method of claim 8,
Generating and storing corrected bit line voltage data, and further including a normal program step of programming the memory cell block using the ABL method,
The normal program step may include setting a correction bit line voltage using the stored correction bit line voltage data;
Inputting program data to be programmed into the memory cell block into a page buffer;
Setting potentials of bit lines of the memory cell block according to the program data;
Programming by applying a program voltage to the memory cell block;
Performing a verify operation to determine programmed memory cells and memory cells in which a program is not completed;
If it is determined as a fail during the verification operation, detecting cells adjacent to a memory cell in which the program is completed among memory cells in which the program is not completed;
Applying a program inhibit voltage to a bit line connected to the memory cell in which the program is completed, and applying the correction bit line voltage to a bit line of cells adjacent to the memory cell in which the program is completed among the memory cells in which the program is not completed; And
And applying the new program voltage having the program voltage increased to the memory cell block and re-executing the program from the programming step.
Controlling the potential of the bit lines in accordance with program data for storage in the memory cells;
Applying a program voltage to the memory cells to perform a program operation;
Performing a verify operation to confirm whether the memory cells are programmed;
If it is determined that the verification operation is a fail, detecting memory cells adjacent to the memory cell in which the program is completed among memory cells in which the program is not completed;
A program inhibit voltage is applied to a bit line connected to the memory cell in which the program is completed, and correction is performed according to the correction bit line voltage data stored in the cam cell in the bit line of cells adjacent to the program memory cell among the memory cells in which the program is not completed. Setting a bit line voltage; And
And applying the new program voltage having the program voltage increased to perform the program operation from the program operation.
15. The method of claim 14,
The correction bit line voltage data uses a first threshold voltage value of the memory cells when the memory cells are tested by the EOBL method and a second threshold voltage value of the memory cells when the memory cells are tested by the ABL method. Method of operating a nonvolatile memory device generated by.
The method of claim 15,
The correction bit line voltage data indicates information on a difference value obtained by subtracting the second threshold voltage value from the first threshold voltage value.
17. The method of claim 16,
And the correction bit line voltage is the difference value.
The method of claim 15,
And the correction bit line voltage data is changed according to an effective field oxide height of the memory cells.
KR1020110138201A 2011-12-20 2011-12-20 Non volatile memory device and operating method thereof KR20130070926A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9336877B2 (en) 2013-12-24 2016-05-10 Samsung Electronics Co., Ltd. Nonvolatile memory device using variable resistive element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9336877B2 (en) 2013-12-24 2016-05-10 Samsung Electronics Co., Ltd. Nonvolatile memory device using variable resistive element

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