KR20130070926A - Non volatile memory device and operating method thereof - Google Patents
Non volatile memory device and operating method thereof Download PDFInfo
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- KR20130070926A KR20130070926A KR1020110138201A KR20110138201A KR20130070926A KR 20130070926 A KR20130070926 A KR 20130070926A KR 1020110138201 A KR1020110138201 A KR 1020110138201A KR 20110138201 A KR20110138201 A KR 20110138201A KR 20130070926 A KR20130070926 A KR 20130070926A
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- program
- bit line
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- voltage
- memory cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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Abstract
Description
The present invention relates to a nonvolatile memory device and a method of operating the same, and more particularly, to a nonvolatile memory device and a method of operating the threshold voltage distribution characteristics of the memory cells can be improved.
There is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function that rewrites data at regular intervals. Here, the program refers to an operation of writing data to a memory cell. The NAND flash memory device of the nonvolatile memory device has a large capacity because a plurality of memory cells are connected in series to form a single cell string by sharing drains or sources between adjacent cells. There is an advantage that is suitable for storing information.
1 is a block diagram illustrating a nonvolatile memory device according to the prior art.
Referring to FIG. 1, a nonvolatile memory device includes a
The
In the conventional method of programming a nonvolatile memory device, program data is temporarily stored in a plurality of page buffers PB1 to PBk, and then the potential of each bit line is controlled according to the program data. Thereafter, a program voltage is applied to the selected word line (eg, WL <0>) of the
Subsequently, when the threshold voltage of the memory cell MC0 connected to the selected word line WL <0> rises above the verify voltage by performing a program verify operation, it is determined as a pass. Thereafter, a program inhibit voltage (for example, VCC) is applied to a bit line connected to the memory cell determined as a pass as a result of a program verifying operation to boost a channel of the corresponding string, and then the program voltage selected as the word line WL <0. Re-apply to ") to program the remaining memory cells that have not yet been programmed.
The program operation of the nonvolatile memory device according to the related art may cause the following problems.
When a program inhibit voltage is applied to a bit line connected to a memory cell determined as a pass as a result of a program verifying operation, a coupling phenomenon occurs due to a potential difference between a string of which a channel is boosted and an adjacent bit line. This causes a problem that the program speed of the memory cell included in the string adjacent to the channel where the channel is boosted increases. As a result, the threshold voltage distribution of the memory cells may be degraded.
An embodiment of the present invention provides a nonvolatile memory device and a method of operating the same in which threshold voltage distribution characteristics of memory cells are improved during a program operation.
In an embodiment, a nonvolatile memory device may include a memory cell block including memory cells connected to an even and odd bit lines, and a page buffer unit including a plurality of page buffers respectively connected to the even and odd bit lines. And a voltage applied to the bit line of the first memory cell when the program inhibit voltage is applied to the bit line of the second memory cell when the second memory cell adjacent to the first memory cell which is not completed the program operation is programmed. And a controller for controlling the page buffer to change from the program allowable voltage to the corrected bit line voltage.
In an operating method of a nonvolatile memory device according to an embodiment of the present invention, after programming memory cells included in a memory cell block using an ABL program, a threshold voltage value of the memory cells is measured. Storing the threshold voltage value, programming the memory cells in an EOBL (Even odd bit line) method, and measuring the threshold voltage value of the memory cells and storing the threshold voltage value as a second threshold voltage value; and Generating and storing data of a correction bit line voltage by using a threshold voltage value and the second threshold voltage value.
A method of operating a nonvolatile memory device according to another embodiment of the present invention includes controlling a potential of bit lines according to program data for storing in memory cells, and applying a program voltage to the memory cells to perform a program operation. Performing a verify operation to check whether the memory cells have been programmed; and if it is determined that the verify operation has failed, detecting memory cells adjacent to a program cell in which the program is not completed; And a program inhibit voltage is applied to a bit line connected to the memory cell in which the program is completed, and a correction bit line voltage stored in the cam cell part in a bit line of cells adjacent to the memory cell in which the program is completed among the memory cells in which the program is not completed. Corrected according to the data Setting a bit line voltage, and applying a new program voltage to which the program voltage is raised and re-starting the program operation.
The present technology improves the threshold voltage distribution characteristic of memory cells during a program operation by controlling the bit line voltage to compensate for coupling by adjacent strings.
1 is a block diagram of a nonvolatile memory device according to the prior art.
2 is a block diagram of a nonvolatile memory device according to the present invention.
3 is a flowchart illustrating a method of setting a correction bit line voltage of a nonvolatile memory device according to the present invention.
4 is a graph illustrating a threshold voltage difference according to a program method.
5 is a flowchart illustrating a program method of a nonvolatile memory device according to the present invention.
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.
2 is a block diagram of a nonvolatile memory device according to the present invention.
Referring to FIG. 2, the
The
The
Each page buffer temporarily stores data for programming in a selected memory cell among memory cells connected to a corresponding bit line during a program operation, and then controls a potential of the corresponding bit line according to the stored data. Also, in each page buffer, the memory cell connected to the adjacent bit line during the program operation is completed and the voltage applied to the bit line is changed from the program allowable voltage (for example, 0V) to the program inhibit voltage (for example, VCC). In this case, it is programmed by applying a correction bit line voltage in which the potential of the bit line corresponding to the page buffer is increased by the correction voltage (ΔV) from the program allowable voltage.
The
The
The
The
3 is a flowchart illustrating a method of setting a correction bit line voltage of a nonvolatile memory device according to the present invention.
4 is a graph illustrating a threshold voltage difference according to a program method.
A method of setting a correction bit line voltage of a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. 2 through 4 as follows.
1) ABL program (S310)
After program data is temporarily stored in all page buffers PB1 to PBk of the
Thereafter, a pass voltage and a program voltage are selectively applied to word lines WL <n: 0> of the
The above-described ABL program is a program operation for setting the correction bit line voltage, and the program data may be set to have the same data value.
2) Threshold voltage value measurement (S320)
After the above-described ABL program operation, the threshold voltage value V ABL of the programmed memory cells is measured using the
3) EOBL Program (S330)
After the above-described step of measuring the threshold voltage value (S320), data programmed in the
Thereafter, according to the program data stored in the page buffers (PB2, PB4, ...) connected to the odd bit lines (BL2, BL4, ...), the corresponding bit line to the program allowable potential level (for example, 0V). Set it. Thereafter, a pass voltage and a program voltage are selectively applied to word lines WL <n: 0> of the
4) Threshold voltage value measurement (S340)
After the above-described EOBL program operation, the threshold voltage value V EOBL of the programmed memory cells is measured using the
5) Correction bit line voltage setting (S350)
The
The correction bit line voltage data ΔV_DATA is obtained by subtracting the threshold voltage value V EOBL of the memory cells after the EOBL program operation from the difference value ΔV obtained by subtracting the threshold voltage value V ABL of the memory cells after the ABL program operation. Indicates.
Referring to FIG. 4, the threshold voltage value of the memory cells due to the EOBL program operation is higher than the threshold voltage value of the memory cells due to the ABL program operation. The ABL program operation simultaneously programs memory cells connected to the even bit line and the odd bit line, so that there is little influence on interference by adjacent cells. However, since the EOBL program operation programs memory cells connected to the even bit line and memory cells connected to the odd bit line separately, the EOBL program operation is affected by the interference caused by adjacent memory cells when the memory cell is programmed. That is, when programming memory cells connected to the even bit line, a program inhibit voltage is applied to the odd bit line adjacent to the even bit line to boost the channel. As a result, the memory cells connected to the even bit line are affected by the interference by the channel of the adjacent memory cells. Accordingly, the correction bit line voltage data ΔV_DATA represents an interference influence value due to a channel of adjacent memory cells. This interference effect is changed according to the effective field oxide height (EFH) of the memory cell. Therefore, the correction bit line voltage data ΔV_DATA may be used as data for estimating the effective field oxide height of the memory cells included in the
6) Store the correction bit line voltage value in the cam cell unit (S360)
The
5 is a flowchart illustrating a program method of a nonvolatile memory device according to the present invention.
A program operation of the nonvolatile memory device in which the above-described correction bit line voltage data ΔV_DATA is stored in the
1) Read the cam cell part (S510)
The
2) Program data input (S520)
Program data for programming the
3) Bit line voltage setting according to program data (S530)
Each page buffer PB1 to PBk controls the potential of the corresponding bit line according to the temporarily stored program data.
4) Program voltage application (S540)
The
5) Verification operation (S550)
Each page buffer PB1 to PBk senses the potential of the corresponding bit line to determine whether the memory cells have been programmed above the target threshold voltage value. That is, when the memory cell is programmed to have a threshold voltage value greater than or equal to the target threshold voltage value, it is determined as a pass and it is determined as a fail so as to have a threshold voltage value lower than the target threshold voltage value.
If the number of memory cells determined as fail is larger than the number of error correction bits that can be processed by the error correction circuit (ECC), it is determined as a program fail, and the number of memory cells determined as fail is greater than the number of error correction bits. If it is small, it is determined as a program pass.
6) Checking Program Status of Failed Memory Cells and Adjacent Memory Cells (S560)
If it is determined that the program fails as a result of the verification operation described above, the
7) Set the bit line voltage to the correction bit line voltage (S570)
If it is detected that the failed memory cell and the passed memory cells are adjacent to each other, the
The correction bit line voltage may be set based on the correction bit line voltage data ΔV_DATA read by the
Among the failed memory cells, the pass-through memory cell is applied by changing the bit line voltage of the adjacent memory cells from the program allowable voltage (for example, 0V) to the corrected bit line voltage (ΔV), so that the program inhibit voltage is applied to the adjacent memory cells. Even when applied and an interference phenomenon occurs, the potential of the bit line of the failed memory cell is changed from a program allowable voltage to a corrected bit line voltage, thereby suppressing an increase in the threshold voltage distribution due to the interference phenomenon. In addition, since the corrected bit line voltage data ΔV_DATA can be estimated based on the effective field oxide film height of the memory cells, and the corrected bit line voltage can be set based on the corrected bit line voltage data ΔV_DATA, each nonvolatile memory device has a different effective field oxide film height. In addition, the correction bit line voltage optimized for each nonvolatile memory device can be set.
7) Increase Program Voltage (S580)
After the program voltage Vpgm applied to the selected word line of the
According to an exemplary embodiment of the present invention, a correction bit optimized for each chip by applying a bit line potential of a failed memory cell adjacent to a passed memory cell during a program operation by changing from a program allowable voltage (0 V) to a correction bit line voltage. The phenomenon that the threshold voltage distribution of the memory cell is degraded by the line voltage is improved.
Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.
110: memory cell block 120: page buffer unit
130: comparison unit 140: cam cell unit
150
Claims (18)
A page buffer unit including a plurality of page buffers respectively connected to the even and odd bit lines; And
When a program inhibit voltage is applied to a bit line of the second memory cell when the second memory cell adjacent to the first memory cell in which the program operation is not completed is applied, the voltage applied to the bit line of the first memory cell is decreased. And a controller for controlling the page buffer to change from a program allowable voltage to a corrected bit line voltage.
The correction bit line voltage is a first threshold voltage value of the memory cells when the memory cell block is programmed in an EOBL (Even odd bit line) method, and the memory cell block is programmed in an ABL (All bit line) program method. The nonvolatile memory device may be set according to a difference between the second threshold voltage values of the memory cells in one case.
And the page buffer unit measures and outputs the first threshold voltage value and the second threshold voltage value.
A comparator for generating correction voltage information by comparing the first threshold voltage value with the second threshold voltage value; And
And a cam cell unit for storing the correction voltage information.
And the control unit sets the correction bit line voltage according to the correction voltage information.
And the correction voltage information is changed according to an effective field oxide height of the memory cells included in the memory cell block.
The program operation may be performed by using an all bit line program.
After a second test program of the memory cells using an EOBL (Even odd bit line) method, measuring and storing a threshold voltage value of the memory cells as a second threshold voltage value; And
Generating and storing data of a correction bit line voltage according to a difference between the first threshold voltage value and the second threshold voltage value.
The correction bit line voltage is a voltage for applying to a bit line of memory cells of which memory cells are not programmed, among memory cells adjacent to the programmed memory cell.
The programming of the memory cells in an ABL program method may include programming the memory cells with the same data.
The storing of the first threshold voltage value may include measuring threshold voltage values of the memory cells and storing the average voltage values as the first threshold voltage value.
The programming of the memory cells by the EOBL program method may include programming the memory cells with the same data as the ABL program method.
The storing of the second threshold voltage value may include measuring threshold voltage values of the memory cells and storing the average voltage values as the second threshold voltage values as average values thereof.
And after the storing of the first threshold voltage value, erasing the memory cell block.
Generating and storing corrected bit line voltage data, and further including a normal program step of programming the memory cell block using the ABL method,
The normal program step may include setting a correction bit line voltage using the stored correction bit line voltage data;
Inputting program data to be programmed into the memory cell block into a page buffer;
Setting potentials of bit lines of the memory cell block according to the program data;
Programming by applying a program voltage to the memory cell block;
Performing a verify operation to determine programmed memory cells and memory cells in which a program is not completed;
If it is determined as a fail during the verification operation, detecting cells adjacent to a memory cell in which the program is completed among memory cells in which the program is not completed;
Applying a program inhibit voltage to a bit line connected to the memory cell in which the program is completed, and applying the correction bit line voltage to a bit line of cells adjacent to the memory cell in which the program is completed among the memory cells in which the program is not completed; And
And applying the new program voltage having the program voltage increased to the memory cell block and re-executing the program from the programming step.
Applying a program voltage to the memory cells to perform a program operation;
Performing a verify operation to confirm whether the memory cells are programmed;
If it is determined that the verification operation is a fail, detecting memory cells adjacent to the memory cell in which the program is completed among memory cells in which the program is not completed;
A program inhibit voltage is applied to a bit line connected to the memory cell in which the program is completed, and correction is performed according to the correction bit line voltage data stored in the cam cell in the bit line of cells adjacent to the program memory cell among the memory cells in which the program is not completed. Setting a bit line voltage; And
And applying the new program voltage having the program voltage increased to perform the program operation from the program operation.
The correction bit line voltage data uses a first threshold voltage value of the memory cells when the memory cells are tested by the EOBL method and a second threshold voltage value of the memory cells when the memory cells are tested by the ABL method. Method of operating a nonvolatile memory device generated by.
The correction bit line voltage data indicates information on a difference value obtained by subtracting the second threshold voltage value from the first threshold voltage value.
And the correction bit line voltage is the difference value.
And the correction bit line voltage data is changed according to an effective field oxide height of the memory cells.
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Cited By (1)
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US9336877B2 (en) | 2013-12-24 | 2016-05-10 | Samsung Electronics Co., Ltd. | Nonvolatile memory device using variable resistive element |
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US9336877B2 (en) | 2013-12-24 | 2016-05-10 | Samsung Electronics Co., Ltd. | Nonvolatile memory device using variable resistive element |
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