KR20130067822A

KR20130067822A - Diode

Info

Publication number: KR20130067822A
Application number: KR1020110134775A
Authority: KR
Inventors: 서덕원
Original assignee: 엘지이노텍 주식회사
Priority date: 2011-12-14
Filing date: 2011-12-14
Publication date: 2013-06-25

Abstract

PURPOSE: A diode is provided to increase the breakdown voltage by speeding up the operational speed and preventing the concentration of the electric field. CONSTITUTION: A compound semiconductor layer is arranged on a substrate. Multiple trenches(140) are arranged in the compound semiconductor layer. A first insulating layer(171) is arranged on the lower part of the trench. A Schottky metal layer(150) is in contact with the side of the trenches. The compound semiconductor layer includes one or more p regions.

Description

Diode {DIODE}

Embodiments relate to Schottky diodes.

Diodes are one of the most widely used devices for low-voltage switching, power supplies, power converters and related applications. For efficient operation, it is desired that the diode have a low on-state voltage (0.1V to 0.2V or less), low reverse leakage current, high breaking capacity and high switching speed.

The most common diodes are pn junction diodes made of silicon and introduced with impurity elements to alter the diode's operating characteristics in a controlled manner.

A special type of diode consisting of a metal-to-semiconductor barrier region instead of a Schottky diode pn junction. Schottky diodes have a good operating speed, but have a low breakdown voltage (BV).

The embodiment provides a diode having a low operating voltage VF and a high breakdown voltage BV.

The diode according to the embodiment may include a substrate doped with n +, a compound semiconductor layer disposed on the substrate and doped with n−, a plurality of trenches disposed in the compound semiconductor layer, and a first insulation disposed below the trench. And a Schottky metal layer disposed over the compound semiconductor layer and in contact with at least the sides of the trenches, wherein the compound semiconductor layer includes at least one or more p-regions doped in a p-type at least in a portion of the upper portion can do.

The diode in the embodiment can have a high operating speed, low operating voltage VF, and breakdown voltage BV.

In addition, since the concentration of the electric field can be prevented, the reliability of the diode can be improved.

1 is a cross-sectional view illustrating a diode according to an embodiment.
FIG. 2 is an exploded perspective view of the diode shown in FIG. 1. FIG.
3 is a cross-sectional view illustrating a diode according to another embodiment.
4 is an exploded perspective view illustrating a diode according to another embodiment.
5 is an exploded perspective view illustrating a diode according to another embodiment.
6 is an exploded perspective view illustrating a diode according to another embodiment.
7 to 10 are flowcharts illustrating a method of manufacturing a diode according to an embodiment.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when flipping a device shown in the figure, a device described as "below" or "beneath" of another device may be placed "above" of another device. Thus, the exemplary term "below" can include both downward and upward directions. The device can also be oriented in other directions, so that spatially relative terms can be interpreted according to orientation.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. Also, the size and area of each component do not entirely reflect actual size or area.

Further, the angle and direction mentioned in the description of the structure of the light emitting device in the embodiment are based on those shown in the drawings. In the description of the structure of the light emitting device in the specification, reference points and positional relationship with respect to angles are not explicitly referred to, refer to the related drawings.

1 is a cross-sectional view of a diode according to an embodiment, and FIG. 2 is an exploded perspective view of the diode shown in FIG. 1.

1 and 2, the diode 100 of the embodiment includes a substrate 110, a plurality of trenches 140 formed in the compound semiconductor layer 120, a compound semiconductor layer 120 on the substrate 110, The Schottky metal layer 150 disposed on the first insulating layer 171 and the compound semiconductor layer 120 disposed under the plurality of trenches 140 and in contact with at least the side surfaces of the trenches 140 may be included. have. Here, the compound semiconductor layer 120 may include a p region 130.

Here, the substrate 110 may include SiC. However, the present invention is not limited thereto, and may include any one of sapphire (Al ₂ O ₃ ), GaN, ZnO, and AlO, but SiC has excellent thermal conductivity and high breakdown voltage (BV). The SiC substrate is usually silicon carbide 4H polytype. Also, 3C, 6H and 15R polytypes can be used.

The substrate 110 may be doped with n +. That is, the substrate 110 may be highly doped to a concentration of at least 10 ¹⁸ per cm ³ . In other words, the compound semiconductor layer 120 may have a higher doping concentration than the doping concentration. The substrate 110 may have a thickness of about 0.1 μm to about 0.5 μm. However, the present invention is not limited thereto.

Meanwhile, an ohmic layer 160 may be further included below the substrate 110. The ohmic layer 160 is in ohmic contact with the bottom surface of the substrate 110 and may be formed in a layer or a plurality of patterns. As the ohmic layer (not shown), a metal may be used. For example, the ohmic layer (not shown) may be implemented as a single layer or a multilayer using one or more of Pt, Ni, Ag, Ni / IrO _x / Au, and Ni / IrO _x / Au / ITO. Can be.

The compound semiconductor layer 120 may be disposed on the substrate 110. In the compound semiconductor layer 120, the substrate 110 may be doped with n +. That is, the compound semiconductor layer 120 may be doped to a doping concentration of impurities up to a concentration of 5 × 10 ¹⁴ to 5 × 10 ¹⁷ per cm ³ . In other words, the doping concentration may be lower than that of the substrate 110. In addition, the thickness of the compound semiconductor layer 120 may be 0.5 μm to 1 μm. However, the present invention is not limited thereto.

The trenches 140 may be located in the compound semiconductor layer 120.

The trenches 140 may be formed as strips extending in parallel to each other in the compound semiconductor layer 120. Alternatively, the trenches 140 may be arranged in the compound semiconductor layer 120 in an island shape or a checkerboard shape. The cross-section of the trenches 140, which are arranged in a checkerboard pattern, may have a regular cross-section, i.e., a cross-section such as a circle, hexagon, etc., in the sense of good reproducibility and ease of manufacture.

When the trenches 140 are formed in parallel to form a strip, the cross-sectional shape of the trench 140 may include a U shape or a rectangle. 1, a rectangular shape is shown, but the present invention is not limited thereto. The pitches of the trenches 140 are not limited, but the same is common. The method of forming the trench 140 is not limited, but a wet etching method or a dry etching method may be used.

If the depth of the trench 140 is too deep, the thickness of the compound semiconductor layer 120 decreases, so that the breakdown voltage BV may decrease. If the depth of the trench 140 is too shallow, the schottky metal layer 150 of the compound semiconductor layer 120 Since the junction area is reduced, there is a problem that the operating voltage (VF) increases. Therefore, the thickness of the compound semiconductor layer 120 may be 30% to 50%. However, the present invention is not limited thereto. The plurality of trenches 140 increases the contact area between the Schottky metal layer 150 and the compound semiconductor layer 120 to reduce the operating voltage VF.

The first insulating layer 171 may be disposed under the trenches 140. In addition, the first insulating layer 171 may be disposed up to a partial region of the side surfaces of the trenches 140. It is not limited to this. The first insulating layer 171 may be a material having low or no electrical conductivity. For example, SiO ₂ _, SiN _X, and Al ₂ O ₃ It may include any one of. However, the present invention is not limited thereto. The shape of the first insulating layer 171 is not limited, and is generally disposed to correspond to the lower shape of the trench 140.

If the diode 100 has the trench 140 structure, the operating voltage VF decreases but the breakdown voltage BV also decreases. Since the first insulating layer 171 bypasses the current path and spreads the electric field evenly in the compound semiconductor layer 120, the breakdown voltage BV of the diode 100 may be improved.

The Schottky metal layer 150 may be disposed on the compound semiconductor layer 120 and may be in contact with at least the sides of the trenches 140. The schottky metal layer 150 may include, for example, any one of metals in the group consisting of Ti, Cr, Nb, Sn, W, Ni, Pt, and Ta. However, the present invention is not limited thereto. The schottky metal layer 150 may have a single layer or a multilayer structure.

Although the Schottky metal layer 150 is illustrated as a structure filling the entire interior of the trench 140 in FIG. 1, the Schottky metal layer 150 is not limited thereto and is positioned on the side of the trench 140, and the interior of the trench 140 may exist as an empty space. It may be.

The p region 130 may be formed in at least a portion of the upper portion of the compound semiconductor layer 120 and may be doped with a p-type. The p region 130 may be disposed adjacent to a corner portion where side surfaces of the trenches 140 and an upper surface of the compound semiconductor layer 120 meet each other. That is, the p region 130 may contact some regions of the bottom surface of the schottky metal layer 150.

If the p-type doped p region 130 exists between the compound semiconductor layer 120 and the Schottky metal layer 150, leakage current can be reduced, and electric fields are concentrated at the corners of the compound semiconductor layer 120. This can improve the breakdown voltage BV.

On the other hand, the thickness d1 of the p region 130 is not limited, but when too thick, the contact area between the Schottky metal layer 150 and the compound semiconductor layer 120 decreases, thereby increasing the operating voltage VF. And too thin, there is a problem that the breakdown voltage BV decreases. Therefore, the Schottky metal layer 150 may be 0.2 times to 0.5 times the width d2 of the side surface of the trench 140.

Although the p region 130 is not limited in arrangement, the p region 130 is not formed in all regions above the compound semiconductor layer 120 in consideration of the even distribution of the electric field and the breakdown voltage BV. It may have any one of a stripe structure, a lattice structure and an island structure at the top. In FIG. 2, the structure in which the p region 130 is disposed in parallel to the longitudinal direction of the compound semiconductor layer 120 is illustrated. Other structures will be described later.

In addition, the area of the p region 130 is not limited, but if it is too large, there is a problem that the contact area between the Schottky metal layer 150 and the compound semiconductor layer 120 decreases, thereby increasing the operating voltage VF. In the narrow case, there is a problem that the breakdown voltage BV decreases. Therefore, the area of the p region 130 may have an area of 40% to 60% of the area of the upper surface of the compound semiconductor layer 120.

Therefore, the diode 100 according to the embodiment has a high operation speed, a low operating voltage VF, and a breakdown voltage BV.

3 is a cross-sectional view illustrating a diode according to another embodiment.

Referring to FIG. 3, the diode 100A according to the embodiment further includes a second insulating layer 172A as compared to the embodiment of FIG. 1, and there is a difference in the structure of the lower portion of the trench 140A.

The second insulating layer 172A may be disposed at a position where a portion of the second insulating layer 172A is vertically overlapped with at least a portion of the p region 130 between the upper surface of the compound semiconductor layer 120 and the Schottky metal layer 150A. The second insulating layer 172A may be formed of the same material as the first insulating layer 171 described above. But is not limited thereto. The second insulating layer 172A prevents concentration of an electric field in a portion of the compound semiconductor layer 120.

The trench 140A may have a curvature at the bottom. That is, since the cross-sectional shape of the trench 140A has a U shape, the breakdown voltage BV can be improved by preventing the electric field from being concentrated in one region of the compound semiconductor layer 120.

In this case, the Schottky metal layer 150A may be disposed to correspond to the lower shape of the trench 140A. In addition, the Schottky metal layer 150A may be disposed only in a portion of the inside of the trench 140A, as shown in FIG. 3.

4 to 6 are exploded perspective views illustrating various arrangements of p regions in a diode according to another exemplary embodiment.

The area of the p region 130 is not limited. However, if the area of the p region 130 is too large, the contact area between the Schottky metal layer 150 and the compound semiconductor layer 120 decreases, thereby increasing the operating voltage VF. There is a problem that the breakdown voltage BV decreases. Therefore, the area of the p region 130 may be freely disposed while having an area of 40% to 60% of the area of the upper surface of the compound semiconductor layer 120. That is, as illustrated in FIG. 4, the p region 130B may have a stripe structure parallel to the width direction of the compound semiconductor layer 120, and as illustrated in FIG. 5, the p region 130C may be a compound semiconductor. The layer 120 may have a lattice structure. As shown in FIG. 6, a plurality of p regions 130D may be arranged in an island shape. However, the present invention is not limited thereto.

7 to 10 are flowcharts illustrating a method of manufacturing a diode according to an embodiment.

Referring to FIG. 7, first, the substrate 110 is disposed. The substrate 110 is doped with n +. There is no limitation on the doping method. In this regard, the substrate 110 may include SiC. However, the present invention is not limited thereto, and may include any one of sapphire (Al ₂ O ₃ ), GaN, ZnO, and AlO, but SiC has excellent thermal conductivity and high breakdown voltage (BV). The SiC substrate is usually silicon carbide 4H polytype. Also, 3C, 6H and 15R polytypes can be used.

Thereafter, the compound semiconductor layer 120 is grown on the substrate 110.

The compound semiconductor layer 120 may be formed of, for example, a metal organic chemical vapor deposition (MOCVD), a chemical vapor deposition (CVD), a plasma chemical vapor deposition (PECVD), or a molecular beam. Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), etc. may be formed using, but is not limited thereto. The compound semiconductor layer 120 may be doped with n−.

Thereafter, the ohmic layer 160 may be further included below the substrate 110. The ohmic layer 160 is in ohmic contact with the bottom surface of the substrate 110 and may be formed in a layer or a plurality of patterns. As the ohmic layer (not shown), a metal may be used. For example, the ohmic layer (not shown) may be implemented as a single layer or a multilayer using one or more of Pt, Ni, Ag, Ni / IrO _x / Au, and Ni / IrO _x / Au / ITO. Can be.

Referring to FIG. 8, the upper region of the compound semiconductor layer 120 is doped with a p-type.

Referring to FIG. 9, a plurality of trenches 140 may be etched into the compound semiconductor layer 120.

The etching method may be performed by dry etching or wet etching after forming the mask.

Thereafter, the first insulating layer 171 may be disposed under the plurality of trenches 140.

Referring to FIG. 10, a Schottky metal layer 150 may be formed on side surfaces of the plurality of trenches 140 and an upper surface of the compound semiconductor layer 120.

The schottky metal layer 150 may be formed by, for example, a deposition method or a plating method, but is not limited thereto.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims

a substrate doped with n +;
A compound semiconductor layer disposed on the substrate and doped with n-;
A plurality of trenches disposed in the compound semiconductor layer;
A first insulating layer disposed under the trench; And
A schottky metal layer disposed on the compound semiconductor layer and in contact with at least the sides of the trenches,
The compound semiconductor layer,
A diode comprising at least one or more p-regions doped p-type at least a portion of the upper portion.

The method of claim 1,
A diode comprising an ohmic layer under the substrate.

The method of claim 1,
The substrate comprises SiC.

The method of claim 1,
The compound semiconductor layer comprises a SiC.

The method of claim 1,
A lower portion of the trench has a curvature.

The method of claim 1,
The pitch of the trenches is the same diode.

The method of claim 1,
And the cross-sectional shape of the trenches includes a U shape or a rectangular shape.

The method of claim 1,
The trenches have a strip or lattice shape in the compound semiconductor layer.

The method of claim 1,
And a doping concentration of the substrate is greater than that of the compound semiconductor layer.

The method of claim 1,
The p region is,
And a side of the trench disposed adjacent to a corner where the top surface of the compound semiconductor layer meets.

The method of claim 1,
The p region is,
The diode having any one of a stripe structure, a lattice structure or an island structure on the compound semiconductor layer.

The method of claim 1,
And a second insulating layer partially overlapping at least partially with the p region between the upper surface of the compound semiconductor layer and the Schottky metal layer.

The method of claim 1,
The first insulating layer and the second insulating layer is SiO ₂ _, SiN _X and Al ₂ O ₃ Diode comprising any of.

The method of claim 1,
The Schottky metal layer is
A diode comprising any one of the metals of the group consisting of Ti, Cr, Nb, Sn, W, Ni, Pt, and Ta.

12. The method of claim 11,
The thickness of the p region is 0.2 to 0.5 times the width of the Schottky metal layer in contact with the side of the trench.