KR20130065947A - Semiconductor device and method for growing semiconductor crystal - Google Patents

Abstract

PURPOSE: A semiconductor device and a semiconductor crystal growth method are provided to form a pattern, which has an irregular thickness and width, on a silicon carbide substrate, thereby preventing an electrical potential defect on the substrate. CONSTITUTION: A semiconductor device comprises a base substrate(10), a pattern(30a), and an epitaxial layer(20). A pattern is made by forming a groove on the base substrate. The pattern has an irregular width between 100 and 2000 nm. The base substrate or the epitaxial layer comprises silicon carbide. The epitaxial layer is formed on a substrate exposed between the patterns.

Description

Semiconductor device and semiconductor crystal growth method {SEMICONDUCTOR DEVICE AND METHOD FOR GROWING SEMICONDUCTOR CRYSTAL}

The present disclosure relates to a semiconductor device and a semiconductor crystal growth method.

In a semiconductor device supporting a semiconductor device, reducing the crystal defects of the semiconductor layer grown on the substrate and improving the crystallinity of the semiconductor layer are the biggest research tasks for improving the efficiency and characteristics of the semiconductor device.

However, the base substrate including silicon carbide may have defects generated from the base surface of the grating, defects due to the lattice of the grating, and defects generated on the surface of the base substrate. The defects may adversely affect the semiconductor device during the epi layer growth. In addition, it may adversely affect the operation of the switching device later.

In particular, the base substrate comprising silicon carbide includes Basal Plane Dislocation (BPD). It is important to reduce the base surface potential defect (BPD) because it greatly affects the reliability of the semiconductor device.

Accordingly, in the related art, a buffer layer is formed in order to reduce dislocation defects during crystal growth, and a step of forming a pattern on the surface of the substrate using mask formation, etching, or the like is further required for the buffer layer.

Therefore, these additional processes are complicated, the cost increases, and there is a problem such as deterioration of the quality of the surface of the substrate.

Accordingly, there is a need for a semiconductor device and a semiconductor crystal growth method capable of controlling potential defects and the like of the base substrate without forming the buffer layer.

The embodiment provides a semiconductor device and a method for growing semiconductor crystals with high efficiency that can reduce process costs and improve the quality of a substrate surface.

A semiconductor device according to the embodiment includes a base substrate; A pattern formed on the base substrate; And an epitaxial layer formed on the base substrate, wherein the pattern has an irregular width within a range of 100 nm to 2000 nm.

A semiconductor crystal growth method according to an embodiment includes cleaning a silicon carbide substrate; Forming a pattern on the silicon carbide substrate; And forming an epitaxial layer on the silicon carbide substrate, wherein forming a pattern on the silicon carbide substrate includes: forming a coating layer on the silicon carbide substrate; Heat-treating the coating layer; Etching the silicon carbide substrate; And removing the coating layer.

The semiconductor device according to the embodiment may form a pattern having an irregular thickness and width on the silicon carbide substrate. Through this pattern, dislocation defects formed thereon can be suppressed. In particular, the basal plane dislocation defect (BPD) of the silicon carbide substrate has a great influence on the reliability of the semiconductor device. As a pattern is formed, such dislocation defects can be prevented from defect growth and a high quality epi thin film can be obtained.

Therefore, it is not necessary to separately form a buffer layer for suppressing such dislocation defects, so that additional processing steps such as a patterning process or a regrowth process step for forming the buffer layer can be reduced. This can reduce the process cost and process time, it is possible to improve the process efficiency.

On the other hand, in the semiconductor crystal growth method according to the embodiment, the gold or silver coating layer formed by coating the gold or silver on the silicon carbide substrate and then heat-treated to form a pattern with an irregular thickness and interval, and then subjected to the etching process A pattern having an irregular thickness and width may be formed on the base substrate. Therefore, the pattern forming operation is easy and the process cost can be reduced. In addition, damage to the surface of the substrate may be reduced due to an additional process for forming the buffer layer, thereby improving crystallinity of the semiconductor layer. As a result, a high quality semiconductor layer capable of securing reliability can be formed.

1 is a cross-sectional view of a semiconductor device according to an embodiment.
2 to 7 are cross-sectional views illustrating a semiconductor crystal growth method according to an embodiment.
8 and 9 are cross-sectional views of a semiconductor device in which electrodes are formed.

In the description of embodiments, each layer, region, pattern, or structure may be “on” or “under” the substrate, each layer, region, pad, or pattern. Substrate formed in ”includes all formed directly or through another layer. Criteria for the top / bottom or bottom / bottom of each layer will be described with reference to the drawings.

The thickness or the size of each layer (film), region, pattern or structure in the drawings may be modified for clarity and convenience of explanation, and thus does not entirely reflect the actual size.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A semiconductor device according to an embodiment will be described in detail with reference to FIG. 1.

1 is a cross-sectional view of a semiconductor device according to an embodiment.

Referring to FIG. 1, the semiconductor device according to the embodiment may include a base substrate 10, a pattern 30a, and an epi layer 20.

The base substrate 10 includes silicon carbide. Silicon carbide has a larger bandgap and a higher thermal conductivity than silicon, while carrier mobility is as large as that of silicon, and electron saturation drift rate and breakdown voltage are also large. For this reason, the material is expected to be applied to semiconductor devices requiring high efficiency, high breakdown voltage and high capacity.

The pattern 30a may be located on the base substrate 10.

The pattern 30a may be formed by forming a groove on the base substrate 10. That is, the base substrate forms a groove on the base substrate 10 to form the pattern pattern 30a.

In addition, the shape of the pattern 30a may include an ellipse shape, a square shape, a triangular shape, or a grid shape. In detail, the shape of the groove formed on the base substrate 10 may include an ellipse shape, a square shape, a triangular shape, or a grid shape.

The pattern 30a may have an irregular irregular width within a range of 100 nm to 2000 nm. That is, although the shape and shape of the pattern 30a are the same, a plurality of patterns having various widths may be formed on the base substrate 10. However, the embodiment is not limited thereto, and the shape, size, and spacing between the patterns 30a of the pattern 30a may vary depending on the distribution of defects in the base substrate 10.

The base substrate 10 including silicon carbide may have defects generated from the bottom surface of the grating, defects caused by the lattice of the grating, and defects generated on the surface of the base substrate 10. The defects may adversely affect the semiconductor device when the epitaxial layer 20 is grown. In addition, it may adversely affect the operation of the switching device later.

In particular, the base substrate 10 including silicon carbide includes Basal Plane Dislocation (BPD). It is important to reduce the base surface potential defect (BPD) because it greatly affects the reliability of the semiconductor device.

Conventionally, in order to suppress such a base surface potential defect (BPD) etc., the buffer layer was further formed in the base substrate, and the epi layer was formed on the buffer layer. That is, crystal defects are prevented due to lattice constant mismatch and thermal expansion coefficient difference existing between the base substrate and the epi layer through the buffer layer. However, in order to form such a buffer layer, an additional patterning process or a regrowth process step such as additional etching was required.

However, in the present exemplary embodiment, defect growth may be suppressed by forming the pattern 30a on the base substrate 10. That is, the base surface potential defect BPD included in the base substrate 10 may no longer be grown by the pattern 30a. In this embodiment, by controlling the base surface potential defects and the like caused by the base substrate 10, a high quality epi thin film can be obtained, and a high-performance device can be manufactured by preventing the growth of dislocation bonds that adversely affect the application of silicon carbide devices. can do.

In addition, it is possible to reduce the process cost by reducing the additional process steps for forming the buffer layer, and to increase the process efficiency.

The epi layer 20 may be located on the base substrate 10. The epi layer 20 is formed in a horizontal direction on one surface of the base substrate 10 exposed in the base substrate 10 and the pattern 30a and is formed while filling the space inside the pattern 30a. Can be.

By reducing the electric potential propagating through the epitaxial layer 20 through the pattern 30a, leakage current due to crystal defects may be greatly reduced.

Hereinafter, the semiconductor crystal growth method according to the embodiment will be described in detail with reference to FIGS. 2 to 7. For the sake of clarity and simplicity, detailed descriptions of what has already been described are omitted.

2 to 7 are cross-sectional views illustrating a semiconductor crystal growth method according to an embodiment.

A semiconductor crystal growth method according to an embodiment includes cleaning a silicon carbide substrate; Forming a pattern on the silicon carbide substrate; And forming an epitaxial layer on the silicon carbide substrate, wherein forming a pattern on the silicon carbide substrate includes: forming a coating layer on the silicon carbide substrate; Heat-treating the coating layer; Etching the silicon carbide substrate; And removing the coating layer.

In the cleaning of the silicon carbide substrate 10, the surface of the silicon carbide substrate 10 may be cleaned.

3 to 6, in the forming of the pattern 30b, the pattern 20 may be formed on the surface of the silicon carbide substrate 10. The forming of the pattern 30b may include forming a coating layer on the silicon carbide substrate; Heat-treating the coating layer; Etching the silicon carbide substrate; And removing the coating layer.

In the forming of the coating layer 40 on the silicon carbide substrate, a coating layer 40 including gold (Au) or silver (Ag) may be formed on the silicon carbide substrate. The coating layer 40 may be coated with a thickness of 50nm or more on the silicon carbide substrate. Preferably, the coating layer 40 may be coated with a thickness of 50nm to 100nm or more on the silicon carbide substrate.

Subsequently, in the heat treatment of the coating layer 40, the coating layer 40 formed on the silicon carbide substrate may be heat treated. The heat treatment temperature may be heat treated at a temperature of 200 ℃ or more. Preferably, the heat treatment temperature may be heat treatment in the temperature range of 200 ℃ to 500 ℃.

As shown in FIG. 4, according to the heat treatment, the coating layer 40 may form a predetermined pattern 30b on the silicon carbide substrate, such as nanowires grown in a bottom-up manner. That is, the coating layer 40 may be grown in a pattern 30b having a shape protruding on the silicon carbide substrate according to the heat treatment. The protruding shape of the coating layer 40 may be formed to have an irregular width and thickness within a range having a width of 100 nm to 2000 nm and a thickness of 10 nm to 200 nm. That is, the coating layer formed on the silicon carbide substrate may be deformed into a protruding shape having various sizes and widths according to the heat treatment.

Subsequently, in the etching of the silicon carbide substrate, the silicon carbide substrate may be etched. More specifically, the silicon carbide substrate may be plasma etched by heat treatment to deposit a coating layer deformed into a protruding shape having various sizes and widths. In this case, the coating layer, that is, the gold or silver coating layer may serve as a mask during plasma etching. Accordingly, the silicon carbide substrate can be plasma etched in a simple process without the need for a mask treatment or the like. The plasma etching may be etched to a depth of 50nm to 1㎛.

As shown in FIG. 5, when the silicon carbide substrate is etched, the silicon carbide substrate may have grooves between the irregular patterns 30b formed in the coating layer, and have the same width as the irregular pattern 30b. The branch pattern 30a may be formed. That is, the silicon carbide substrate may be formed with a pattern 30a having the same width as the width of the pattern 30b, the pattern is formed with a plurality of patterns having an irregular width within the range of 100nm to 2000nm Can be.

Subsequently, in the step of removing the coating layer, a gold etchant or silver etchant may be used to remove the gold or silver coating layer remaining on the silicon carbide substrate.

Through these patterns 30a, dislocation defects formed on the silicon carbide substrate may be suppressed. In particular, the basal plane dislocation defect (BPD) of the silicon carbide substrate has a great influence on the reliability of the semiconductor device. By forming the pattern 30a, the dislocation defect can be prevented from defect growth and a high quality epi thin film can be obtained.

In addition, the pattern forming operation is easy and the process cost can be reduced. In addition, damage to the surface of the substrate may be reduced due to an additional process for forming the buffer layer, thereby improving crystallinity of the semiconductor layer. As a result, a high quality semiconductor layer capable of securing reliability can be formed.

Subsequently, referring to FIG. 6, forming an epitaxial layer 20. The epitaxial layer 20 may be formed on the silicon carbide substrate. The epi layer 20 may be formed on the surface of the substrate exposed inside the pattern 30a.

Although not illustrated, a channel region (not shown) may be formed by implanting impurities into the epitaxial layer 20.

The epitaxial layer 20 is formed through an epitaxial lateral over growth (ELOG). This lateral growth method may use a process such as conventional organic organic vapor deposition (MOCVD), molecular beam epitaxy (MBE). The organometallic vapor deposition method is a method of growing a desired thin film by sending a vapor of a metal organic compound having a high vapor pressure to a heated substrate surface in a chamber, and thus has an advantage of shortening the process time due to the fast deposition rate. Molecular beam growth method is a method of stacking a variety of growth materials in the form of molecules to deposit a desired material on a substrate to have a slow growth rate but excellent quality. However, since the embodiment is not limited thereto, the epitaxial layer 30 may be formed by various growth methods.

Although not shown, a thick film semiconductor growth layer may be further formed on the epitaxial layer 20.

In the semiconductor crystal growth method according to the embodiment, an additional process such as formation of a buffer layer for suppressing defect growth may be omitted, and thus damage to the substrate surface may be reduced, thereby improving crystallinity of the semiconductor layer. As a result, a high quality semiconductor layer capable of securing reliability can be formed.

Hereinafter, the structure of the vertical semiconductor device and the horizontal semiconductor device will be described with reference to FIGS. 8 and 9. 8 and 9 are cross-sectional views of a semiconductor device.

As shown in FIG. 8, the electrodes 50a and 60a may be formed on the bottom surface of the base substrate 10 and the top surface of the epi layer 20.

The electrodes 50a and 60a may include at least one of a metal material such as silver (Ag), copper (Cu), nickel (Ni), aluminum (Al), zinc (Zn), or an alloy thereof, and a vacuum. It may be formed by a method such as a vapor deposition method.

Next, the semiconductor element shown in FIG. 9 is a horizontal semiconductor element.

Referring to FIG. 9, electrodes 50b and 60b are formed on the epitaxial layer 20. The electrodes 50b and 60b have a horizontal structure arranged almost horizontally on the upper surface of the epi layer 20.

However, the embodiment is not limited thereto and may be applied to various semiconductor devices using the semiconductor crystal growth method.

The features, structures, effects and the like described in the foregoing embodiments are included in at least one embodiment of the present invention and are not necessarily limited to one embodiment. In addition, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the present invention. It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments may be modified. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

Claims (10)

A base substrate;
A pattern formed on the base substrate; And
An epi layer formed on the base substrate,
The pattern is a semiconductor device having an irregular width in the range of 100nm to 2000nm. The method of claim 1,
The base substrate or the epi layer comprises a silicon carbide. The method of claim 1,
The epi layer is formed on the surface of the substrate exposed between the pattern. Cleaning the silicon carbide substrate;
Forming a pattern on the silicon carbide substrate; And
Forming an epitaxial layer on the silicon carbide substrate,
Forming a pattern on the silicon carbide substrate,
Forming a coating layer on the silicon carbide substrate;
Heat-treating the coating layer;
Etching the silicon carbide substrate; And
Removing the coating layer; 5. The method of claim 4,
The coating layer is a semiconductor crystal growth method comprising gold (Au) or silver (Ag). 5. The method of claim 4,
The coating layer is a semiconductor crystal growth method is coated to a thickness of 50nm to 100nm. 5. The method of claim 4,
The coating layer is a semiconductor crystal growth method of heat treatment at a temperature of 200 ℃ to 500 ℃. 5. The method of claim 4,
The etching comprises plasma etching,
The etching is a semiconductor crystal growth method for etching to a depth of 50nm to 1㎛. 5. The method of claim 4,
The forming of the epitaxial layer is a semiconductor crystal growth method performed by a side growth method (Epitaxy Lateral Over Growth, ELOG). 5. The method of claim 4,
The pattern has a semiconductor crystal growth method having an irregular width in the range of 100nm to 2000nm.

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