KR20130065243A - Oxide semiconductor transistor and manufacturing method thereof - Google Patents

Abstract

PURPOSE: An oxide semiconductor transistor and a manufacturing method thereof are provided to improve stability by irradiating high energy electronic beam to the oxide semiconductor transistor. CONSTITUTION: A buffer layer(12) is formed on the front side of a glass substrate. A source electrode(13a) and a drain electrode(13b) are formed using a magnetron sputtering method. An IGZO layer is formed in the thickness of 20 to 40nm using an RF magnetron sputtering method. An alumina(Al2O3) layer in the thickness of 6 to 12nm is formed on the front side of the IGZO layer. A gate insulating layer(16) is formed on the front side of the buffer layer with a protective layer using an ALD method. A gate electrode(17a) is formed by patterning an ITO layer after applying the ITO layer in the thickness of 130 to 170nm.

Description

Oxide semiconductor transistor and manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oxide semiconductor transistor and a method for manufacturing the same, and more particularly, to an oxide semiconductor transistor and a method for manufacturing the same having improved safety by irradiating a high energy electron beam to the oxide semiconductor transistor.

Flat panel display (FPD) has a very high share in the display market due to its very thin and light advantage. FPD is required for large area and high image quality with increasing market share. Furthermore, FPD can be processed at low temperature to be applied to lighter, thinner, flexible or rollable flexible display. This guaranteed backplane technology is required.

There are silicon-based thin film transistors (TFTs) and oxide semiconductor transistors that use amorphous silicon (a-Si) or polysilicon (poly-Si) as a switching or driving device used as a backplane of a display. . Amorphous silicon (a-Si) thin film transistors of silicon (Si) based thin film transistors are easy to manufacture but have low electron mobility.

Poly-Si thin film transistor has higher electron mobility than amorphous silicon (a-Si) thin film transistor, so it can be applied to high-definition display with large area and high stability, but it is complicated in manufacturing process and high in manufacturing cost. There is a problem in that a compensation circuit is required due to nonuniformity of device characteristics.

Oxide semiconductor TFTs have been developed to solve such drawbacks of silicon (Si) based TFTs.

Korean Patent Registration No. 857455 The prior art described in the literature relates to an oxide semiconductor transistor, which can reduce the off-current of a transistor and to manufacture a thin film transistor for forming and patterning a protective film on an oxide semiconductor film capable of improving electron mobility. It is about a method. As in the prior art, oxide semiconductor transistors have much higher electron mobility than silicon (Si) based thin film transistors, which is suitable for realizing a large-area high-definition display. It's going on.

As described above, although oxide semiconductor transistors have very high electron mobility, technology development for applying them to display backplanes is in progress, but there is a problem that stability is not secured. In other words, the gate bias is relatively stable, but the characteristics of the gate bias and light vary greatly.

SUMMARY OF THE INVENTION An object of the present invention is to provide an oxide semiconductor transistor and a method for manufacturing the same, which are designed to solve the above object and improve safety by irradiating a high energy electron beam to an oxide semiconductor transistor.

The oxide semiconductor transistor of the present invention is an oxide semiconductor transistor having an active layer made of IGZO (InGaZnO) material, wherein an electron beam having an energy of 0.01 to 10 MeV is irradiated to the active layer made of IGZO (InGaZnO) material of the oxide semiconductor transistor. It features.

A method of manufacturing an oxide semiconductor transistor of the present invention comprises the steps of providing a glass substrate; Forming a buffer layer on the entire surface of the glass substrate by applying a silicon oxide film (SiO ₂ ) to a thickness of 10 to 20 nm using an atomic layer deposition (ALD) method; Applying an indium tin oxide (ITO) layer to a thickness of 130 to 170 nm using a radio frequency (RF) magnetron sputtering method on the entire surface of the buffer layer, and patterning the ITO layer to form a source electrode and a drain electrode; Forming an IGZO (InGaZnO) layer with a thickness of 20 to 40 nm on an entire surface of the buffer layer on which the source electrode and the drain electrode are formed by using an RF magnetron sputtering method; Forming an alumina (Al ₂ O ₃ ) layer having a thickness of 6 to 12 nm on an entire surface of the IGZO layer by using an ALD method; Patterning the alumina (Al ₂ O ₃ ) layer to form a protective layer; Patterning the IGZO layer to form an active layer; Forming a gate insulating layer by coating an alumina (Al ₂ O ₃ ) on the entire surface of the buffer layer on which the protective layer is formed to have a thickness of 150 to 200 nm ; Forming a gate electrode by applying an ITO layer to a thickness of 130 to 170 nm on an entire surface of the buffer layer on which the gate insulating layer is formed using an RF magnetron sputtering method, and then patterning the ITO layer; And irradiating an electron beam to the active layer by irradiating an electron beam using an electron beam accelerator to the gate electrode and the gate insulating layer, respectively.

The oxide semiconductor transistor of the present invention and a method of manufacturing the same have an advantage of improving safety by irradiating a high energy electron beam to the oxide semiconductor transistor.

1 is a front sectional view of an oxide semiconductor transistor of the present invention;
2 to 11 are cross-sectional views illustrating a manufacturing process of the oxide semiconductor transistor illustrated in FIG. 1, respectively.
12 is a graph showing the electrical characteristics of the oxide semiconductor transistor of the present invention irradiated with an electron beam,
13 is a graph showing electrical characteristics of an oxide semiconductor transistor not irradiated with an electron beam.

Hereinafter, an embodiment of an oxide semiconductor transistor of the present invention will be described with reference to the accompanying drawings.

The oxide semiconductor transistor 10 of the present invention is an oxide semiconductor transistor 10 having an active layer 14a made of IGZO (InGaZnO) material as shown in FIG. 1, and has an energy of 0.01 to 10 MeV in the direction of the gate electrode 17a. Irradiation of an electron beam having a structure changes the property of the active layer 14a made of IGZO (InGaZnO) material of the oxide semiconductor transistor. The electron beam has a dose of 1 × 10 ⁵ to 1 × 10 ²⁰ electrons / cm ² per unit area, and a high energy electron beam (HEEBI) having an energy of 0.01 to 10 MeV is used.

The oxide semiconductor transistor 10 of the present invention irradiated with a high energy electron beam has a glass substrate 11, a buffer layer 12, a source electrode 13a, a drain electrode 13b, an active layer 14a, a protective layer 15a, Consisting of the gate insulating layer 16 and the gate electrode 17a, the respective structures will be described in detail as follows.

The glass substrate 11 is used as a base substrate, the buffer layer 12 is formed on the entire surface of the glass substrate 11, and the material is a silicon oxide film (SiO ₂ ). The source electrode 13a is formed above the buffer layer 12, and the drain electrode 13b is formed above the buffer layer 12 so as to be spaced apart from the source electrode 13a. The active layer 14a is formed above the buffer layer 12 so as to be connected to the source electrode 13a and the drain electrode 13b, respectively, and the protective layer 15a is formed above the active layer 14a to form the active layer 14a. Protect. The gate insulating layer 16 is formed on the buffer layer 12 and the protective layer 15a, respectively, and the material of the protective layer 15a and the gate insulating layer 16 is made of alumina (Al ₂ O ₃ ), respectively. . The gate electrode 17a is formed above the gate insulating film layer 16.

Indium Tin Oxide (ITO) is used as the material of the source electrode 13a, the drain electrode 13b, and the gate electrode 17a. The active layer 14a is made of IGZO (InGaZnO), and a high energy electron beam is irradiated. do. When the electron beam is irradiated, the electron beam having a high energy characteristic irradiated to the upper side of the gate electrode 17a and the gate insulating film layer 16 and irradiated to the upper side of the gate electrode 17a and the gate insulating film layer 16 is the gate electrode 17a. ), The gate insulating layer 16 and the protective layer 15a are transmitted to the active layer 14a and irradiated. That is, the electron beam has a high energy, and passes through the protective layer 15a made of alumina (Al ₂ O ₃ ) and the gate insulating layer layer 16 and is irradiated to the active layer 14a.

When an electron beam having a high energy is irradiated to the active layer 14a using IGZO (InGaZnO), the active layer 14a generates an acceptor-type defect therein, resulting in negative bias voltage (NBIS) and negative gate voltage and light. Is applied at the same time to improve the stability against light and gate bias by reducing the characteristic change when applied.

A method of manufacturing the oxide semiconductor transistor 10 of the present invention having the above configuration will be described with reference to FIGS. 1 to 11.

First, as shown in FIG. 2, a glass substrate 11 used as a base substrate is provided. When the glass substrate 11 is provided, as shown in FIG. 3, the buffer layer 12 is coated by applying a silicon oxide film (SiO ₂ ) to a thickness of 10 to 20 nm using an atomic layer deposition (ALD) method on the entire surface of the glass substrate 11. ).

When the buffer layer 12 is formed, an indium tin oxide (ITO) layer 13 is coated on the entire surface of the buffer layer 12 to a thickness of 130 to 170 nm by using a RF (Radio Frequence) magnetron sputtering method. After that, as shown in FIG. 5, the ITO layer 13 is patterned to form the source electrode 13a and the drain electrode 13b.

When the source electrode 13a and the drain electrode 13b are respectively formed, as shown in FIG. 6, 20 to 40 using the RF magnetron sputtering method on the entire surface of the buffer layer 12 on which the source electrode 13a and the drain electrode 13b are formed. After forming the IGZO (InGaZnO) layer 14 to a thickness of ㎚ , alumina (Al ₂ O) having a thickness of 6 to 12 nm using the ALD method on the entire surface of the IGZO (InGaZnO) layer 14 as shown in FIG. ₃ ) After forming the layer 15, when the protective layer 15a is formed by patterning the alumina (Al ₂ O ₃ ) layer 15 as shown in FIG. 8, the IGZO layer 14 is formed as shown in FIG. 9. Patterning is performed to form the active layer 14a.

When the protective layer 15a is formed, as shown in FIG. 10, alumina (Al ₂ O ₃ ) is applied to the entire surface of the buffer layer 12 on which the protective layer 15a is formed to have a thickness of 150 to 200 nm using the ALD method. Thus, the gate insulating film layer 16 is formed. When the gate insulating layer 16 is formed, the ITO layer 17 is coated to a thickness of 130 to 170 nm by using an RF magnetron sputtering method on the entire surface of the buffer layer 12 on which the gate insulating layer 16 is formed, as shown in FIG. 11. After that, as shown in FIG. 1, the ITO layer 17 is patterned to form the gate electrode 17a. The process of patterning the gate electrode 17a, the source electrode 13a, the drain electrode 13b, the active layer 14a, and the protective layer 15a, respectively, uses a photolithography process.

When the gate electrode 17a is formed, the active layer 14a is irradiated with the electron beam using the electron beam accelerator 20 above the gate electrode 17a and the gate insulating layer 16 in the arrow direction shown in FIG. The electron beam is transmitted and irradiated, and the electron beam has an energy of 0.01 to 10 MeV and a high energy electron beam having an electron dose per unit area of 1 × 10 ⁵ to 1 × 10 ²⁰ electrons / cm ² is used.

The high energy electron beam is performed after the gate electrode 17a is formed to thereby irradiate the electron semiconductor beam with the oxide semiconductor transistor 10 of the present invention to maximize the irradiation effect of the electron beam. That is, the reduction of the electron beam irradiation effect due to thermal stress or the like caused by heat treatment or the like generated during the intermediate manufacturing process of the oxide semiconductor transistor 10 can be prevented. Here, the electron beam accelerator 20 is omitted because it is a known technique.

In order to measure the electrical characteristics of the oxide semiconductor transistor 10 according to the present invention, that is, the characteristics of NBIS (Negative Bias Illumination Stress (Negative Gate Voltage and Light)), the buffer layer 12 may be 15 nm thick. The source electrode 13a, the drain electrode 13b, and the gate electrode 17a are each 150 nm thick, the active layer 14a is formed to a thickness of 30 nm , and the protective layer 15a is 9 nm thick. The oxide film layer 16 was formed to a thickness of 176 nm . The oxide semiconductor transistor 10 of the present invention thus prepared was irradiated with a high energy electron beam having an energy of 0.8 MeV and an electron dose per unit area of 1 × 10 ¹⁴ electrons / cm ² .

Experimental results of the electrical characteristics, namely NBIS characteristics, of the oxide semiconductor transistor 10 of the present invention irradiated with a high energy electron beam having an energy of 0.8 MeV and an electron quantity of 1 × 10 ¹⁴ electrons / cm ² are shown in FIG. 12. have. 12 is a graph showing NBIS characteristics of the oxide semiconductor transistor 10 irradiated with a high energy electron beam, and FIG. 13 is a graph showing NBIS characteristics of an oxide semiconductor transistor not irradiated with a high energy electron beam.

The experimental method applies a gate bias of -20V to the oxide semiconductor transistor 10 of the present invention irradiated with the high energy electron beam and the oxide semiconductor transistor without the high energy electron beam, and applies white light. The NBIS characteristics of each white light irradiation time were measured while irradiating for 0 seconds, 100 seconds, 1000 seconds, and 10000 seconds, respectively. When the oxide semiconductor transistor 10 of the present invention is used as a backplane, the white light irradiation time often displays only one piece of information continuously when displaying a still image on a display, which is influenced by light, that is, white light, on the oxide semiconductor transistor. Since it is applied continuously, the irradiation time of white light was set variously.

As a result of measuring the characteristics of the NBIS, the oxide semiconductor transistor 10 of the present invention irradiated with a high energy electron beam as shown in FIG. 12 is significantly reduced in the NBIS characteristics of the oxide semiconductor transistor not irradiated with a high energy electron beam as shown in FIG. You can see that.

That is, in the oxide semiconductor transistor to which the high energy electron beam is not irradiated, when light energy of a wavelength band or more is applied to the bandgap, electrons are excited in the bandgap, generating numerous electron-hole carriers and generating electron-hole recombination. On the other hand, a myriad of holes are trapped by the insulating film, which causes degradation of the active layer of the semiconductor thin film transistor, that is, the channel, thereby reducing the stability of the oxide semiconductor transistor.

On the other hand, as in the present invention, an oxide semiconductor transistor having a high energy electron beam generates an acceptor like state that traps electrons near the valence band of the bandgap, and generates the acceptor level. by the further generation of electron-hole recombination, which reduces the amount of trapped holes, thereby reducing the change in the threshold voltage toward the negative direction and increasing the stability of the oxide semiconductor transistor, thereby improving the device's operational reliability. Will be.

The oxide semiconductor transistor of the present invention and its manufacturing method can be applied to the field of backplane manufacturing of a display.

11: glass substrate 12: buffer layer
13: ITO layer 13a: source electrode
13b: drain electrode 14: IGZO layer
14a: active layer 15: alumina layer
15a: protective layer 16: gate insulating film layer
17: ITO layer 17a: gate electrode

Claims (7)

In an oxide semiconductor transistor having an active layer made of IGZO (InGaZnO) material,
An oxide semiconductor transistor, characterized in that an electron beam having an energy of 0.01 to 10 MeV is irradiated to an active layer made of IGZO (InGaZnO) material of the oxide semiconductor transistor. The oxide semiconductor transistor of claim 1, wherein an electron beam has a dose of 1 × 10 ⁵ to 1 × 10 ²⁰ electrons / cm ² per unit area. The method of claim 1, wherein the oxide semiconductor transistor irradiated with the electron beam comprises a glass substrate;
A buffer layer formed on the entire surface of the glass substrate;
A source electrode formed on the buffer layer;
A drain electrode formed on the buffer layer to be spaced apart from the source electrode;
An active layer formed on the buffer layer so as to be connected to the source electrode and the drain electrode, respectively;
A protective layer formed on the active layer;
A gate insulating layer formed on the buffer layer and the protective layer, respectively;
A gate electrode formed on the gate insulating layer,
The buffer layer is made of silicon oxide (SiO ₂ ), and the source electrode, the drain electrode, and the gate electrode are made of indium tin oxide (ITO), respectively, and the active layer is made of IGZO (InGaZnO). And alumina (Al ₂ O ₃ ) is used as the material of the protective layer and the gate insulating layer, respectively.  The method of claim 3, wherein the active layer is characterized in that the electron beam is irradiated to the upper side of the gate electrode and the gate insulating film layer, respectively, and the irradiated electron beam is transmitted through the gate electrode, the gate insulating film layer and the protective layer, respectively, and irradiated. Oxide semiconductor transistor. Providing a glass substrate;
Forming a buffer layer on the entire surface of the glass substrate by applying a silicon oxide film (SiO ₂ ) to a thickness of 10 to 20 nm using an atomic layer deposition (ALD) method;
Applying an indium tin oxide (ITO) layer to a thickness of 130 to 170 nm using a radio frequency (RF) magnetron sputtering method on the entire surface of the buffer layer, and patterning the ITO layer to form a source electrode and a drain electrode;
Forming an IGZO layer after forming an IGZO (InGaZnO) layer with a thickness of 20 to 40 nm by using an RF magnetron sputtering method on an entire surface of the buffer layer on which the source electrode and the drain electrode are formed;
Forming an alumina (Al ₂ O ₃ ) layer having a thickness of 6 to 12 nm on an entire surface of the IGZO layer by using an ALD method;
Patterning the alumina (Al ₂ O ₃ ) layer to form a protective layer;
Patterning the IGZO layer to form an active layer;
Forming a gate insulating layer by coating an alumina (Al ₂ O ₃ ) on the entire surface of the buffer layer on which the protective layer is formed to have a thickness of 150 to 200 nm ;
Forming a gate electrode by applying an ITO layer to a thickness of 130 to 170 nm on an entire surface of the buffer layer on which the gate insulating layer is formed using an RF magnetron sputtering method, and then patterning the ITO layer;
And irradiating an electron beam to the active layer by irradiating an electron beam using an electron beam accelerator to the gate electrode and the gate insulating layer, respectively.
 The oxide semiconductor transistor of claim 5, wherein the electron beam has an energy of about 0.01 to about 10 MeV in the step of irradiating the electron beam to the active layer. The oxide semiconductor transistor of claim 5, wherein the electron beam has a dose of 1 × 10 ⁵ to 1 × 10 ²⁰ electrons / cm ² per unit area in the electron beam irradiation to the active layer.

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