KR20130056527A - Substrate panel array - Google Patents

Abstract

PURPOSE: A substrate panel array is provided to prevent a warpage in a panel by arranging two strips to cross each other, each of which includes multiple substrates laminated in the opposite order of the other. CONSTITUTION: A substrate panel array comprises multiple first unit strips(ABC), and multiple second unit strips(CBA) located adjacent to the first unit strips. The first unit strips include multiple first unit substrates including multiple circuit layers laminated in a first order. The second unit strips include multiple second unit substrates including multiple circuit layers laminated in a second order. The first unit strips and the second unit strips are alternately arranged.

Description

Substrate panel array

The present invention relates to a substrate panel array.

In general, a printed circuit board (PCB) serves to easily connect various electronic devices according to a predetermined frame, and is widely used in all electronic products such as digital TV and other home appliances to high-tech communication devices. According to the application, it is also classified into general purpose PCB, module PCB, package PCB, and the like.

In other words, the printed circuit board is formed by attaching a thin plate such as copper to one side of a phenolic resin insulating plate or an epoxy resin insulating plate, and then etching it according to the wiring pattern of the circuit (corroding and removing only the circuit on the line) to form a necessary circuit. It is formed by drilling holes for attaching and mounting them.It is classified into single-sided board, double-sided board, and multi-layered board according to the number of wiring circuit surface.The higher the number of layers, the better the mounting force of the parts and it is adopted in high-precision products. With the development of the industry, multilayer printed circuit boards with ultra-thin printed circuit boards (thickness of 0.04 mm to 0.2 mm) are widely used.

Such a printed circuit board has a cross-section used for a relatively simple electronic device, but recently, a double-sided board having a circuit formed on both sides and interconnected through a through hole, or a multilayer in which this is expanded into a plurality of layers as well as both sides. Substrate use is on the rise.

Commonly known multilayer circuit boards are impregnated with woven glass fibers to impregnate BT, FR-4, or other resins to produce an insulator plate core. Then, copper foils are laminated on both sides of the core to form an inner layer circuit. It is manufactured using a subtractive process or a semi-additive process.

Briefly describing the manufacturing process of the multilayer circuit board, the inner circuit pattern is formed on both sides of the core, wherein the core is CCL (Copper Clad Laminate) is mainly used, as the insulating material of the CCL is woven glass fiber FR-4 or epoxy series insulating materials impregnated with resin are mainly used.

After the inner circuit pattern is formed, roughness is formed on the surface of the core and the inner circuit pattern by CZ etching on the substrate on which the inner circuit pattern is formed, and then a vacuum laminator is applied to the substrate having the roughness on the surface of the core and the inner circuit pattern. By using the heat-curable resin in the form of an ink or a resin in the form of a dry film attached to the external insulating layer to form a build-up layer.

Thereafter, during the desmear process, heat is applied to the substrate on which the build-up layer is laminated so as to have chemical resistance and chemical resistance, and the pre-hardening of the external insulating layer is performed. Through-holes and via-holes are formed.

Subsequently, through the desmear process, residues in the inner walls of the through-holes and via-holes are removed to form a rough surface, and then surface roughness is formed by CZ etching solution. After forming, an outer circuit pattern is formed through an image forming process. Thereafter, a solder resist layer is formed on an outer surface of the outer circuit pattern.

On the other hand, the above-described multilayer circuit board is manufactured using a panel, wherein the panel is divided into a plurality of strips including a plurality of unit substrates at equal intervals.

That is, a plurality of strips having a predetermined size is formed in the panel, and each of the strips is divided into a plurality of unit substrates on which electronic components are mounted.

However, the conventional panel for multilayer circuit boards is accompanied by a change due to heat applied from the outside during the various processes for manufacturing the substrate, the change of each heat is deformed according to the thermal expansion coefficient characteristics of the material There was a problem in that the warpage phenomenon, that is, warpage phenomenon occurs for the entire panel as a result.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the prior art, and an aspect of the present invention is to provide a substrate panel array in which warpage is minimized.

A substrate panel array according to an embodiment of the present invention includes a plurality of first unit strips including a plurality of first unit substrates in which a plurality of circuit layers are stacked in a first order, and the first unit strips. And a plurality of second unit strips disposed adjacent to each other, the plurality of circuit layers including a plurality of second unit substrates stacked in a second order opposite to the first order.

In this case, the first unit strip and the second unit strip may be arranged to cross each other.

In addition, a first unit strip may be arranged inside the substrate panel array, and a second unit strip may be arranged outside the substrate panel array.

In addition, a second unit strip may be arranged inside the substrate panel array, and a first unit strip may be arranged outside the substrate panel array.

In addition, each of the plurality of circuit layers may have a different metal content.

Here, the metal may be copper (Cu).

In addition, the first unit substrate and the second unit substrate are divided into a first region and a second region having a higher copper (Cu) share than the first region, and the first unit strip and the second unit strip are the substrate. The second region may be arranged on the panel array to face inward.

The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

Prior to that, terms and words used in the present specification and claims should not be construed in a conventional and dictionary sense, and the inventor may properly define the concept of the term in order to best explain its invention It should be construed as meaning and concept consistent with the technical idea of the present invention.

The present invention mixes and arranges two strips in which copper circuits having different copper contents are stacked in the opposite order, thereby partially canceling the bending stress generated in each strip during heating, thereby providing a panel of the panel. There is an effect that can suppress the bending deformation.

In addition, the present invention arranges the unit substrate so that a region having a high Cu share is located inside the panel, thereby offsetting the force of expansion of the copper during heating, thereby preventing warpage of the panel. There is an effect that can minimize the occurrence of.

In addition, the present invention can suppress the bending deformation of the panel (panel) as described above, it can provide an industrially useful effect that can be expected to standardize the product and improve productivity and yield.

1 is an exploded perspective view showing the structure of a general substrate panel array.
2 to 4 are plan views illustrating structures of layered strips of a general substrate panel array.
5 is an exploded perspective view showing the structure of a substrate panel array according to an embodiment of the present invention.
6 to 7 are plan views showing the arrangement structure according to the copper (Cu) occupancy of the unit substrate.
8 is a plan view illustrating a strip arrangement example in a substrate panel array according to an exemplary embodiment.
9 is a plan view illustrating a strip arrangement example in a substrate panel array according to another exemplary embodiment of the present disclosure.
10 is a plan view illustrating a strip arrangement example in a substrate panel array according to another exemplary embodiment of the present disclosure.

The objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and embodiments associated with the accompanying drawings. In the present specification, in adding reference numerals to the components of each drawing, it should be noted that the same components as much as possible even if displayed on different drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In this specification, the terms first, second, etc. are used to distinguish one element from another, and the element is not limited by the terms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exploded perspective view illustrating a structure of a general substrate panel array, and FIGS. 2 to 4 are plan views illustrating structures of layered strips of a general substrate panel array, and FIG. 5 is a plan view of a substrate panel array according to an embodiment of the present invention. An exploded perspective view showing the structure.

In the present embodiment, as shown in FIG. 1, the substrate panel array 10 includes a plurality of strip units A, B, and C, each of which includes a plurality of substrate units A1... A8, B1 .. B8, C1 .. C8. A plurality of panels L1, L2, and L3 may be stacked.

In FIG. 1, three panels L1, L2, and L3 are stacked, but this is simplified for the sake of explanation, and it is common that four or more panels are laminated.

Herein, the substrate units A1... A8, B1... B8, or C1 ... C8 mean one layer of a plurality of layers that each form a multi-layered substrate, and each of the plurality of substrate units A1 .. A8, B1 .. B8 or Each multilayer substrate (eg, A1-B1-C1, A2-B2-C2, ... A8-B8-C8) on which C1 ... C8) is formed will be referred to as a unit substrate hereinafter.

For example, a multilayer substrate in which substrate units A1, B1, and C1 are stacked is a first unit substrate, and a multilayer substrate in which substrate units A2, B2, and C2 are stacked is a second unit substrate.

In addition, although each strip unit (A, B, C) in Figures 1 to 4 is shown to include eight substrate units, this is only one embodiment may include fewer substrate units, more It will be appreciated by those skilled in the art that a large number of substrate units may be included.

Similarly, the strip units A, B, and C also mean a plurality of strips partitioned on one panel, and a plurality of strip units A, B, and C are stacked to form a unit strip. Will name.

As a result, the substrate panel array 10 may mean that one or more unit strips including a plurality of unit substrates, which are multilayer substrates formed of at least one or more circuit layers, are arranged.

In the unit substrate on which the first unit substrate, that is, the substrate units A1, B1, and C1 are stacked with reference to FIGS. 1 to 4, circuit patterns (not shown) may be formed on the substrate units A1, B1, and C1, respectively. In this case, circuit patterns (not shown) formed in each of the substrate units A1 and B1 and C1 may have different shapes, and accordingly, differences in the amount of metal contained in each substrate unit may occur. That is, the metal content is different for each substrate unit of each layer.

At this time, although not particularly limited, when the circuit pattern is made of copper (Cu), the metal content may be copper (Cu) content.

In addition, the density of circuit patterns formed for each of the substrate units A1, B1, and C1 may locally vary on the same plane. That is, the circuit pattern may be divided into regions formed by dense circuit patterns for respective substrate units of each layer and regions not formed.

In this case, as described above, when the circuit pattern is made of copper (Cu), the occupancy rate of copper (Cu) of the region where the circuit pattern is densely formed may be higher than that of the other region. Accordingly, each of the substrate units may be divided into regions having a high copper (Cu) occupancy rate and regions not having the copper occupancy rate.

For example, FIG. 2 to FIG. 4 show a state in which the copper occupancy rate per substrate unit is divided into a region having a high occupancy ratio and a region not having the same.

2 to 4, the copper occupancy rate per substrate unit may be high in the left region of the substrate unit (see FIG. 2), the center region of the substrate unit may be high (see FIG. 3), The occupancy of copper (Cu) in the entire area of the substrate unit may be high (see FIG. 4).

In general, an insulating material and a metal are representative of the materials constituting the substrate. Among them, the coefficient of thermal expansion of the metal is significantly higher than that of the insulating material. That is, the degree of expansion during heating is significantly greater in the case of metal than in the case of the insulating material.

As a result, the area with high metal occupancy increases in the amount of expansion during heating, and the area with high occupancy in the insulating material increases in amount of shrinkage during heating, so that the expansion and contraction of the entire substrate does not occur uniformly, so that warpage may occur.

The present invention is to improve such a problem, the substrate panel array 100 according to an embodiment of the present invention is disclosed in FIG.

Referring to FIG. 5, the substrate panel array 100 according to the present embodiment includes a plurality of first unit strips ABC and a plurality of first unit strips including a plurality of unit substrates in which a plurality of circuit layers are stacked in a first order. A plurality of second unit strips (CBA) are formed adjacent to (ABC) and include a plurality of unit substrates in which a plurality of circuit layers are stacked in a second order opposite to the first order.

For example, as shown in FIG. 5, the unit substrates included in the first unit strip ABC are stacked in the order of L1-L2-L3 from the top with respect to FIG. 5, and the second unit strip CBA is disposed on the second unit strip CBA. The included unit substrates may be stacked in the order of L3-L2-L1 from the top with reference to FIG. 5 as opposed to the first unit strip ABC.

That is, as described above, circuit patterns (not shown) may be formed in the substrate units A1, B1, and C1, respectively, and in this case, circuit patterns (not shown) formed in each of the substrate units A1, B1, and C1 may be formed in each other. As a result, a difference occurs in the amount of metal contained in each substrate unit, and thus the metal content may vary for each substrate unit of each layer.

At this time, for example, when the metal content increases in the order of L1-L2-L3, as shown in FIG. 1, when the unit boards of all the unit strips of the substrate panel array are stacked in the order of L1-L2-L3, L1 during heating In addition, the expansion ratio of L3 becomes relatively very large, and thus, smile-shaped warpage may occur in the substrate panel array.

Accordingly, the structure in which the substrate unit having a relatively high metal content is concentrated at the lower portion of the structure is disposed so as to be symmetrically disposed at the upper and lower portions as shown in FIG. 5 to cancel the bending stress acting on the upper and lower portions of the substrate panel array 100. The warpage phenomenon is prevented from occurring in the substrate panel array 100.

In FIG. 5, the first unit strips ABC are arranged inside the substrate panel array 100, and the second unit strips CBA are arranged at both ends thereof. However, this is only an example. The second unit strip (CBA) may be arranged inside, and the first unit strip (ABC) may be arranged at both ends, and the first unit strip (ABC) and the second unit strip (CBA) may be arranged crosswise. It will be appreciated by those skilled in the art that the arrangement is not particularly limited and may be arranged in a variety of ways.

In addition, as described above, referring to FIGS. 2 to 4, the density of circuit patterns formed for each of the substrate units A1, B1, and C1 may be locally different on the same plane.

For example, it may be divided into a first region formed by dense circuit patterns for each substrate unit of each layer and a second region not formed by dense circuit patterns.

That is, the occupancy rate of copper (Cu) of the substrate unit A1 may be high in the left region of the substrate unit based on FIG. 2, and the occupancy rate of copper (Cu) of the substrate unit B1 may be high in the central area of the substrate unit based on FIG. 3. In addition, the copper (Cu) occupancy rate of the substrate unit C1 may be high over the entire area of the substrate unit based on FIG. 4.

As described above, as the copper occupancy is high and low in each substrate unit, as illustrated in FIG. 6, a unit substrate on which substrate units are stacked may also have a high copper occupancy and a low copper occupancy rate.

For example, referring to FIG. 6, the unit substrate of the second unit strip CBA may have a region (a) having a high copper (Cu) occupancy rate and a region (b) having a lower copper (Cu) occupancy rate than the region (a). It can be divided into.

Accordingly, in the present embodiment, as shown in FIG. 7, adjacent unit strips may be arranged such that regions (a), which are regions having a high copper (Cu) occupancy, face each other, that is, regions (a) face inward. Can be.

That is, by arranging the regions (a) having a high occupancy ratio of copper (Cu) to face each other, the bending force of the substrate panel array 100 is minimized by offsetting the force to expand.

8 to 10 are plan views illustrating strip arrangement examples in a substrate panel array according to an exemplary embodiment.

Here, L1 and Ln may refer to one layer and n layers in the multilayer substrate, respectively. At this time, the unit boards of the strips written as L1 are stacked in the order of L1-L2 -...- Ln (first unit strip), and the unit boards of the strips written as Ln are arranged in the order of Ln-Ln-1 -... L1 ( The second unit strip).

That is, in the substrate panel array 100 shown in FIGS. 8 to 10, the first unit strips are arranged outside and the second unit strips are arranged inside.

At this time, a part or the whole of the unit strip located on the left side of the substrate panel array 100 is rotated with reference to FIGS. By moving inward, it arrange | positions so that the area | region with a high copper (Cu) occupancy rate of the unit strip located on the right side may face.

Accordingly, the substrate panel array 100 according to the present embodiment is intended to expand by arranging a layer having a high copper (Cu) content at the top or the bottom thereof and at the same time arranging a region having a high copper (Cu) occupancy toward the surface. The force may be canceled to minimize occurrence of warpage of the substrate panel array 100.

Although the present invention has been described in detail through specific embodiments, this is for explaining the present invention in detail, and the substrate panel array according to the present invention is not limited thereto. It is obvious that modifications and improvements are possible by those who have them.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

100: Board Panel Array
A, B, C: strip unit
A1 to A8, B1 to B8, C1 to C8: Board unit
ABC: 1st unit strip
CBA: 2nd unit strip

Claims (7)

A plurality of first unit strips including a plurality of first unit substrates in which a plurality of circuit layers are stacked in a first order; And
A plurality of second unit strips positioned adjacent to the first unit strip, the plurality of second unit substrates including a plurality of second unit substrates stacked in a second order opposite to the first order;
Substrate panel array comprising a. The method according to claim 1,
And the first unit strip and the second unit strip are arranged to cross each other. The method according to claim 1,
And a first unit strip arranged inside the substrate panel array and a second unit strip arranged outside the substrate panel array. The method according to claim 1,
And a second unit strip is arranged inside the substrate panel array, and a first unit strip is arranged outside the substrate panel array. The method according to claim 1,
And a plurality of circuit layers each having a different metal content. The method according to claim 5,
And the metal is copper (Cu). The method according to claim 1,
The first unit substrate and the second unit substrate are respectively divided into a first region and a second region having a higher copper (Cu) share than the first region.
And the first unit strip and the second unit strip are arranged on the substrate panel array such that the second region faces inward.

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