KR20130051342A - Liquid crystal display having oxide thin film transistor and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A liquid crystal display having an oxide thin film transistor and a method for manufacturing the same are provided to prevent the damage of an oxide semiconductor layer by performing a dry etching process after a wet etching process is performed. CONSTITUTION: A first conductive layer is exposed by a wet etching process for a second conductive layer. A second drain electrode(162b) and a second source electrode(162a) are formed, and then a dry etching process for the first conductive layer is performed to expose an etch stopper(150) and an oxide semiconductor layer(140). A first drain electrode(161b) and a first source electrode(161a) are formed, and then a first insulation layer(170) and a pixel electrode(175) are formed. A liquid crystal layer is formed between a first substrate(110) and a second substrate. The second substrate is attached to the first substrate.

Description

Liquid Crystal Display Having Oxide Thin Film Transistor and Method of manufacturing the same

Embodiments of the present invention relate to a liquid crystal display and a method for manufacturing a liquid crystal display, and more particularly, to a method for manufacturing a liquid crystal display for reducing parasitic capacitors in a pixel region.

 In a flat panel display such as a liquid crystal display, an active element such as a thin film transistor is provided in each pixel to drive a display element. This type of display device driving method is commonly referred to as an active matrix driving method. In the active matrix method, the thin film transistor is disposed in each pixel to drive the corresponding pixel.

On the other hand, the general thin film transistor has been using amorphous silicon as a semiconductor layer, the amorphous silicon has a low electron transfer speed, it was difficult to achieve high resolution and high-speed driving capability on a very large screen. Therefore, an oxide thin film transistor having an electron transfer speed 10 times faster than that of amorphous silicon has emerged, and it has recently been spotlighted as a device suitable for high resolution of UD (Ultra Definition) and high speed driving of 240Hz or more.

The liquid crystal display is manufactured by a process such as photolithography. The photolithography process is performed through a series of processes such as deposition of a pattern target material and photoresist, exposure using a mask, development of the photoresist, and etching. It's a complex process. Herein, the configuration of the liquid crystal display device formed through such a process will be described in detail with reference to FIGS. 1 and 2.

1 is a cross-sectional view of an array substrate of a liquid crystal display device including a conventional oxide thin film transistor, and FIG. 2 is a plan view of a unit pixel of a conventional liquid crystal display device.

The liquid crystal display device includes a liquid crystal panel for displaying an image, a backlight unit for emitting light, and a driving circuit unit for driving the liquid crystal panel and the backlight unit. Among them, the liquid crystal panel includes a thin film transistor substrate 10, a color filter substrate, and a liquid crystal layer. FIG. 1 is a cross-sectional view of the thin film transistor substrate.

The thin film transistor substrate 10 includes a thin film transistor (TFT) (not shown), a pixel electrode 75, and the like. The thin film transistor (not shown) includes a gate electrode 21, a gate insulating layer 30, an oxide semiconductor layer 40, an etch stopper 50, a source electrode 61, and a drain electrode 62.

The gate electrode 21 is formed at the time of forming the gate line 20 of FIG. 2 and has a shape extending in one direction from the gate line 20.

Subsequently, a gate insulating film 30 is formed on the entire surface of the thin film transistor substrate 10 to insulate the oxide semiconductor layer 40 from the gate electrode 21, and the oxide semiconductor is positioned at a position overlapping with the gate electrode 21. Form layer 40. The oxide semiconductor layer 40 is formed to overlap the gate electrode 21 because the oxide semiconductor layer 40 receives a voltage from the gate electrode and serves to conduct the electron transfer channel.

The etch stopper 50 is disposed on the oxide semiconductor layer 40 so that the region where the channel of the oxide semiconductor layer 40 is formed is not damaged during the etching process for forming the source and drain electrodes 62. To form.

The source electrode 61, the drain electrode 62, and the data line 60 are formed. The source electrode 61 and the drain electrode 62 partially overlap the oxide semiconductor layer 40, and the source electrode 61 extends in one direction from the data line 60.

The insulating layer 70 is formed on the source electrode 61 and the drain electrode 62, and the pixel electrode 75 is connected to the drain electrode 62 through the contact hole 71 of the insulating layer 70. It is formed in electrical contact. The pixel electrode 75 is formed in a single pattern as wide as an area corresponding to a unit pixel in order to apply a voltage to a liquid crystal layer corresponding to one unit pixel.

On the other hand, the etching process of the photoresist process is a process of selectively scraping off the area that is not covered by the photoresist using the undeveloped photoresist as a film, which may be performed by dry etching or wet etching.

Wet etching is a method of selectively removing etched materials by using etchant, which is cheaper and more productive, but the precision of etching is lower than that of dry etching and damage of other components by etchant may occur. In this way, the dry etching is faster than the wet etching, the reaction rate is fast and can be etched fine shape and has a safe advantage because the reaction is made in a vacuum chamber (chamber).

Therefore, inorganic materials such as the etch stopper 50 are formed by dry etching, and metals such as the source electrode 61 and the drain electrode 62 which are not significantly damaged by the etchant are formed by the wet etching process. do.

However, in the wet etching process, the oxide semiconductor layer 40 under the source and drain electrodes 61 and 62 may be damaged by the etchant. The channel formation region of the oxide semiconductor layer 40 is protected by the etch stopper 50, but other regions may be exposed and thus may be affected by the etchant.

Therefore, as shown in the enlarged view of FIG. 2, the upper surface of the oxide semiconductor layer 40 is entirely covered by the etch stopper 50 and the source and drain electrodes 61 and 62.

At this time, the area of the region where the source and drain electrodes 62 overlap the lower gate electrode 21 becomes wider. The source and drain electrodes 62 become the upper electrode, and the gate electrode 21 becomes the lower electrode. In this case, a parasitic capacitor may be generated in the thin film transistor because the gate insulating layer 30 serves as a dielectric.

The parasitic capacitor acts as a load increase factor of the data line 60 and the gate line 20, and increases power consumption by requiring a larger driving voltage as the load increases.

That is, the problem of reducing the parasitic capacitors is whether or not the overlap area of the source and drain electrodes 61 and 62 is reduced, but the area of the source and drain electrodes 61 and 62 is reduced to prevent the loss of the oxide semiconductor layer. There was a big difficulty in reducing parasitic capacitors because they could not be reduced.

Therefore, in order to solve the above problems, embodiments of the present invention mix dry and wet etching when forming the source and drain electrodes so that the oxide semiconductor layer is not damaged so that the source and drain electrodes overlap with the gate electrode. The purpose is to reduce the

In addition, other objects and features of the present invention will be described in the description and claims for carrying out the invention described below.

In order to achieve the above object of the present invention, the liquid crystal display device manufacturing method according to an embodiment of the present invention comprises the steps of forming a gate electrode, a gate insulating film on the first substrate; Forming an oxide semiconductor layer over the gate insulating layer and overlapping the gate electrode; Forming an etch stopper on the oxide semiconductor layer; Sequentially stacking a first conductive layer and a second conductive layer on the entire surface of the first substrate including the etch stopper; Wet etching the second conductive layer to expose the first conductive layer and form a second source electrode and a second drain electrode overlapping the oxide semiconductor layer but spaced apart from each other; Dry etching the first conductive layer to expose the etch stopper and the oxide semiconductor layer, and forming a first source electrode and a first drain electrode under the second source electrode and the second drain electrode; Forming a first insulating layer on the first and second source electrodes and the first and second drain electrodes, and forming a pixel electrode in electrical contact with the first and second drain electrodes through a contact hole; And attaching the second substrate to face the first substrate through a liquid crystal layer between the first substrate and the second substrate.

Preferably, the second source electrode and the second drain electrode have the same pattern as the first source electrode and the first drain electrode.

The first and second source electrodes, the first and second drain electrodes, and the etch stopper may not cover the entire surface of the oxide semiconductor.

The forming of the first and second source electrodes and the first and second drain electrodes may include forming the first and second source electrodes and the first and second drain electrodes spaced apart from the etch stopper. It is done.

In addition, the first conductive layer is composed of any one of Ti, Mo, MoTi, Ti alloy, Al, the second conductive layer is characterized in that composed of any one of Cu, Al, Ag, Pt, Au.

The method may further include forming a second insulating layer on the pixel electrode; Forming a common electrode on an area of the second insulating layer and overlapping the pixel electrode; Characterized in that it further comprises.

In addition, the pixel electrode may be formed in a single pattern, and the common electrode may be in the form of a box having a plurality of slits.

The method may further include forming a common electrode on the second substrate.

The method may further include forming a common electrode on the first insulating layer, wherein the common electrode is formed in a plurality of bars facing the pixel electrode and the common electrode.

On the other hand, a fringe field type liquid crystal display device according to another embodiment of the present invention is a first substrate; A gate electrode formed on the first substrate; A gate insulating layer formed on the gate electrode; An oxide semiconductor layer formed on an upper portion of the gate insulating layer and overlapping the gate electrode; An etch stopper formed on an upper surface of the oxide semiconductor layer; A source electrode and a drain electrode spaced apart from the etch stopper but overlapping the oxide semiconductor layer and formed of a first conductive layer and a second conductive layer; A first insulating layer formed on the source electrode and the drain electrode; A pixel electrode electrically connected to the drain electrode through a contact hole on the first insulating layer; A second insulating layer formed on the pixel electrode; A common electrode overlapping the pixel electrode on the second insulating layer, and having a plurality of slits; A second substrate including a color filter bonded to and opposed to the first substrate; And a liquid crystal layer interposed between the first substrate and the second substrate.

According to at least one embodiment of the present invention configured as described above, a liquid crystal display device or a liquid crystal display device manufacturing method includes

Dry etching after wet etching may prevent the oxide semiconductor layer from being damaged. Accordingly, by minimizing the area of the source and drain electrodes covering the top of the oxide semiconductor layer, the area overlapping with the gate electrode can be reduced, thereby reducing the capacitance of the parasitic capacitor.

The reduction of parasitic capacitors reduces the load on the data and gate lines, allowing lower drive voltages to be used, resulting in lower power consumption.

Since the load can be reduced, a narrower line width can be formed than in the prior art, and the size of the thin film transistor can be reduced by reducing the area of the source and drain electrodes, thereby increasing the aperture ratio and transmittance.

1 is a cross-sectional view of an array substrate of a liquid crystal display device including a conventional oxide thin film transistor.
2 is a plan view of a unit pixel of a conventional liquid crystal display.
3A is a plan view of a unit pixel of a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 3B is an enlarged view illustrating region T of FIG. 3A.
4 is a cross-sectional view taken along line II ′, II ′, II ′, and III ′ III ′ of FIG. 3A.
5A to 5L are cross-sectional views of a manufacturing process of a liquid crystal display according to an exemplary embodiment of the present invention.
6 is a flowchart of a manufacturing process of a liquid crystal display according to an exemplary embodiment of the present invention.
7A is a cross-sectional photograph of a thin film transistor according to the prior art.
7B is a cross-sectional photograph of a thin film transistor according to an embodiment of the present invention.

Hereinafter, a liquid crystal display device and a liquid crystal display device manufacturing method according to an embodiment of the present invention will be described in more detail with reference to the accompanying drawings.

As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise.

In addition, it should be considered that elements of the drawings attached to the present specification may be enlarged or reduced for convenience of description.

3A is a plan view of a unit pixel of a liquid crystal display according to an exemplary embodiment of the present invention. 3B is an enlarged view illustrating region T of FIG. 3A, and FIG. 4 is a cross-sectional view taken along line II ′, II ′, II ′, and III ′ III ′ of FIG. 3A.

The liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel, a backlight unit, and a driving circuit unit. Here, the liquid crystal panel is composed of a first substrate, a second substrate, and a liquid crystal layer. Hereinafter, a description will be given of the configuration formed on the first substrate in detail.

First, referring to FIG. 3A, the space between the data line 160 and the gate line 120 crossing each other is defined as a unit pixel, and a thin film transistor T is formed in one space of the unit pixel. A gate pad is formed at one end of the gate line 120, and a data pad is formed at one end of the data line 160.

When the data line 160 is formed in a first direction, the gate line 120 is formed in a second direction perpendicular to the first direction. The data line 160 may be formed in an angled S shape.

Referring to FIG. 4, the gate pad (not shown) includes a gate pad electrode 122 and an upper conductive layer 192. The gate pad electrode 122 is formed at the same time as the gate electrode 121. The upper conductive layer 192 is electrically contacted through the second contact hole 182 formed in the first insulating layer 170 and the second insulating layer 180. Therefore, the signal generated by the gate driver may be transferred to the gate pad electrode 122 through the upper conductive layer of the gate pad, and then to the gate line 120.

The data pad (not shown) includes the data pad electrodes 161c and 162c and the upper conductive layer 193 and is formed simultaneously with the source and drain electrodes 161a, 162a, 161b, and 162b. The data pad electrodes 161c and 162c include a first data pad electrode 161c and a second data pad electrode 162c, and the upper conductive layer 193 includes the first insulating layer 170 and the second insulating layer. Electrical contact with the data pad electrodes 161c and 162c is made through the third contact hole 183 formed at 180. Therefore, the data signal generated by the data driver may be transmitted to the data pad electrodes 161c and 162c through the upper conductive layer 193 of the data pad and then to the data line 160.

The thin film transistor T is a switching element, and includes a gate electrode 121, a gate insulating layer 130, an oxide semiconductor layer 140, an etch stopper 150, a source electrode 161a and 162a, and a drain electrode. 161b and 162b.

Referring to the structure of the thin film transistor T through FIG. 4, the gate electrode 121 is formed on the first substrate 110, and the gate electrode 121 and the oxide semiconductor layer 140 are insulated therefrom. The gate insulating film 130 is formed. The oxide semiconductor layer 140 is formed on the gate insulating layer 130 in the region overlapping with the gate electrode 121. There is no limitation on the type of the oxide semiconductor layer 140. For example, the Zn oxide may be formed of a Zn oxide, an In—Zn oxide, a Ga—In—Zn oxide, and the like, and further include other materials such as an organic material. An etch stopper 150 layer is formed on one surface of the oxide semiconductor layer 140 to prevent the channel region of the oxide semiconductor layer 140 from being damaged by etching. The etch stopper 150 layer may be formed of an inorganic material. In addition, overlapping both ends of the oxide semiconductor layer 140, the source electrodes 161a and 162a and the drain electrodes 161b and 162b are formed to be spaced apart from the etch stopper 150.

The source electrodes 161a and 162a and the drain electrodes 161b and 162b may include a second source electrode 162a and a second drain electrode 162b disposed above and a first source electrode 161a and a second disposed below. It consists of two drain electrodes 162b.

The first source electrode 161a and the first drain electrode 161b may include titanium (Ti), titanium alloys (Ti alloys), molybdenum (Mo), and molybdenum titanium alloys so as to facilitate ohmic contact with the oxide semiconductor layer 140. MoTi), aluminum (Al), or indium-tin oxide (ITO), and the like. The second source electrode 162a and the second drain electrode 162b may be low resistance metals such as copper (Cu) and platinum. (Pt), gold (Au), silver (Ag), aluminum (Al), and the like.

The first source electrode 161a and the first drain electrode 161b may be formed in the same shape as the second source electrode 162a and the second drain electrode 162b.

Here, the upper structure of the thin film transistor T will be described in detail with reference to FIG. 3B.

The gate electrode 121 is formed to be wider than the area of the oxide semiconductor layer 140 in order to smoothly transfer the gate voltage and prevent damage (reliability and reduced lifetime) of the oxide semiconductor layer due to incident light of the backlight unit. The fur 150 covers an upper surface of the oxide semiconductor layer 140. The one surface may be a central surface. The source electrodes 161a and 162a and the drain electrodes 161b and 162b cover portions of both ends of the oxide semiconductor layer 140. Therefore, the etch stopper 150 is formed to be spaced apart from the source electrodes 161a and 162a and the drain electrodes 161b and 162b, and the upper entire surface of the oxide semiconductor layer 140 is formed as an etch stopper. 150 and the source and drain electrodes 161a, 162a, 161b, and 162b.

In other words, the thin film transistor T has a smaller area where the source and drain electrodes 161a, 162a, 161b, and 162b overlap with the gate electrode 121 as compared with the related art. Compared with the prior art, an embodiment of the present invention can reduce the area of the source electrode and the drain electrode by about one third.

As a result, the capacitance of the capacitor is proportional to the cross-sectional area of the upper and lower electrodes (C = A / d; C = capacitor capacitance, A = phase, cross-sectional area of the lower electrode, d = phase, the distance between the lower electrode). The capacitance of the parasitic capacitor generated by overlapping the 161a, 162a, 161b, and 162b and the gate electrode 121 can be reduced by about one third.

The parasitic capacitor may cause a delay of the data signal and the gate signal. In other words, the parasitic capacitor may act as a resistance of the data line 160 and the gate line 120.

Accordingly, the load of the data line 160 and the gate line 120 may be reduced by reducing the capacitance of the parasitic capacitor, and the signal transmission without distortion may be performed even if the driving voltage for driving the unit pixel is low. As a result, power consumption can be reduced by using a low driving voltage.

In addition, since the load can be reduced, a narrower line width can be formed, and the size of the thin film transistor can be reduced by reducing the area of the source and drain electrodes 161a, 162a, 161b, and 162b. It is possible to increase the aperture ratio and transmittance of the device. Increasing the aperture ratio and transmittance of the liquid crystal display leads to an increase in luminance, thereby reducing power consumption for driving the light source.

On the other hand, in the operation of the thin film transistor T, when a channel is connected to the active layer by the gate voltage transmitted from the gate line 120, the data voltage transmitted from the data line 160 is transferred to the drain electrode through the channel. Drives to 161b, 162b to be applied to the pixel electrode 175.

Here, one surface of the drain electrodes 161b and 162b may extend in one direction and be connected to the pixel electrode 175 through the first contact hole 171. The pixel electrode 175 is on the first insulating layer 170 and is formed in a single pattern in an area corresponding to the unit pixel. In FIG. 3A, an area indicated by a dotted line is an area where the pixel electrode 175 is formed.

The common electrode 195 may be formed to form the fringe field with the pixel electrode 175 with the second insulating layer 180 therebetween. In this case, the common electrode 195 may be formed in a box shape on the front surface of the first substrate 110 with the first opening 195a and the second opening 195b open.

The first opening 195a is a plurality of slits formed in parallel with the data line 160. The plurality of slits may be arranged at regular intervals. The second opening 195b opens the upper portion of the thin film transistor T region and is formed so as not to interfere with the movement of electrons in the channel region of the oxide semiconductor layer 140.

The common electrode 195 and the pixel electrode 175 may be formed by changing their positions.

In the present specification, only a fringe field type liquid crystal display (FFS LCD) has been described, but one embodiment of the present invention is not limited thereto, and the oxide semiconductor layer 140 includes the source and drain electrodes 161a. 162a, 161b, and 162b, the TN, VA, and IPS liquid crystal display devices are all included as one embodiment of the present invention.

Hereinafter, a manufacturing method of the liquid crystal display device will be examined through other drawings.

5A to 5L are cross-sectional views of a manufacturing process of a liquid crystal display according to an exemplary embodiment of the present invention. 6 is a flowchart of a manufacturing process of a liquid crystal display according to an exemplary embodiment of the present invention.

First, referring to FIG. 5A, a gate electrode 121, a gate line (not shown), and a gate pad electrode 122 are formed on the first substrate 110 made of a transparent insulating material.

The gate electrode 121 is formed by depositing a conductive film (not shown) on the entire surface of the first substrate 110 and selectively patterning the same by a photolithography process. The photolithography process includes laminating a photoresist, then performing an exposure process, developing the photoresist, and etching the remaining photoresist as a film.

Here, the conductive film may be aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum ( Low resistance opaque conductive materials such as Pt) and tantalum (Ta) may be used. In addition, an opaque conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) may be used as the first conductive layer.

Next, the gate insulating layer 130 is deposited according to FIG. 5B and the oxide semiconductor layer 140 is formed (S2).

First, a gate insulating layer 130 is formed, and the gate insulating layer 130 is formed on an entire surface of the first substrate 110 on which the gate electrode is formed, such as an inorganic insulating layer or hafnium such as silicon nitride (SiNx) and silicon oxide (SiO 2); Hf) oxide, a high dielectric oxide film such as aluminum oxide and the like deposited. In this case, the gate insulating layer 130 may be formed by Chemical Vapor Deposition (CVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD).

The oxide semiconductor layer 140 is deposited on the entire surface of the first substrate 110 on which the gate insulating layer 130 is formed. At this time, the type of the oxide semiconductor layer 140 is not limited. For example, the Zn oxide may be formed of a Zn oxide, an In—Zn oxide, a Ga—In—Zn oxide, and the like, and further include other materials such as an organic material. As in the case of forming the gate electrode 121, the oxide semiconductor layer 140 overlapping the gate electrode 121 is patterned through an exposure, development, and etching process.

Subsequently, an etch stopper 150 may be formed on the oxide semiconductor layer 140 as shown in FIG. 5C.

The etch stopper 150 is formed to prevent the channel formation region of the oxide semiconductor layer 140 from being damaged during the etching process of the source and drain electrodes 161a, 162a, 161b, and 162b. To form. The etch stopper 150 may be formed by depositing an inorganic material and depositing a photoresist thereon, and then patterning the same through an exposure, development, and etching process.

Next, as shown in FIG. 5D, the first conductive layer 161 and the second conductive layer 162 are deposited to form the data electrodes and the data lines of the source electrodes 161a and 162a (S4).

At this time, the first conductive layer 161 is laminated first, and the second conductive layer 162 is laminated thereon.

In order to facilitate ohmic contact with the oxide semiconductor layer 140, the first conductive layer 161 may include titanium (Ti), titanium alloy (Ti alloy), molybdenum (Mo), and molybdenum titanium alloy (molybdenum titanium). : MoTi), aluminum (Al) or indium tin oxide (ITO) can be used.

The second conductive layer 162 may be formed of a low resistance wiring material, and copper (Cu), silver (Ag), platinum (Pt), gold (Au), and aluminum (Al) may be used.

In addition, the second conductive layer 162 may be patterned to form a second source electrode 162a and a second drain electrode 162b (S5).

First, a photoresist is laminated on the second conductive layer 162. An exposure process is performed such that only a predetermined portion of the photoresist is exposed to light by using a mask. Thereafter, the portions exposed to light or the portions not exposed to light are removed according to the properties of the photoresist. A second data line, a second source electrode 162a, a second drain electrode 162b, and a second data pad electrode 162c are formed by wet etching using the remaining photoresist as a film.

The wet etching may be performed by depositing a substrate on which a photoresist mask pattern is formed in an etchant solution or by spraying an etchant solution on the substrate using a spray nozzle to react the etching liquid with the electrode material part. The etchant may etch only the second conductive layer 162 as a solution having good selectivity.

In this case, the second source electrode 162a and the second drain electrode 162b partially overlap both ends of the oxide semiconductor layer 140, and are formed to be spaced apart from the etch stopper 150 by a predetermined interval.

Subsequently, as illustrated in FIG. 5F, the first conductive layer 161 is patterned to form a first source electrode 161a and a first drain electrode 161b.

In this case, the first data line (not shown), the first data pad electrode 161c, the first source electrode 161a, and the first drain electrode 161b are simultaneously etched and patterned, whereby dry etching is used. . In the dry etching, a method using plasma is mainly used. In order to proceed with the etching process, first, a reaction gas is injected into the dry etching apparatus, and high frequency power is applied to the upper electrode and the lower electrode in the dry etching apparatus. The electrons accelerated by the high frequency electric field formed between the lower electrodes undergo high collisions with the reaction gas molecules to obtain high energy, and then inelastic collision with the reaction gas molecules to ionize and excite the reaction gas molecules to generate plasma. Among these plasma gases, the plasma gas having a negative characteristic moves to the lower electrode by the potential difference between the upper and lower electrodes, and reacts with the dry etching member loaded on the lower electrode, and has a high vapor pressure. The etching process proceeds by producing volatiles.

Therefore, since the first source electrode 161a and the drain electrodes 161b and 162b are also formed to be spaced apart from the etch stopper 150, the upper surface of the oxide semiconductor layer 140 is exposed, and the dry etching may be performed by wet etching. Otherwise, since no etchant is used, there is no fear of damaging the exposed surface of the oxide semiconductor layer 140.

Therefore, even if the source electrodes 161a and 162a and the drain electrodes 161b and 162b reduce the overlapping area of the oxide semiconductor layer 140, the oxide semiconductor layer 140 is not affected.

The first data line (not shown), the first data pad electrode 161c, the first source electrode 161a, and the first source electrode 161a may include a second data line (not shown) and a second data pad electrode (not shown). 162c, the second source electrode 162a, and the second source electrode 162a are etched as a film, so that the second data line (not shown), the second data pad electrode 162c, the second source electrode 162a, It may be patterned in the same shape as the second source electrode 162a. Accordingly, the first and second source electrodes 161a and 162a, the first and second drain electrodes 161b and 162b, the first and second data pad electrodes 161c and 162c, and the first and second data lines Not shown) constitutes a source electrode, a drain electrode, a data pad electrode, and a data line.

As a result, the source and drain electrodes 161a, 161b, 162a, and 162b may be formed by selectively applying wet etching and dry etching using one mask process.

Subsequently, as illustrated in FIG. 5G, the first insulating layer 170 is deposited on the entire surface of the first substrate 110, and the first contact hole 171 exposing a part of the second drain electrode 162b is formed as shown in FIG. 5H. (S7)

The first insulating layer 170 may be formed of a silicon nitride film (SiNx), a silicon oxide film (SiO 2), or the like. The first contact hole 171 may be formed through a photolithography process.

Thereafter, as illustrated in FIG. 5I, the pixel electrode 175 is formed in the first contact hole 171 (S8).

The pixel electrode 175 may have a conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) on the upper surface of the first insulating layer 170. After deposition, it is formed by patterning through a photolithography process.

The pixel electrode 175 is in electrical contact with the drain electrodes 161b and 162b through the first contact hole 171 and may be formed in a single pattern in the form of a board in a region corresponding to the unit pixel.

Next, as shown in FIG. 5J, the second insulating layer 180 is formed on the top surface of the first insulating layer 170, and the second contact hole 182 and the third contact hole 183 are formed as shown in FIG. 5K. (S9)

The second contact hole 182 is formed through the first insulating layer 170, the second insulating layer 180, and the gate insulating layer 130 to expose the gate pad electrode 122, and the third contact. The hole 183 is formed through the first insulating layer 170 and the second insulating layer 180 to expose the data pad electrode.

Finally, the common electrode 195, the gate pad, and the data pad are formed (S10).

The upper conductive layers 192 and 193 of the common electrode 195, the gate pad, and the data pad may be formed of a conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The material is deposited on the top surface of the second insulating layer 180, the second contact hole 182, and the third contact hole 183, and then patterned through a photolithography process.

In this case, the common electrode 195 is formed to overlap the pixel electrode 175, and the plurality of slit-shaped first openings 195a and the second opening 195b above the thin film transistor are opened.

The liquid crystal display may be manufactured by bonding a second substrate to face the first substrate 110 after interposing a liquid crystal layer on the first substrate 110.

Hereinafter, one embodiment of the present invention will be compared with the prior art through FIGS. 7A and 7B.

Figure 7a is a cross-sectional picture of a thin film transistor according to the prior art, Figure 7b is a cross-sectional picture of a thin film transistor according to an embodiment of the present invention.

7A and 7B, the prior art and the embodiment of the present invention have different lengths of the oxide semiconductor layer in the red dotted box in the photograph.

That is, in the prior art of FIG. 7A, since the source and drain electrodes are formed by wet etching, the ends of the oxide semiconductor layer are etched by the etchant and thus disappear. Although not shown in the photo, when the wet etching is performed for a longer time, the oxide semiconductor layer may be further dug into the bottom of the source and drain electrodes.

As such, when the oxide semiconductor layer is etched away, the area of the oxide semiconductor layer is reduced, and current transfer characteristics between the source and drain electrodes are deteriorated.

However, referring to FIG. 7B, since the embodiment of the present invention undergoes a dry etching process after wet etching, the oxide semiconductor layer is not damaged by the dry etching. Thus, the oxide semiconductor layer region beyond the source and drain electrodes also remains unetched. As a result, the current transfer characteristics of the device can be preserved intact.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Accordingly, the scope of the present invention is not limited thereto, but various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims are also within the scope of the present invention.

110: first substrate 121: gate electrode
130 gate insulating film 140 oxide semiconductor layer
150: etch stopper 161: first conductive layer
161a: first source electrode 161b: first drain electrode
162: second conductive layer 162a: second source electrode
162b: second drain electrode 170: first insulating layer
175: pixel electrode 195: common electrode

Claims (10)

Forming a gate electrode and a gate insulating layer on the first substrate;
Forming an oxide semiconductor layer over the gate insulating layer and overlapping the gate electrode;
Forming an etch stopper on the oxide semiconductor layer;
Sequentially stacking a first conductive layer and a second conductive layer on the entire surface of the first substrate including the etch stopper;
Wet etching the second conductive layer to expose the first conductive layer and form a second source electrode and a second drain electrode overlapping the oxide semiconductor layer but spaced apart from each other;
Dry etching the first conductive layer to expose the etch stopper and the oxide semiconductor layer, and forming a first source electrode and a first drain electrode under the second source electrode and the second drain electrode;
Forming a first insulating layer on the first and second source electrodes and the first and second drain electrodes, and forming a pixel electrode in electrical contact with the first and second drain electrodes through a contact hole; And
Bonding the second substrate to the first substrate, the liquid crystal layer being interposed between the first substrate and the second substrate;
Liquid crystal display device manufacturing method comprising a. The method of claim 1,
And the second source electrode and the second drain electrode have the same pattern as the first source electrode and the first drain electrode. The method of claim 1,
And the first and second source electrodes, the first and second drain electrodes, and the etch stopper do not cover the entire surface of the oxide semiconductor. The method of claim 1,
The forming of the first and second source electrodes and the first and second drain electrodes may include forming the first and second source electrodes and the first and second drain electrodes spaced apart from the etch stopper. Liquid crystal display device manufacturing method. The method of claim 1,
The first conductive layer is made of any one of Ti, Mo, MoTi, Ti alloy, Al, and the second conductive layer is made of any one of Cu, Al, Ag, Pt, Au Way. The method of claim 1,
Forming a second insulating layer on the pixel electrode; And
Forming a common electrode on an area of the second insulating layer and overlapping the pixel electrode;
Liquid crystal display device manufacturing method comprising a further. The method according to claim 6,
The pixel electrode is formed in a single pattern, the common electrode is a liquid crystal display device characterized in that the box (box) having a plurality of slits. The method of claim 1,
Forming a common electrode on the second substrate;
Liquid crystal display device manufacturing method comprising a further. The method of claim 1,
Forming a common electrode on the first insulating layer; further comprising,
And forming a plurality of bars that are fingered while facing the pixel electrode and the common electrode. A first substrate;
A gate electrode formed on the first substrate;
A gate insulating layer formed on the gate electrode;
An oxide semiconductor layer formed on an upper portion of the gate insulating layer and overlapping the gate electrode;
An etch stopper formed on an upper surface of the oxide semiconductor layer;
A source electrode and a drain electrode spaced apart from the etch stopper but overlapping the oxide semiconductor layer and formed of a first conductive layer and a second conductive layer;
A first insulating layer formed on the source electrode and the drain electrode;
A pixel electrode electrically connected to the drain electrode through a contact hole on the first insulating layer;
A second insulating layer formed on the pixel electrode;
A common electrode overlapping the pixel electrode on the second insulating layer, and having a plurality of slits;
A second substrate including a color filter bonded to and opposed to the first substrate; And
A liquid crystal layer interposed between the first substrate and the second substrate;
Fringe field type liquid crystal display device comprising a.

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