KR20130044492A - Method for encoding and decoding error correction using low density parity check code - Google Patents

Method for encoding and decoding error correction using low density parity check code Download PDF

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Publication number
KR20130044492A
KR20130044492A KR1020110108584A KR20110108584A KR20130044492A KR 20130044492 A KR20130044492 A KR 20130044492A KR 1020110108584 A KR1020110108584 A KR 1020110108584A KR 20110108584 A KR20110108584 A KR 20110108584A KR 20130044492 A KR20130044492 A KR 20130044492A
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South Korea
Prior art keywords
error correction
decoding
ldpc
axis direction
correction decoding
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KR1020110108584A
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Korean (ko)
Inventor
이재진
박동혁
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숭실대학교산학협력단
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Priority to KR1020110108584A priority Critical patent/KR20130044492A/en
Publication of KR20130044492A publication Critical patent/KR20130044492A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3784—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 for soft-output decoding of block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation

Abstract

An error correction encoding method and a decoding method using an LDPC code are disclosed. The error correction decoding method using the disclosed LDPC code has a two-dimensional block structure, and has LDPC in one of a horizontal axis direction and a vertical axis direction for decoding target data including information data, horizontal parity symbols, and vertical parity symbols. Performing decoding to perform first error correction decoding; Performing second error correction decoding by performing LDPC decoding on the decoding target data in a second direction of the other of a horizontal axis direction and a vertical axis direction using the result data of the first error correction decoding; And outputting result data of the first error correction decoding and the second error correction decoding as LDPC decoded data.

Description

Error correction coding method and decoding method using LDPC code {METHOD FOR ENCODING AND DECODING ERROR CORRECTION USING LOW DENSITY PARITY CHECK CODE}

Embodiments of the present invention relate to an error correction encoding method and a decoding method, and more particularly, error correction encoding using LDPC code having good encoding / decoding performance in a long contiguous error and a random error situation occurring in a two-dimensional storage device. It relates to a method and a decoding method.

4G wireless mobile communication systems require high data transfer rates and low error rates to provide various multimedia services to users. More specifically, the fourth generation wireless mobile communication requires a data transfer rate of up to 100 Mbps at high speed and up to 155 Mbps to 1 Gbps at low speed or stop. Therefore, in order to perform high quality and high reliability communication in a poor transmission environment, channel encoding / decoding techniques must be accompanied.

The channel encoding technique may be used in various forms according to the characteristics of the channel. Basically, a technique for encoding / decoding a signal using an error correcting code is commonly used.

The error correction code is used to achieve reliable communication on an unreliable channel. As a representative example, an encoding / decoding technique using a Reed-Solomon (RS) code, low density parity Encoding / decoding techniques using a check (LDPC: Low Density Parity Check) code.

On the other hand, as a conventional technique related to the error correction decoding method, in the open article "Novel Error Correcting System Based on Product Codes for Future Magnetic Recording Channels", when the information data is stored in a two-dimensional block structure, it is deleted and decoded using RS code. After performing (Erasure Decoding), there is disclosed a method (error correction decoding method using RS-LDPC Product) to decode the information data using the result of the erase decoding.

However, the above-described prior art has excellent performance in concatenation error, but when a large number of random errors occur, and the erasure decision is large when decoding using the RS code, the performance in decoding using the LDPC code can be corrected. There was a problem that can not be.

In order to solve the problems of the prior art as described above, the present invention provides an error correction encoding method and a decoding method using an LDPC code having good encoding / decoding performance in a long contiguous error and a random error situation occurring in a two-dimensional storage device. I would like to suggest.

Other objects of the present invention may be derived by those skilled in the art through the following examples.

In order to achieve the above object, according to an embodiment of the present invention, first parity is performed by performing LDPC encoding on one of a horizontal axis and a vertical axis of information data having a two-dimensional block structure. Generating a symbol; Generating a second parity symbol by performing LDPC encoding on the information data in a second direction of another one of a horizontal axis direction and a vertical axis direction; Merging the first parity symbol and the second parity symbol into the information data; And outputting the merged result data as LDPC encoded data.

Further, according to another embodiment of the present invention, having a two-dimensional block structure, in the first direction of any one of the abscissa direction and the ordinate direction for decoding target data including information data, abscissa parity symbols, and ordinate parity symbols. Performing first error correction decoding by performing LDPC decoding; Performing second error correction decoding by performing LDPC decoding on the decoding target data in a second direction of the other of a horizontal axis direction and a vertical axis direction using the result data of the first error correction decoding; And outputting the result data of the first error correction decoding and the second error correction decoding as LDPC decoded data.

In this case, performing the first error correction decoding may perform LDPC decoding in the horizontal axis direction, and performing the second error correction decoding may perform LDPC decoding in the vertical axis direction.

In addition, the performing of the first error correction decoding and the performing of the second error correction decoding may be repeatedly performed for a predetermined number of times.

In this case, the predetermined number of times may be set based on at least one of the number of the horizontal parity symbols, the number of the vertical parity symbols, and the noise detection level of the channel through which the decoding target data is transmitted.

The error correction coding method and the decoding method using the LDPC code according to the present invention have an advantage of having good encoding / decoding performance in both a long concatenated error and a random error situation generated in a 2D storage device.

1 is a flowchart illustrating the overall flow of an error correction encoding method using an LDPC code according to an embodiment of the present invention.
2 is a diagram illustrating a structure of result data according to an error correction encoding method using an LDPC code according to an embodiment of the present invention.
3 is a flowchart illustrating the overall flow of an error correction decoding method using an LDPC code according to an embodiment of the present invention.
4 is a block diagram illustrating a schematic configuration of an error correction encoding / decoding system using an LDPC code according to an embodiment of the present invention.
5 is a view for explaining the performance of the error correction decoding method using the LDPC code according to an embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a flowchart illustrating an overall flow of an error correction encoding method using an LDPC code according to an embodiment of the present invention, and FIG. 2 is a result of an error correction encoding method using an LDPC code according to an embodiment of the present invention. It is a figure which shows the structure of data (LDPC coded data). A process performed for each step will be described in detail with reference to FIGS. 1 and 2.

First, in step S110, information data is input, and in step S120, the input information data is stored in the two-dimensional block structure 210.

Subsequently, in step S130, the first parity symbol is generated by performing LDPC encoding on one of the horizontal axis direction 240 and the vertical axis direction 250 for the information data having the two-dimensional block structure. In operation S140, the second parity symbol is generated by performing LDPC encoding on the information data having the two-dimensional block structure in the second direction of the other of the horizontal axis direction 240 and the vertical axis direction 250.

As an example, in step S130, the LDPC encoding is performed in the horizontal direction 240 to generate the horizontal parity symbol 220, and in step S140, the LDPC encoding is performed in the vertical direction 250 to perform the vertical parity symbol 230. ) Can be created.

Subsequently, in step S150, the first parity symbol (horizontal parity symbol 220) and the second parity symbol (vertical parity symbol 230) are merged with the information data 210, and in step S160, the merged information is merged. The result data 260 is output as LDPC coded data.

3 is a flowchart illustrating the overall flow of an error correction decoding method using an LDPC code according to an embodiment of the present invention.

Here, the error correction decoding method using the LDPC code according to an embodiment of the present invention is performed on the result data 260 generated by the error correction coding method using the LDPC code described above in Figure 1 to be.

Hereinafter, a process performed for each step will be described in detail with reference to FIGS. 2 and 3.

First, in step S310, the horizontal direction 240 is performed on the decoding target data 260 having the two-dimensional block structure and including the information data 210, the horizontal parity symbol 220, and the vertical parity symbol 230. And the first error correction decoding by performing LDPC decoding in any one of the longitudinal directions 250.

In operation S320, LDPC decoding is performed in the second direction of one of the horizontal axis direction 240 and the vertical axis direction 250 with respect to the decoding target data 260 using the result data of the first error correction decoding. To perform the second error correction decoding.

According to an embodiment of the present invention, in step S310, LDPC decoding is performed on the decoding target data 260 in the horizontal axis direction 240, and in step S320, the horizontal axis is targeted on the decoding target data 260. LDPC decoding may be performed using the result data of the LDPC decoding in the direction 240.

Subsequently, in step S330, it is determined whether the number of times of the first error correction decoding and the second error correction decoding is a predetermined number or more. In this case, the predetermined number of times may be set based on at least one of the number of horizontal parity symbols, the number of vertical parity symbols, and the noise detection level of the channel to which the decoding target data is transmitted.

If it is determined in step S330 that the number of times of the first error correction decoding and the second error correction decoding is smaller than the predetermined number of times, steps S310 and S320 are repeatedly performed. On the contrary, when it is determined in step S330 that the number of times of the first error correction decoding and the second error correction decoding is more than a predetermined number, in step S340, the first error correction decoding and the second error correction decoding are performed. The result data is output as LDPC decoded data.

4 is a block diagram illustrating a schematic configuration of an error correction encoding / decoding system using an LDPC code according to an embodiment of the present invention.

Referring to FIG. 4, an error correction encoding / decoding system 400 using an LDPC code according to an embodiment of the present invention includes a first LDPC encoder (LDPC1 encoder) 410 and a second LDPC encoder (LDPC2 encoder). 420, merger 430, bit patterned media (BPM) 440, equalizer 450, soft output viterbi algorithm 460, first LDPC decoder 470, and second LDPC decoder 480 is included.

The first LDPC encoder 410 performs LDPC encoding on the information data D in the horizontal axis direction to generate a horizontal parity symbol P1, and the second LDPC encoder 420 generates the information data D in the vertical axis direction. LDPC encoding is performed to generate a vertical parity symbol (P2).

The merger 430 merges the information data D, the horizontal parity symbol P1, and the vertical parity symbol P2 to output LDPC coded data, and the BPM 440 converts the LDPC coded data into a two-dimensional structure. Save it. Thus, error correction coding using the LDPC code is completed.

The LDPC coded data includes first decoding target data including the information data D and the horizontal axis parity symbol P1, the information data D, and the vertical axis parity symbol P2 through the equalizer 450 and the SOVA 460. Is extracted as second decoding target data.

The first LDPC decoding unit 470 performs LDPC decoding on the first decoding target data, and the second LDPC decoding unit 480 targets the second decoding target data using the first decoding result data EI. LDPC decoding is performed.

5 is a view for explaining the performance of the error correction decoding method using the LDPC code according to an embodiment of the present invention.

In FIG. 5, simul 1 is a graph showing the performance of the conventional error correction decoding method using the RS-LDPC Product, simul 2 is a diagram showing the performance of the error correction decoding method using the LDPC code according to the present invention.

Referring to FIG. 5, it can be seen that the error correction decoding method using the LDPC code according to the present invention has better performance in random / contiguous errors than in the prior art.

As described above, the conventional error correction decoding method using the RS-LDPC product has good performance in the concatenated error, but when the error of the RS increases due to a lot of random errors, the performance cannot be properly performed in the LDPC code. However, in the error correction decoding method using the LDPC code according to the present invention, the error correction of the LDPC code is first performed to reduce the Erasure judgment due to many random errors according to the Erasure decoding, and then information is transmitted to the second LDPC through the Erasure decoding. To prevent deterioration of performance. Accordingly, the detection performance can be improved, and applied to a two-dimensional storage device to play a role in driving commercialization.

In addition, embodiments of the present invention may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the medium may be those specially designed and constructed for the present invention or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Examples of program instructions, such as magneto-optical and ROM, RAM, flash memory and the like, can be executed by a computer using an interpreter or the like, as well as machine code, Includes a high-level language code. The hardware device described above may be configured to operate as one or more software modules to perform the operations of one embodiment of the present invention, and vice versa.

As described above, the present invention has been described with reference to particular embodiments, such as specific elements, and limited embodiments and drawings. However, it should be understood that the present invention is not limited to the above- Various modifications and variations may be made thereto by those skilled in the art to which the present invention pertains. Accordingly, the spirit of the present invention should not be construed as being limited to the embodiments described, and all of the equivalents or equivalents of the claims, as well as the following claims, belong to the scope of the present invention .

Claims (6)

Generating first parity symbols by performing LDPC encoding on one of a horizontal axis direction and a vertical axis direction for information data having a two-dimensional block structure;
Generating a second parity symbol by performing LDPC encoding on the information data in a second direction of another one of a horizontal axis direction and a vertical axis direction;
Merging the first parity symbol and the second parity symbol into the information data; And
Outputting the merged result data as LDPC encoded data
Error correction encoding method comprising a. A first error correction decoding method is performed by performing LDPC decoding on one of a horizontal axis direction and a vertical axis direction of decoding target data having a two-dimensional block structure and including information data, a horizontal parity symbol, and a vertical parity symbol. Performing;
Performing second error correction decoding by performing LDPC decoding on the decoding target data in a second direction of the other of a horizontal axis direction and a vertical axis direction using the result data of the first error correction decoding; And
Outputting result data of the first error correction decoding and the second error correction decoding as LDPC decoded data;
Error correction decoding method comprising a. The method of claim 2,
The performing of the first error correction decoding may be performed by performing LDPC decoding in a horizontal axis direction.
The performing of the second error correction decoding may include performing LDPC decoding in the longitudinal direction. The method of claim 2,
And performing the first error correction decoding process and the second error correction decoding process repeatedly performed for a predetermined number of times. 5. The method of claim 4,
And the predetermined number of times is set based on at least one of the number of the horizontal parity symbols, the number of the vertical parity symbols, and the noise detection level of the channel through which the decoding target data is transmitted. A computer-readable recording medium having recorded thereon a program for performing the method of any one of claims 2 to 5.
KR1020110108584A 2011-10-24 2011-10-24 Method for encoding and decoding error correction using low density parity check code KR20130044492A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110751977A (en) * 2019-10-18 2020-02-04 西安工业大学 Memory chip fault-tolerant device and fault-tolerant error-correcting method based on LDPC code

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110751977A (en) * 2019-10-18 2020-02-04 西安工业大学 Memory chip fault-tolerant device and fault-tolerant error-correcting method based on LDPC code

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