KR20130044405A - Semiconductor chip package with insulating tape for protecting the chip from esd - Google Patents

Semiconductor chip package with insulating tape for protecting the chip from esd Download PDF

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Publication number
KR20130044405A
KR20130044405A KR1020110108440A KR20110108440A KR20130044405A KR 20130044405 A KR20130044405 A KR 20130044405A KR 1020110108440 A KR1020110108440 A KR 1020110108440A KR 20110108440 A KR20110108440 A KR 20110108440A KR 20130044405 A KR20130044405 A KR 20130044405A
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South Korea
Prior art keywords
chip
insulating tape
metal layer
solder resist
protecting
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KR1020110108440A
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Korean (ko)
Inventor
강석훈
임준성
홍성원
신세철
최영민
전민호
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주식회사 루셈
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Priority to KR1020110108440A priority Critical patent/KR20130044405A/en
Publication of KR20130044405A publication Critical patent/KR20130044405A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A semiconductor chip package with insulating tape is provided to protect a chip from ESD generated in a solder resist region by surrounding a part of the solder resist region and the whole region of the chip with insulating tape. CONSTITUTION: A chip(10) includes a bump(13). A protection layer made of insulating tape(80) is formed in the outer surface of a chip. A metal layer(30) forms a lead connected to the bump in the lower surface of the chip. A solder resist(20) connects the lead of the metal layer to the bump. A support layer(50) is arranged in the lower surface of the metal layer and functions as a substrate. An insulating layer(40) made of resin is arranged between the chip and the support layer.

Description

외부 정전기로부터 칩을 보호하기 위한 절연테이프를 구비한 칩 패키지 {Semiconductor chip package with insulating tape for protecting the chip from ESD}Chip package with insulating tape for protecting the chip from external static electricity

본 발명은 반도체 칩 패키지에 관한 것으로서, 보다 상세하게는, 외부의 정전기로부터 칩을 보호할 수 있는 구조의 반도체 칩 패키지에 관한 것이다.The present invention relates to a semiconductor chip package, and more particularly, to a semiconductor chip package having a structure capable of protecting a chip from external static electricity.

도 1 은 일반적인 칩 패키지의 구조를 도시한 것이다. 칩 패키지는 범프(13)를 구비한 칩(10), 칩(10)의 하면에서 범프(13)와 연결된 리드를 형성하는 금속층(30), 금속층(30)의 리드들을 범프(13)와 연결시키는 솔더레지스트(20), 금속층(30)의 하면에 배치되어 칩(10)이 장착되는 기판의 기능을 하는 지지층(50), 및 칩(10)과 지지층(50) 사이에 배치된 수지 재질의 절연층(40)을 구비하고 있다.1 illustrates a structure of a general chip package. The chip package connects the chip 10 having the bumps 13, the metal layer 30 forming a lead connected to the bump 13 on the bottom surface of the chip 10, and the leads of the metal layer 30 with the bump 13. To the solder resist 20, the support layer 50 disposed on the lower surface of the metal layer 30 to function as a substrate on which the chip 10 is mounted, and the resin material disposed between the chip 10 and the support layer 50. The insulating layer 40 is provided.

이러한 칩 패키지가 PCB 등과 같은 전장품에 장착되어 사용되는 동안 칩(10)은 지속적으로 외부의 정전기(ESD : Electrostatic Discharge)에 노출된다. 정전기는 칩(10)의 동작에 치명적인 오류를 야기하거나 칩(10) 자체의 손상을 가져오므로, 정전기로부터 칩을 보호하기 위한 방안이 다양하게 강구되어 왔다.While the chip package is mounted on and used in an electronic device such as a PCB, the chip 10 is continuously exposed to external electrostatic discharge (ESD). Since static electricity causes a fatal error in the operation of the chip 10 or damages the chip 10 itself, various methods for protecting the chip from static electricity have been devised.

종래의 일반적인 정전기 보호 구조는, 예컨대 제너다이오드나 바리스터 같은 소자를 이용하여 칩(10)에 가해지는 정전기를 소진시키는 방식이 채용되어 왔다. 그러나, 이러한 종래의 구조는 칩(10)의 제작시 별도의 소자 형성 과정과 소자와 전기적으로 연결하기 위한 공정을 필요로 하므로 고비용이 소모된다.As a conventional general static electricity protection structure, a method of dissipating static electricity applied to the chip 10 by using a device such as a zener diode or a varistor has been adopted. However, such a conventional structure requires a separate device forming process and a process for electrically connecting the device when the chip 10 is manufactured, which consumes high cost.

그 밖에 칩(10)의 외면을 수지로 밀봉하는 방식이 존재하나, 수지 밀봉은 칩(10)을 외부의 충격이나 외부 환경 요인의 변화로부터 보호하기 위한 것으로서 정전기로부터의 보호를 목적으로 하지는 않는다. 따라서 이런 방식은 일정 수준 이상의 정전기로부터의 보호 효과는 간접적으로 얻을 수 있을지언정, 정전기로부터의 보호할 수 있는 근본적인 방법이 되지는 못한다.In addition, there is a method of sealing the outer surface of the chip 10 with a resin, but the resin sealing is to protect the chip 10 from external impact or changes in external environmental factors, and is not intended to protect from static electricity. Therefore, this method may indirectly obtain a certain level of protection from static electricity, but it is not a fundamental way to protect against static electricity.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 본 발명의 목적은 칩 패키지에 장착된 칩을 외부의 정전기로부터 보호할 수 있으면서도 그 비용이 적게 소요되어 경제적인 방안을 제시하는 것이다.The present invention has been made to solve the above problems, and an object of the present invention is to provide a cost-effective solution while protecting the chip mounted in the chip package from external static electricity.

상기 목적을 달성하기 위한 본 발명에 따른 칩 패키지는, 상기 칩의 외면을 감싸도록 부착되어 외부 ESD 로부터 상기 칩을 보호하기 위한 절연테이프를 포함하는 것을 특징으로 한다.The chip package according to the present invention for achieving the above object is characterized in that it comprises an insulating tape attached to surround the outer surface of the chip to protect the chip from external ESD.

상기 절연테이프는 상기 칩의 전체 영역과 상기 솔더레지스트 영역의 적어도 일 부분을 감싸도록 구성되는 것이 바람직하다.The insulating tape may be configured to surround at least a portion of the entire area of the chip and the solder resist area.

본 발명에 따르면, 칩의 외면을 감싸는 절연테이프에 의하여 칩 패키지에 장착된 칩이 외부의 정전기로부터 보호되는 경제적인 방안이 제시된다.According to the present invention, an economical method for protecting a chip mounted on a chip package from an external static electricity by an insulating tape surrounding an outer surface of the chip is proposed.

도 1 은 종래의 일반적인 칩 패키지의 구조를 도시한 도면.
도 2 는 본 발명에 따른 칩 패키지의 구조를 도시한 도면.1 is a view showing the structure of a conventional general chip package.
2 shows the structure of a chip package according to the invention;

이하에서는 첨부 도면을 참조하여 본 발명을 보다 구체적으로 설명한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

도 2 는 본 발명에 따른 칩 패키지의 구조를 도시한 도면이다. 도 2 에서, 종래 기술과 실질적으로 동일한 구성요소에 대해서는 도시 및 설명의 편의상 동일한 참조부호를 부여하여 인용한다.2 is a view showing the structure of a chip package according to the present invention. In FIG. 2, the same reference numerals are used to refer to the same elements as those in the prior art for convenience of illustration and description.

본 발명에 따른 칩 패키지는, 도 2 의 칩 패키지와 마찬가지로, 범프(13)를 구비한 칩(10), 칩(10)의 하면에서 범프(13)와 연결된 리드를 형성하는 금속층(30), 금속층(30)의 리드들을 범프(13)와 연결시키는 솔더레지스트(20), 금속층(30)의 하면에 배치되어 칩(10)이 장착되는 기판의 기능을 하는 지지층(50), 및 칩(10)과 지지층(50) 사이에 배치된 수지 재질의 절연층(40)을 구비하고 있다.The chip package according to the present invention includes a chip 10 having bumps 13, a metal layer 30 forming a lead connected to bumps 13 on a bottom surface of the chip 10, like the chip package of FIG. 2, A solder resist 20 connecting the leads of the metal layer 30 to the bump 13, a support layer 50 disposed on the bottom surface of the metal layer 30 to function as a substrate on which the chip 10 is mounted, and the chip 10. ) And a resin insulating layer 40 disposed between the support layer 50.

칩(10)의 외면에는 본 발명에 따른 절연테이프(80)로 이루어진 보호층이 구비되어 있다. 절연테이프(80)는 칩(10)을 감싸도록 얇은 박층의 형태로 칩(10)에 부착되어, 외부 ESD 로부터 칩(10)을 보호하는 기능을 한다.The outer surface of the chip 10 is provided with a protective layer made of an insulating tape 80 according to the present invention. The insulating tape 80 is attached to the chip 10 in the form of a thin thin layer to surround the chip 10, thereby protecting the chip 10 from external ESD.

절연테이프(80)가 칩(10)의 보호 기능을 충실하게 하기 위하여, 바람직하게는 칩(10)의 전체 영역을 덮도록 구성된다.The insulating tape 80 is preferably configured to cover the entire area of the chip 10 in order to enhance the protection function of the chip 10.

나아가, 절연테이프(80)는 도 2 에 도시된 바와 같이 칩(10)의 전체 영역과 함께 솔더레지스트(20) 영역의 적어도 일 부분을 감싸도록(더욱 바람직하게는 솔더레지스트의 전체 영역을 감싸도록) 구성된다. 이에 따르면 외부의 정전기가 솔더레지스트 영역(20)에 가해지는 경우에도 절연테이프(80)에 의해 칩(10)이 정전기로부터 보호된다.Furthermore, the insulating tape 80 covers at least a portion of the solder resist 20 region together with the entire region of the chip 10 as shown in FIG. 2 (more preferably, to cover the entire region of the solder resist). Is composed). Accordingly, even when external static electricity is applied to the solder resist region 20, the chip 10 is protected from the static electricity by the insulating tape 80.

10 : 칩 20 : 솔더레지스트
30 : 금속층 40 : 절연층
50 : 지지층 80 : 절연테이프10 chip 20 solder resist
30: metal layer 40: insulating layer
50: support layer 80: insulating tape

Claims (2)

칩, 상기 칩의 하면에서 상기 칩의 범프와 연결된 리드를 형성하는 금속층, 상기 금속층의 하면에 배치된 절연 재질의 지지층, 및 상기 금속층 위에 형성된 솔더레지스트 영역을 구비한 칩 패키지에 있어서,
상기 칩의 외면을 감싸도록 부착되어, 외부 ESD 로부터 상기 칩을 보호하기 위한 절연테이프를 포함하는 것을 특징으로 하는 칩 패키지.
A chip package having a chip, a metal layer forming a lead connected to bumps of the chip on a bottom surface of the chip, a support layer of an insulating material disposed on a bottom surface of the metal layer, and a solder resist region formed on the metal layer,
And an insulating tape attached to surround an outer surface of the chip to protect the chip from external ESD.
제 1 항에 있어서,
상기 절연테이프는 상기 칩의 전체 영역과 상기 솔더레지스트 영역의 적어도 일 부분을 감싸도록 구성되는 것을 특징으로 하는 칩 패키지.The method of claim 1,
And the insulating tape is configured to cover the entire area of the chip and at least a portion of the solder resist area.
KR1020110108440A 2011-10-24 2011-10-24 Semiconductor chip package with insulating tape for protecting the chip from esd KR20130044405A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015000226A1 (en) * 2013-07-05 2015-01-08 京东方科技集团股份有限公司 Esd device manufacturing method, esd device and display panel
USD884038S1 (en) 2018-06-11 2020-05-12 Samsung Electronics Co., Ltd. Drawer for refrigerator
US10921853B2 (en) 2019-04-30 2021-02-16 Samsung Display Co., Ltd. Display device and method of fabricating the same
EP4177707A3 (en) * 2021-11-04 2023-08-02 Samsung Display Co., Ltd. Display device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015000226A1 (en) * 2013-07-05 2015-01-08 京东方科技集团股份有限公司 Esd device manufacturing method, esd device and display panel
USD884038S1 (en) 2018-06-11 2020-05-12 Samsung Electronics Co., Ltd. Drawer for refrigerator
US10921853B2 (en) 2019-04-30 2021-02-16 Samsung Display Co., Ltd. Display device and method of fabricating the same
EP4177707A3 (en) * 2021-11-04 2023-08-02 Samsung Display Co., Ltd. Display device

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