KR20130042374A

KR20130042374A - Method for controlling write retry operation and storage device applying the same

Info

Publication number: KR20130042374A
Application number: KR1020110106640A
Authority: KR
Inventors: 전진완
Original assignee: 시게이트 테크놀로지 인터내셔날
Priority date: 2011-10-18
Filing date: 2011-10-18
Publication date: 2013-04-26

Abstract

PURPOSE: A write retry operation control method and a storage device using the same are provided to partially perform data write from a position in which a write defect occurs when write retry operation is performed. CONSTITUTION: A write start point is determined to perform the write skip of a written area in a sector to perform write retry(S101). Write operation is performed from the write start point(S102). A data size of the sector is set to be larger than the storage capacity of one servo section. The sector is composed of sub sectors. One of the sub sectors is determined as the write start point. [Reference numerals] (AA) Start; (BB) End; (S101) Determining a write start point to be write retried; (S102) Performing a write operation from the determined write start point;

Description

Method for controlling write retry operation and storage device applying the same}

The present invention relates to a method and apparatus for controlling data write operations for a storage medium, and more particularly, to a method and apparatus for controlling a write retry operation in a storage device.

A disk drive, which is one of the storage devices, contributes to the operation of a computer system by writing data to or reading data from a storage medium according to a command issued from a host device. The disk drive performs a write retry operation when a write fault occurs during the write operation. However, as the sector size increases, the possibility of write defects occurring in one sector increases. Accordingly, there is a need for a technique for efficiently performing the write retry operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of partially performing a write retry from an area where data is not normally written when a write defect is detected in a storage device.

Another object of the present invention is to provide a storage device that partially performs a write retry from an area in which data is not normally written when a write defect is detected.

According to one or more exemplary embodiments, a method of controlling a write retry operation according to an embodiment of the present disclosure may include determining a write start position such that a written area is skipped in a sector to be rewritten, and the determined write start position is determined. Performing a write operation.

According to an embodiment of the inventive concept, the data size of the sector may be set larger than the storage capacity of one servo section.

According to an embodiment of the inventive concept, the sector may include a plurality of sub-sectors, and a start position of one sub-sector among the plurality of sub-sectors may be determined as a write start position.

According to an embodiment of the inventive concept, it is preferable that a section of the sector is determined by a sector pulse, and the section of the sector is divided into subsectors based on a servo gate signal.

According to an embodiment of the inventive concept, it is preferable to determine, as a write start position, a start position of a subsector in which a write defect occurs among a plurality of subsectors included in a sector to be rewritten.

According to an embodiment of the inventive concept, the performing of the write operation may be performed based on a write start control signal generated based on the determined write start position and a sector pulse indicating the start of a sector to be rewritten. And generating a write enable signal by performing a logical multiplication on the generated light gate signal, and performing a write operation according to the write enable signal.

According to another aspect of the inventive concept, a storage device includes a storage medium, a storage medium interface for accessing or writing data to and accessing the storage medium, and a write skip such that a written area is skipped in a sector to be rewritten. And a processor configured to determine a start position and to generate a write control signal for performing a write operation from the determined write start position, wherein the storage medium interface writes data to the storage medium according to the write control signal. It is done.

According to an embodiment of the inventive concept, the processor may include a write start control signal generated based on the determined write start position and a write gate generated based on a sector pulse indicating the start of a sector to be rewritten. It is preferable to generate a write enable signal by performing a logical multiplication on the signal.

According to an embodiment of the inventive concept, the storage medium interface may generate a write current for writing data to the storage medium according to the write enable signal.

According to an embodiment of the inventive concept, the storage medium interface is

A read / write operation for generating a write enable signal by performing a logical multiplication on a write start control signal generated based on the determined write start position and a write gate signal generated based on a sector pulse representing a start of a sector to be rewritten It is preferable to include a channel and a pre-amplifier for generating a write current according to the write enable signal and applying it to the light head.

According to the present invention, when a light defect is detected during a write operation, an area already written normally is skipped, and data writing is started from an area where the light defect has occurred, thereby reducing the possibility of additional write retries. Effect occurs.

That is, the redundant write operation on the region where the writing is normally performed in the defective sector region is avoided, and the write operation by the write retry is performed from the region where the defect is generated, thereby performing the writing operation in the region where the writing is normally performed. An effect can be prevented from generating additional light retries due to redundant write operations.

Then, the data read operation of the read / write channel of the disk drive is performed without changing the data processing operation of the disk drive, and the write current is partially performed in the sector where the write defect has occurred in a manner that controls the write current output timing of the preamplifier. Even if the chip for the write channel is used as it is, the effect that can achieve the objective of this invention is produced.

1A is a block diagram of a computer system according to an embodiment of the inventive concept.
1B is a configuration diagram of a computer system according to another exemplary embodiment of the inventive concept.
2 is a software operating system diagram of a storage device according to an embodiment of the inventive concept.
3 is a plan view of a head disk assembly of a disk drive according to an embodiment of the inventive concept.
4A is an electrical configuration diagram of a disk drive according to an embodiment of the inventive concept.
4B is an electrical configuration diagram of a disk drive according to another embodiment of the inventive concept.
5 is a plan view of a slider included in a disk drive according to an embodiment of the inventive concept.
6 is a cross-sectional view of the head mounted on the slider shown in FIG. 5.
7A and 7B are diagrams showing examples of a sector structure for one track of a disk which is a storage medium to which the present invention is applied.
FIG. 8 is a diagram showing the structure of the servo information area shown in FIGS. 7A and 7B.
9 is a block diagram of a write retry operation control apparatus according to an embodiment of the present invention.
10 is a diagram illustrating an example of a configuration of a preamplifier circuit of a disk drive according to an embodiment of the inventive concept.
FIG. 11 is a diagram illustrating another example of a configuration of a preamplifier circuit of a disk drive according to an embodiment of the inventive concept.
12 is a flowchart illustrating a write retry operation control method according to an embodiment of the present invention.
FIG. 13 is a detailed flowchart of a process of performing a write retry operation illustrated in FIG. 12.
14 is a flowchart illustrating a write operation control method in a disk drive according to an embodiment of the present invention.
15 is a detailed flowchart of a process of performing a write retry operation illustrated in FIG. 14.
16 is a timing chart of main control signals when a normal write operation is performed in a storage device according to an embodiment of the present invention.
17 is a timing chart of main control signals when a write defect is detected in the storage device according to an exemplary embodiment.
18 is a timing chart of main control signals when a write retry operation is performed in a storage device according to an exemplary embodiment.

Embodiments according to the spirit of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the inventive concept may be modified in many different forms and should not be construed as limited to the scope of the invention as set forth below. Embodiments according to the spirit of the present invention are provided to more completely describe the present invention to those skilled in the art. In the accompanying drawings, like numerals always mean like elements.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1A, a computer system according to an embodiment of the inventive concept includes a storage device 1000A, a host device 2000, and a connector 3000.

In detail, the storage device 1000A may include a processor 110, a ROM 120, a RAM 130, a storage medium interface (storage medium I / F; 140), a storage medium 150, and a host interface (HOST I). / F (160) and a bus (BUS) 170.

The host device 2000 issues a command for operating the storage device 1000A, transmits the command to the storage device 1000A connected through the connector 3000, and transmits data with the storage device 1000 according to the issued command. Follow the process of getting or receiving.

The connector 3000 is a means for electrically connecting the interface port of the host device 2000 and the interface port of the storage device 1000A. The connector 3000 may include a data connector and a power connector. For example, in case of using a Serial Advanced Technology Attachment (SATA) interface, the connector 3000 may include a 7-pin SATA data connector and a 15-pin SATA power connector.

First, the constituent means of the storage device 1000A will be described.

The processor 110 interprets the command and controls the constituent means of the data storage device according to the interpreted result. The processor 110 includes a code object management unit, and loads the code object stored in the storage medium 150 into the RAM 130 using the code object management unit. The processor 110 loads the code objects into the RAM 130 for executing the method according to the flowcharts of FIGS. 12 to 15.

Then, the processor 110 may execute a task for the method according to the flowcharts of FIGS. 12 to 15 using the code objects loaded in the RAM 130. The write operation control method and the write retry operation control method executed by the processor 110 will be described in detail with reference to FIGS. 12 to 15 below.

The ROM (Read Only Memory) 120 stores program codes and data necessary for operating the data storage device.

In the random access memory (RAM) 130, program codes and data stored in the ROM 120 or the storage medium 150 are loaded under the control of the processor 110.

The storage medium 150 may include a disk or a nonvolatile semiconductor memory device as a main storage medium of the storage device. The storage device may include a disk drive as an example, and the detailed configuration of the head disk assembly 100 including the disk and the head in the disk drive is shown in FIG. 3.

Referring to FIG. 3, the head disk assembly 100 includes at least one disk 12 that is rotated by the spindle motor 14. The disk drive also includes a head 16 positioned adjacent to the disk 12 surface.

The head 16 can read or write information to the rotating disk 12 by sensing and magnetizing the magnetic field of each disk 12. Typically the head 16 is coupled to the surface of each disk 12. Although depicted and described as a single head 16, it should be understood that this consists of a head for writing to magnetize the disc 12 and a separate reading head for sensing the magnetic field of the disc 12. The read head is constructed from Magneto-Resistive (MR) elements. The head 16 may also be referred to as a magnetic head or a transducer.

Head 16 may be integrated into slider 20. The slider 20 is configured to create an air bearing between the head 16 and the surface of the disk 12. The slider 20 is coupled to the head gimbal assembly 22. The head gimbal assembly 22 is attached to an actuator arm 24 having a voice coil 26. The voice coil 26 is located adjacent to the magnetic assembly 28 to specify a voice coil motor 30 (VCM). The current supplied to the voice coil 26 generates a torque for rotating the actuator arm 24 relative to the bearing assembly 32. Rotation of the actuator arm 24 causes the head 16 to move across the disk 12 surface.

5 illustrates a detailed structure of the slider 20 according to the technical spirit of the present invention.

As shown in FIG. 5, the surface of the slider 20 is formed with patterns 20-1 for creating an air bearing between the surfaces of the disk 12. The slider 20 has a structure in which the head 16 is mounted.

FIG. 6 is a cross-sectional view of the head 16 taken along the line AA ′ of FIG. 5. As shown in FIG. 6, the head 16 includes a reader 16-1 and a writer 16-2. In detail, the reader 16-1 includes a magnetoresistive element 6D mounted between a pair of shields 6C and 6E and a pair of shields 6C and 6E. The writer 16-2 includes a main pole 6F for applying a magnetic field to the disk 12, a return yoke 6G and a main pole 6F for forming a magnetic path together with the main pole 6F. ), A coil 6H for inducing a magnetic field. The head 16 is mounted on the slider body 6A made of AlTiC and has a structure surrounded by a protective layer 134 made of alumina (Al ₂ O ₃ ). Here, the width of the reader 16-1 corresponds to the width of the surface opposite to the disk 12 of the MR element 6D.

Referring again to FIG. 3, the information is typically stored in an annular track of the disc 12. Each track 34 includes a plurality of sectors. Examples of sector configuration for one track are shown in FIGS. 7A and 7B.

One track is composed of servo information areas S in which servo information is recorded and a data sector D in which data is stored. The data sector D may also be referred to simply as a sector.

As shown in FIG. 7A, one servo period T may include a plurality of data sectors D. FIG. According to FIG. 7A, the data size of one data sector is set smaller than the storage capacity of one servo section T. FIG. As an example, the sector size may be set to a 512 byte size.

In addition, as illustrated in FIG. 7B, one data sector D1 may be distributed over the plurality of servo sections T. FIG. According to FIG. 7B, the data size of one data sector is set larger than the storage capacity of one servo section T. FIG. As an example, one data sector D1 may be distributed and stored in three servo sections. That is, in FIG. 7B, D1_1, D1_2, and D1_3 represent data included in one data sector as a subsector. As an example, the sector size may be set to a 4K byte size.

In each servo information area S, signals as shown in FIG. 8 are recorded in detail.

As illustrated in FIG. 8, a preamble 101, a servo synchronization display signal 102, a gray code 103, and a burst signal 104 are recorded in the servo information area S. FIG.

The preamble 101 provides clock synchronization when reading servo information, and also provides a constant timing margin by leaving a gap in front of the servo sector. Then, it is used to determine the gain (not shown) of the automatic gain control (AGC) circuit.

The servo synchronization display signal 102 is composed of a servo address mark (SAM) and a servo index mark (SIM). The servo address mark is a signal indicating the start of a servo sector, and the servo index mark is a signal indicating the start of the first servo sector in the track.

The gray code 103 provides the track information, and the burst signal 104 is the signal used to control the head 16 to follow the center of the track 34. As an example, the burst signal 104 may be composed of two or more patterns, and specifically, may be composed of four patterns or two patterns. Then, the burst patterns are combined to generate a position error signal used in the track following control.

Referring again to FIG. 3, the disc 12 is divided into a maintenance cylinder region inaccessible to the user and a user data region accessible by the user. The maintenance cylinder area is also called a system area. In the maintenance cylinder area, various kinds of information for controlling the disk drive are stored. In particular, information necessary to perform the write operation control method and the write retry operation control method according to the present invention is also stored in the maintenance cylinder region.

The head 16 is moved across the surface of the disc 12 to read or write information on other tracks. The disk 12 may store a plurality of code objects for implementing various functions as a disk drive. As an example, a code object for performing an MP3 player function, a code object for performing a navigation function, a code object for performing various video games, and the like may be stored in the disk 12.

Referring back to FIG. 1A, the storage medium interface 140 is a component that processes the processor 110 to access the storage medium 150 to write or read information. The storage medium interface 140 in a storage device implemented as a disk drive includes a servo circuit for controlling the head disk assembly 100 in detail and a read / write channel circuit for performing signal processing for data read / write.

The host interface 160 is a means for executing data transmission / reception processing with the host device 2000 such as a personal computer, a mobile device, and the like, for example, a Serial Advanced Technology Attachment (SATA) interface and a Parallel Advanced Technology Attachment (PATA) interface. Various standard interfaces such as USB and Universal Serial Bus (USB) interfaces are available.

The bus 170 serves to transfer information between the constituent means of the storage device.

Next, a software operating system of a hard disk drive, which is an example of a storage device, will be described with reference to FIG. 2.

As illustrated in FIG. 2, a plurality of code objects Code Objects 1 to N are stored in the disk 150A, which is a storage medium of the hard disk drive HDD.

The ROM 120 stores a boot image and a packed RTOS image.

A plurality of code objects CODE OBJECT 1 to N are stored in the disk 150A. The code objects stored in the disk may include not only code objects required for the operation of the disk drive but also code objects related to various functions that can be extended to the disk drive. In particular, code objects for executing the method according to the flowcharts of FIGS. 12-15 are stored on disk 150A. Of course, code objects for executing the method according to the flowcharts of FIGS. 12-15 may be stored in the ROM 120 instead of the disk 150A. In addition, code objects that perform various functions such as an MP3 player function, a navigation function, a video game function, and the like may also be stored in the disk 150A.

The RAM 130 loads an unpacked RTOS image by reading a boot image from the ROM 120 during a booting process. In addition, code objects required for performing a host interface stored in the disk 150A are loaded into the RAM 130. Of course, an area DATA AREA for storing data is also allocated to the RAM 130.

The channel circuit 200 includes circuits necessary for performing signal processing for data read / write, and the servo circuit 210 includes a head disk assembly 100 to perform data read / write operations. The circuits necessary to control) are embedded.

RTOS (Real Time Operating System) 110A is a real-time operating system program, a multi-program operating system using a disk. Depending on the task, multi-processing is performed in real time in the foreground with high priority, and batch processing is performed in the background with low priority. Then, the code object from the disk is loaded and the code object is unloaded to the disk.

RTOS (Real Time Operating System) 110A is a Code Object Management Unit (COMU) 110-1, Code Object Loader (COL, 110-2), Memory Handler (Memory Handler; MH, 110-3), the channel control module (CCM) 110-4 and the servo control module (SCM) 110-5 are managed to execute a task according to the requested command. The RTOS 110A also manages application programs 220.

In detail, the RTOS 110A loads code objects necessary for disk drive control into the RAM 130 during the booting process of the disk drive. Therefore, after executing the booting process, the disk drive may be operated using the code objects loaded in the RAM 130.

The COMU 110-1 stores the positional information where the code objects are recorded, and performs a process of arbitrating the bus. It also stores information about the priority of tasks that are running. It also manages task control block (TCB) information and stack information necessary for performing tasks on code objects.

The COL 110-2 loads the code objects stored in the disk 150A into the RAM 130 using the COMU 110-1, or the code objects stored in the RAM 130 in the disk 150A. Unloading is performed. Accordingly, the COL 110-2 may load the code objects into the RAM 130 for executing the method according to the flowcharts of FIGS. 12 to 15 stored in the disk 150A.

The RTOS 110A may execute the method according to the flowcharts of FIGS. 12 to 15, which will be described below, using the code objects loaded into the RAM 130.

The MH 110-3 performs a process of writing or reading data to the ROM 120 and the RAM 130.

The CCM 110-4 performs channel control necessary to perform signal processing for data read / write, and the SCM 110-5 performs servo control including a head disk assembly to perform data read / write. do.

Next, FIG. 1B is a block diagram of a computer system according to another embodiment of the inventive concept.

In the storage device 1000B of the computer system as illustrated in FIG. 1B, a nonvolatile memory device 180 is added to the storage device 1000A illustrated in FIG. 1A. In FIG. 1B, the storage medium 150 may be implemented as a disk.

The nonvolatile memory device 180 may be implemented as a nonvolatile semiconductor memory device. For example, the nonvolatile memory device 180 may be implemented as a flash memory, a phase change RAM (PRAM), a ferroelectric RAM (FRAM), a magnetic RAM (MRAM), or the like.

The nonvolatile memory device 180 may store some or all of data to be stored in the storage device 1000B. As an example, various information required for controlling the storage device 1000B may be stored in the nonvolatile memory device 180.

In addition, program code and information for executing the method according to the flowcharts of FIGS. 12 to 15 may be stored in the nonvolatile memory device 180. In detail, program codes and information necessary to perform a write operation and a write retry operation may be stored in the nonvolatile memory device 180. In addition, code objects for implementing various functions of the storage device may be stored in the nonvolatile memory device 180.

Duplicate description of the same constituent means already described in the computer system of FIG. 1A will be avoided.

For reference, the software operating system for the hard disk drive including the nonvolatile memory device 180 has a structure in which the nonvolatile memory device 180 is additionally connected to the memory handler 110-3 in FIG. 2. In this case, the memory handler 110-3 performs a process of writing or reading data to the nonvolatile memory device 180.

Next, an electrical circuit configuration of a disk drive 1000A ', which is an example of a storage device, according to an embodiment of the inventive concept illustrated in FIG. 1A is illustrated in FIG. 4A.

As shown in FIG. 4A, the disc drive 1000A ′ according to an embodiment of the inventive concept may include a preamplifier 410, a read / write channel 420, and a processor 430. And a voice coil motor driver 440 (VCM driver), a spindle motor driver 450 (SPM driver), a ROM 460, a RAM 470, and a host interface 480.

The processor 430 may be a digital signal processor (DSP), a microprocessor, a microcontroller, or the like. The processor 430 read / write channel for reading information from or writing information to the disk 12 according to a command received from the host device 2000 via the host interface 480. Control 420.

The processor 430 is coupled to a voice coil motor (VCM) driver 440 that supplies a driving current for driving the voice coil motor 30 (VCM). The processor 430 supplies a control signal to the VCM driver 440 to control the movement of the head 16.

The processor 430 is also coupled to a SPM (Spindle Motor) driver 450 that supplies a drive current for driving the spindle motor 14 (SPM). When power is supplied, the processor 430 supplies a control signal to the SPM driver 450 to rotate the spindle motor 14 at a target speed.

Processor 430 is coupled to ROM 460 and RAM 470, respectively. The ROM 460 stores firmware and control data for controlling the disk drive. Program code and information for executing the method according to the flowcharts of FIGS. 12-15 may be stored in the ROM 460. Of course, program code and information for executing the method according to the flowcharts of FIGS. 12-15 may be stored in the maintenance cylinder region of the disk 12 instead of the ROM 460.

In the RAM 470, program codes stored in the ROM 460 or the disk 12 are loaded in the initialization mode under the control of the processor 430, and are read from the data or the disk 12 received through the host interface 480. The generated data is temporarily stored in the cache buffer area. Of course, the cache buffer area may be allocated to a memory device other than the RAM 470 in the storage device.

The RAM 470 may be implemented with DRAM or SRAM. In addition, the RAM 470 may be designed to be driven by a single data rate (SDR) method or a double data rate (DDR) method.

In addition, the processor 430 may control the disk drive to execute the method according to the flowcharts of FIGS. 12 to 15 using program codes and information stored in the maintenance cylinder area of the ROM 460 or the disk 12. .

Next, FIG. 4B illustrates an electrical circuit configuration of the disk drive 1000B 'which is an example of a storage device according to an embodiment of the inventive concept shown in FIG. 1B.

The disk drive 1000B 'as shown in FIG. 4B has a nonvolatile memory device 490 added to the disk drive 1000A' shown in FIG. 4A. The nonvolatile memory device 490 may store a part of data to be stored in the disk drive 1000B '. As an example, various information required for controlling the disk drive 1000B 'may be stored in the nonvolatile memory device 490.

In addition, program code and information for executing the method according to the flowcharts of FIGS. 12 to 15 may be stored in the nonvolatile memory device 490. In detail, program codes and information used to perform the write operation control method and the write retry operation control method may be stored in the nonvolatile memory device 490. In addition, code objects for implementing various functions of the storage device may be stored in the nonvolatile memory device 490.

The processor 430 is coupled to the ROM 460, the RAM 470, and the nonvolatile memory device 490, respectively. The ROM 460 stores firmware and control data for controlling the disk drive. Program code and information for executing the method according to the flowcharts of FIGS. 12-15 may be stored in the ROM 460. Of course, program code and information for executing the method according to the flowcharts of FIGS. 12-15 may be stored in the maintenance cylinder region of the disk 12 or the nonvolatile memory device 490 instead of the ROM 460.

The RAM 470 may load program codes and information stored in the ROM 460, the disk 12, or the nonvolatile memory device 490 under the control of the processor 430 in an initialization mode.

Duplicate description of the same constituent means already described in the disk drive 1000A 'of FIG. 4A will be avoided.

Next, a data read operation and a data write operation performed after searching for the physical address of the disk corresponding to the logical block address designated by the read command or the write command will be described with reference to FIGS. 4A and 4B.

In the data read mode, the disc drive amplifies in the preamplifier 410 the electrical signal sensed by the head 16 from the disc 12. Then, amplify the signal output from the preamplifier 410 by an automatic gain control circuit (not shown) that automatically varies the gain in accordance with the magnitude of the signal in the read / write channel 420, which is then converted into a digital signal. After conversion to, decoding is performed to detect data. After the processor 430 performs an error correction process using the Reed Solomon code, which is an error correction code, as an example, the data is converted into stream data and transmitted to the host device 2000 through the host interface 500.

In the data write mode, the disk drive receives data from the host device through the host interface 480, adds a symbol for error correction by the Reed Solomon code in the processor 430, and read / write channel 420. After the encoding process is performed so as to suit the recording channel, the recording current is amplified by the preamplifier 410 and recorded on the disc 12 through the head 16.

9 is a block diagram of a write retry operation control apparatus according to an embodiment of the present invention.

As shown in FIG. 9, the write retry operation control apparatus according to an exemplary embodiment of the inventive concept includes a write gate signal generator 910, a write defect detector 920, and a write retry start position determiner. 930, a write control signal generator 940, a multiplexer 950, and an AND gate 960.

9 may be designed to be included in the processor 110 in the computer system of FIGS. 1A and 1B and may also be designed to be included in the storage medium interface 140.

9 may be designed to be included in the read / write channel 420 or the processor 430 in the disk drive illustrated in FIGS. 4A and 4B. Of course, it can also be designed as a unique circuit block.

The write gate signal generator 910 generates a write gate signal for writing data to a sector position of the storage medium corresponding to the address specified by the write command received from the host device. That is, as shown in FIG. 16, except for the section in which the servo gate signal SG is generated from the time when the sector pulse SP indicating the start position of the sector of the storage medium corresponding to the address designated by the write command is generated. And a write gate signal WG having a first logical value (eg, logical HIGH). The read / write channel 420 of the disk drive performs data processing for the write operation in the section in which the write gate signal WG has the first logic value. That is, the encoding process for the data to be written is performed.

The write gate signal generator 910 generates a write gate signal WG having a second logical value (for example, logical LOW) from the time when the write defect is detected during the write operation. Referring to FIG. 17, it can be seen that the logic state of the write gate signal WG is converted to the second logic value as the write defect occurs in the servo section in which the servo gate signal SG_2 is generated. The read / write channel 420 of the disk drive does not perform data processing for the write operation in the section in which the write gate signal WG has the second logic value.

The write defect detector 920 determines whether a write defect is generated using a signal read from the servo information area S shown in FIG. 7A or 7B while performing a write operation. That is, when a defect occurs in any one of the preamble 101, the servo synchronization display signal 102, the gray code 103, and the burst signal 104 read out from the servo information area S, a write defect Is determined to be generated, and a light defect detection signal is generated to signal that a light defect has occurred. As an example, the write defect detector 920 may determine that a write defect is generated when the level of the position error signal generated using the burst signal 104 during the write operation is less than the reference value. If the level of the position error signal is less than the reference value, the track following control cannot be executed normally.

The write retry start position determiner 930 determines the start position of the servo section in which the write defect detection signal is generated as the write retry start position, and outputs a signal indicating this to the write control signal generator 940.

The write control signal generator 940 generates a write control signal for rewriting from the start position of the servo section in which the write defect is generated. As an example, the write control signal generated by the write control signal generator 940 has a second logic value in a section before the servo information region in which the write defect is generated, and the first logic value from the servo information region in which the write defect is generated. Has

The multiplexer 950 has two input terminals IN1 and IN2, one output terminal OUT, and one control terminal CTL. The signal output from the write control signal generator 940 is applied to the first input terminal IN1, and the power Vcc having a logical high state is applied to the second input terminal IN2. The write retry signal WR is applied to the control terminal CTL. The write retry signal WR is generated by the processor 110 or 430 and may be designed to have a first logic value in the write retry operation section and a second logic value in the other section.

In the multiplexer 950, a signal of the first input terminal IN1 is output to the output terminal OUT in a section in which the write retry signal WR has the first logic value, and the write retry signal WR is output to the second. In a section having a logic value, the signal of the second input terminal IN2 is output to the output terminal OUT. The signal output from the output terminal of the multiplexer 950 is called a write start control signal WC.

Accordingly, the write start control signal WC output to the output terminal OUT of the multiplexer 950 in the normal write operation period other than the write retry operation period is illustrated in FIGS. 16 and 17 (d). Maintain a logical high state as shown.

However, in the write retry operation section, the write start control signal WC outputted to the output terminal OUT of the multiplexer 950 is the servo information region SG_2 in which the write defect is generated, as shown in FIG. 18 (d). ) Has a second logical value in the previous section, and has a first logical value from the servo information area SG_2 where the write defect occurred.

Referring to FIG. 18D, in one embodiment of the present invention, the logic state of the write start control signal WC is changed from the second logic value to the first logic value in the servo information area SG_2 in which the write fault occurs. It can be seen that the change.

The AND gate 960 performs a logical multiplication on the write gate control signal WC output from the write gate signal generator 910 and the write start control signal WC output from the output terminal OUT of the multiplexer 950. Output The signal output from the AND gate 960 is applied to the preamplifier 410 of FIG. 4A or 4B as a write enable signal WE.

In the normal write operation period, the write enable signal WE output from the AND gate 960 is as shown in FIG. 16E, and the write enable output from the AND gate 960 is generated in a state where a write defect is generated. The signal WE is as shown in Fig. 17E. In addition, the write enable signal WE output from the AND gate 960 in the write retry operation period is as shown in FIG. 18E.

The preamplifier 410 supplies or blocks a write current to the light head using the light enable signal WE generated as described above.

10 and 11 illustrate circuit configurations of the preamplifier 410 of the disk drive according to the embodiment of the present invention.

As shown in FIG. 10, the preamplifier 410 according to an embodiment of the present invention includes a light amplifier A1 and a switch SW1.

The light signal is input to the input terminal of the write amplifier A1. The write signal is a signal encoded for the write operation in a section in which the write gate signal WG has the first logical value in the read / write channel 420 of the disc drive.

The first terminal of the switch SW1 is connected to the power supply terminal Vcc, the second terminal of the switch SW1 is connected to the power input terminal of the light amplifier A1, and the third terminal of the switch SW1 is connected to the third terminal of the switch SW1. The write enable signal WE described in FIG. 9 is applied.

According to the logic state of the write enable signal WE applied to the third terminal of the switch SW1, the first terminal and the second terminal of the switch SW1 are electrically connected or disconnected. As an example, when the logic state of the write enable signal WE has a first logic value, the first terminal and the second terminal of the switch SW1 are electrically connected. When the logic state of the write enable signal WE has the second logic value, the first terminal and the second terminal of the switch SW1 are electrically disconnected.

Accordingly, the power supply Vcc is supplied to the power supply input terminal of the write amplifier A1 in the section in which the logic state of the write enable signal WE has the first logic value. The power source Vcc is not supplied to the power input terminal of the write amplifier A1 in a section in which the logic state of the write enable signal WE has the second logic value.

For this reason, the light amplifier A1 amplifies the light signal and outputs the amplified light current to the light head only in a section in which the logic state of the write enable signal WE has the first logic value. This means that data is written to the disk 12 only in a section in which the logic state of the write enable signal WE has the first logical value.

As illustrated in FIG. 11, the preamplifier 410 according to another embodiment of the present invention includes a light amplifier A1 and a switch SW1.

The power supply terminal Vcc is connected to the power input terminal of the light amplifier A1. Accordingly, the write amplifier A1 amplifies the input light signal, and outputs the amplified light current through the output terminal.

The first terminal of the switch SW1 is connected to the output terminal of the light amplifier A1, the second terminal of the switch SW1 is connected to the light head, and the third terminal of the switch SW1 is described with reference to FIG. The write enable signal WE is applied.

Accordingly, the signal of the output terminal of the write amplifier A1 is transmitted to the write head in a section in which the logic state of the write enable signal WE has the first logical value. However, the signal of the output terminal of the write amplifier A1 is not transmitted to the write head in the section in which the logic state of the write enable signal WE has the second logic value.

For this reason, the write current amplified by the light amplifier A1 is applied to the light head only in a section in which the logic state of the write enable signal WE has the first logic value. This means that data is written to the disk 12 only in a section in which the logic state of the write enable signal WE has the first logical value.

Referring to FIG. 16, in the normal write operation state, the write enable signal WE as 16 (e) is generated, so that data is normally written in a section having a first logical state (logical high). Accordingly, data for sector S1 is written over a plurality of servo sections. That is, data for one sector is divided and written into subsectors S1_sub1, S1_sub2, and S1_sub3 constituting sector S1.

Referring to FIG. 17, when a write defect occurs in the servo section in which the servo gate signal SG_2 is generated, the write enable signal WE as shown in 17 (e) is generated. Therefore, after the write defect is generated, the write enable signal WE goes into the second logical state (logical low) and the data write operation is stopped. Accordingly, the write operation is stopped in the servo section in which the servo gate signal SG_2 is generated. That is, among the sub-sectors S1_sub1, S1_sub2, and S1_sub3 constituting the sector S1, data is normally written in the S1_sub1 and S1_sub2 sections, but the write operation is stopped while the data writing is not completed in the S1_sub3 section.

Referring to FIG. 18, when a write defect is generated in the servo section in which the servo gate signal SG_2 is generated, the write enable signal WE as shown in 18 (e) is generated. Accordingly, the write operation starts from the S1_sub3 section in which the write enable signal WE has the first logical state (logical high). That is, since data is normally written in the S1_sub1 and S1_sub2 sections among the subsectors S1_sub1, S1_sub2, and S1_sub3 constituting the sector S1, data writing starts from S1_sub3 where a write defect has occurred.

In the write retry mode, as shown in FIG. 18C, the write gate signal WG is converted to the first logical value from the time when the sector pulse SP is generated, and thus the read / write channel 420 of the disk drive is performed. ) Performs data processing for a write operation normally from subsector S1_sub1.

However, as shown in FIG. 18E, since the logic state is switched to the first logic value from the S1_sub3 section where the write defect is generated, the pre-amplifier 410 writes from the S1_sub3 section. Output the current. That is, in the write retry mode, data is written from the S1_sub3 section of the disk 12 on which the write defect has occurred.

Next, one embodiment of a method for controlling a write retry operation according to the spirit of the present invention executed by the firmware of the processor 110 shown in FIGS. 1A and 1B or the processor 430 shown in FIGS. 4A and 4B. An example will be described with reference to FIG. 12. For convenience of description, the description will be limited to that executed by the processor 430 of the disk drive shown in FIGS. 4A and 4B. Of course, the processor 110 may also be executed by the processor 110 illustrated in FIGS. 1A and 1B.

The processor 430 determines a write start position to be rewritten before the write defect is detected and the write retry mode is performed (S101). The processor 430 determines the write start position such that the written region is write skipped in the sector to be rewritten. Specifically, the start position of a subsector in which a write defect occurs among the plurality of subsectors included in the sector to be rewritten may be determined as the write start position.

Next, the write operation is performed from the write start position determined in step 101 (S101) (S102). That is, the processor 430 controls the disk drive to perform the write operation according to the write retry mode from the start position of the sub sector in which the write defect is generated.

13 is a detailed flowchart of the step 102 of performing a write retry operation. Referring to Fig. 13, the operation performed in step 102 (S102) will be described in more detail.

The processor 430 generates a write control signal for the write retry based on the write start position determined in step 101 (S101) (S201). The write control signal may include a write gate signal WG, a write start control signal WC, and a write enable signal WE.

In detail, the write start control signal WC generated on the basis of the write start position determined in step 101 (S101) and the write gate signal generated on the basis of the sector pulse SP representing the start of the sector to be rewritten. The write enable signal WE may be generated by performing a logical multiplication on the WG. As an example, referring to FIG. 18, when a write defect is generated in the servo section in which the servo gate signal SG_2 is generated, the write start control signal WC may be generated as shown in FIG. 18 (d). The write gate signal WG may be generated as shown in FIG. 18C. Accordingly, the write enable signal WE may be generated as shown in FIG. 18 (e).

The storage device such as a disk drive performs a write operation according to the write control signal (S202). In detail, the write enable signal WE outputs the write current from the preamplifier 410 of the disc drive to the head 16 during the first logical value period, thereby writing data to the disc 12. Referring to FIG. 18E, it can be seen that the write operation according to the write retry mode is started from S1_sub3 when a defect is generated in the previous write operation according to the write enable signal WE.

Next, a write operation control method in the disk drive will be described with reference to the flowchart of FIG. 14.

The processor 430 determines whether a write command is received by the disk drive through the host interface 480 (S301).

When a write command is received as a result of the determination in step 301 (S301), the processor 430 seeks a target track in which the physical address of the disk 12 corresponding to the logical address included in the write command is located. It performs (S302). That is, the processor 430 performs voice coil motor 30 drive control for moving the head 16 to the target track of the disk 12.

After moving the head 16 to the target track position, the processor 430 controls the disk drive to perform write operations and write defect checks. That is, whether or not a write defect is generated by using a signal read from the servo information area S of the disk 12 while performing a write operation in accordance with the timing of the write gate signal WG and the write enable signal WE. Determine. That is, when a defect occurs in any one of the preamble 101, the servo synchronization display signal 102, the gray code 103, and the burst signal 104 read out from the servo information area S, a write defect Can be determined to occur.

The processor 430 determines whether the write operation is completed while performing the write operation and the write defect inspection (S304).

The processor 430 determines whether a write defect is detected in a state in which the write operation is not completed (S305). As an example, it may be determined that a write defect occurs when the level of the position error signal generated using the burst signal 104 is less than the reference value.

When a write defect is detected as a result of the determination in step 305 (S305), the processor 430 controls the disk drive to stop the write operation (S306). That is, when a write defect is detected, the processor 430 stops the write operation by changing the logic state of the write gate signal WG from the first logic value to the second logic value.

Then, the processor 430 controls the disk drive to perform the write retry operation (S307). A detailed process of performing the write retry operation will be described with reference to the flowchart of FIG. 15.

First, the processor 430 determines whether a write retry is generated (S401).

When a write retry occurs, the processor 430 changes a write related parameter value of the disk drive (S402). As an example, the write related parameter may include a write current, a coefficient of filters used in the disk drive, an off track amount, and the like.

After completing step 402 (S402), the processor 430 determines the write retry start position (S403). The processor 430 may determine the start position of the servo section in which the write defect occurs, as the write retry start position.

Next, the processor 430 generates a control signal for writing (S404). The write control signal may include a write gate signal WG, a write start control signal WC, and a write enable signal WE. Since the operation of generating the write gate signal WG, the write start control signal WC, and the write enable signal WE has been described above with reference to FIG. 9, a redundant description thereof will be omitted.

Next, the disk drive performs a write operation according to the write control signal (S405). The write enable signal WE outputs a write current from the preamplifier 410 of the disc drive to the head 16 during the interval of the first logic value, thereby writing data to the disc 12.

As described above, when a light defect is generated during a write operation to perform a write retry operation, data writing may be partially performed from the position where the write defect is generated.

The invention can be practiced as a method, apparatus, system, or the like. When implemented in software, the constituent means of the present invention are code segments that necessarily perform the necessary work. The program or code segments may be stored in a processor readable medium. Examples of processor-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memory, erasable ROM (EROM), floppy disks, optical disks, hard disks, and the like.

Specific embodiments shown and described in the accompanying drawings are only to be understood as examples of the present invention, and not to limit the scope of the present invention, even in the scope of the technical spirit described in the present invention in the technical field to which the present invention belongs As various other changes may occur, it is obvious that the invention is not limited to the specific constructions and arrangements shown or described.

1000A, 1000B; Storage device, 2000; Host device, 3000; Connector 110; Processor, 120; ROM, 130; RAM, 140; A storage medium interface, 150; Storage medium, 160; Host interface 170; Bus, 410; Preamplifier, 420; Lead / light channel, 430; Processor 440; Voice coil motor driver 450; Spindle motor drive 460; ROM, 470; RAM, 480; Host interface, 490; Non-volatile memory device, 910; A write gate signal generator 920; A light defect detector 930; A write retry start position determiner 940; A write control signal generator 950; Multiplexer, 960; Logical gate

Claims

Determining a write start position such that a written area is skipped in the sector to be rewritten; And
And performing a write operation from the determined write start position.

The method of claim 1, wherein the data size of the sector is set to be larger than a storage capacity of one servo section.

The method of claim 1, wherein the sector comprises a plurality of sub-sectors, and a start position of one sub-sector among the plurality of sub-sectors is determined as a write start position.

The method of claim 3, wherein the sector is determined by a sector pulse, and the sector is divided into sub-sectors based on a servo gate signal.

The method of claim 1, wherein a start position of a subsector in which a write defect is generated is determined as a write start position among a plurality of subsectors included in the sector to be rewritten.

The method of claim 1, wherein performing the write operation
Generating a write enable signal by performing a logical multiplication on a write start control signal generated based on the determined write start position and a write gate signal generated on the basis of a sector pulse indicating the start of a sector to be rewritten; And
And performing a write operation according to the write enable signal.

Storage media;
A storage medium interface for accessing the storage medium to write or read data; And
And a processor configured to determine a write start position such that a written area is skipped in the sector to be rewritten, and generate a write control signal for performing a write operation from the determined write start position, wherein the storage medium interface includes: And writing data to the storage medium in accordance with the write control signal.

8. The processor of claim 7, wherein the processor performs a logical multiplication on the write start control signal generated on the basis of the determined write start position and the write gate signal generated on the basis of a sector pulse indicating the start of a sector to be rewritten. And generate an enable signal.

The storage device of claim 8, wherein the storage medium interface generates a write current for writing data to the storage medium according to the write enable signal.

8. The storage medium of claim 7, wherein the storage medium interface is
A read / write operation for generating a write enable signal by performing a logical multiplication on a write start control signal generated based on the determined write start position and a write gate signal generated based on a sector pulse representing a start of a sector to be rewritten channel; And
And a preamplifier configured to generate a light current according to the light enable signal and apply the light current to the light head.