KR20130039874A - Wafer processing apparatus - Google Patents

Wafer processing apparatus Download PDF

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Publication number
KR20130039874A
KR20130039874A KR1020110104515A KR20110104515A KR20130039874A KR 20130039874 A KR20130039874 A KR 20130039874A KR 1020110104515 A KR1020110104515 A KR 1020110104515A KR 20110104515 A KR20110104515 A KR 20110104515A KR 20130039874 A KR20130039874 A KR 20130039874A
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KR
South Korea
Prior art keywords
wafer
module
inline
facility
end module
Prior art date
Application number
KR1020110104515A
Other languages
Korean (ko)
Inventor
김진환
임성민
Original Assignee
세메스 주식회사
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Publication date
Application filed by 세메스 주식회사 filed Critical 세메스 주식회사
Priority to KR1020110104515A priority Critical patent/KR20130039874A/en
Publication of KR20130039874A publication Critical patent/KR20130039874A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67173—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers in-line arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
    • H01L21/67769—Storage means

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE: A wafer processing apparatus is provided to transfer a wafer between in-line apparatuses through a buffer module, to reduce the time for transferring the wafer, and to improve wafer production efficiency. CONSTITUTION: An in-line apparatus(200-500) includes an in-line process module(230,330,430,530) and a front end module(220,320,420,520). The in-line process module includes a process module(251-254,351-354,451-454) for a wafer and a transport module(240,340,540,640). The transport module transfers the wafer from the front end module to the process module. The front end module transfers the wafer from the in-line process module to the in-line process module or receives the wafer from the in-line process module. A buffer module(260,360,460) is arranged between the in-line apparatuses. The buffer module receives the wafer from the front end module and stores the wafer between the in-line apparatuses.

Description

Wafer processing apparatus {WAFER PROCESSING APPARATUS}

The present invention relates to a wafer processing apparatus, and more particularly, to a wafer processing apparatus for transferring a wafer.

An inline system for processing a wafer is disposed between a process module for performing a process on a wafer, a loading / unloading portion for loading or unloading the wafer, and between the loading / unloading portion and the process module to load the wafer. And an Equipment Front End Module (EFEM) that moves between the loading / unloading unit and the process module.

The wafer processed in one inline system is seated in the loading / unloading section and transferred to another inline system where the next process is performed by an overhead hoist transport (OHT).

However, when the wafer is transferred between the inline systems through the overhead hoist transport, there is a problem in that the production efficiency of the wafer is lowered due to the movement time of the overhead hoist transport.

In addition, since the wafer is exposed to the outside during the transfer of the wafer between the inline systems through the overhead hoist transport, the wafer is contaminated by particles, thereby reducing the yield of the wafer. .

Accordingly, the technical problem of the present invention was conceived in this respect, and an object of the present invention is to provide a wafer processing apparatus for improving the production efficiency of a wafer and increasing the yield of the wafer.

A wafer processing apparatus according to an embodiment for realizing the above object of the present invention includes a plurality of inline facilities and a buffer module. The inline installations each include an inline processing unit for processing a wafer and a facility front end module for transferring the wafer to or receiving the wafer from the inline processing unit. The buffer module is disposed between the inline facilities and receives the wafer from the facility front end module to store the wafer between the inline facilities.

In one embodiment of the present invention, the in-line process unit may include a plurality of process modules for processing the wafer, and a transfer module for transferring the wafer from the facility front end module to the process modules.

According to such a wafer processing apparatus, since the wafer is transferred between the inline facilities through the buffer module, the wafer transfer time can be reduced to improve the production efficiency of the wafer.

In addition, the wafer can be prevented from being contaminated by external particles, thereby increasing the yield of the wafer.

1 is a block diagram illustrating a wafer processing apparatus according to an embodiment of the present invention.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing. The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "consist of" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described on the specification, but one or more other features. It is to be understood that the present disclosure does not exclude the existence or the possibility of addition of numbers, steps, operations, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a block diagram illustrating a wafer processing apparatus according to an embodiment of the present invention.

Referring to FIG. 1, the wafer processing apparatus 100 may include a first inline facility 200, a second inline facility 300, a third inline facility 400, a fourth inline facility 500, and a first buffer module. 260, a second buffer module 360, and a third buffer module 460.

In the present embodiment, the wafer processing apparatus 100 has been described as including four inline facilities, but the present invention is not limited thereto, and the wafer processing apparatus 100 may include N inline facilities (N is a natural number). .

The first inline facility 200 includes a first loading unit 210, a first equipment front end module 220 (EFEM), and a first inline process unit 230.

The first loading unit 210 loads or unloads a wafer.

The first facility front end module 220 is installed between the first loading unit 210 and the first inline processing unit 230, and the first inline processing unit 230 from the first loading unit 210. Transfer the wafer. In addition, the first facility front end module 220 may receive the wafer from the first in-line process unit 230. In addition, the first facility front end module 220 may transfer the wafer to the first buffer module 260. The first facility front end module 220 may include a transfer robot for transferring the wafer. In addition, the first facility front end module 220 may include a decontamination device such as a fan filter unit (FFU) to prevent the wafer from being contaminated by particles. .

The first inline process unit 230 includes a transfer module 240 and a first, process module 251, a second process module 252, a third process module 253, and a fourth process module 254. do. In the present exemplary embodiment, the first in-line process unit 230 has been described as including four process modules. However, the present invention is not limited thereto, and the first in-line process unit 230 includes M process modules (M is a natural number). can do.

The first transfer module 240 receives the wafer from the first facility front end module 220 to the first, second, third and fourth process modules 251, 252, 253, 254. Transfer. The first transfer module 240 also transfers the wafer from the first, second, third and fourth process modules 251, 252, 253, 254 to the first facility front end module 220. Transfer. The first transfer module 240 may include a transfer robot for transferring the wafer.

The first, second, third and fourth process modules 251, 252, 253, and 254 may be disposed at both sides of the first transfer module 240 to transfer the wafer from the first transfer module 240. Receive and process the wafer. Each of the first, second, third, and fourth process modules 251, 252, 253, and 254 may perform the same process on the wafer. For example, the first, second, third and fourth process modules may perform an etching process. In contrast, each of the first, second, third and fourth process modules 251, 252, 253, and 254 may perform different processes. For example, the first, second, third, and fourth process modules 251, 252, 253, and 254 may each perform a deposition process, a baking process, an etching process, and an ashing process.

The first buffer module 260 is disposed between the first inline facility 200 and the second inline facility 300, from the first inline facility 200 and the second inline facility 300. The wafer is received and stored. For example, the first buffer module 260 may receive the wafer processed by the first inline process unit 230 from the first facility front end module 220.

The second inline facility 300 includes a second loading unit 310, a second facility front end module 320, and a second inline process unit 330, wherein the second inline process unit 330 is formed of a second in-line unit 330. And a second transfer module 340, a fifth process module 351, a sixth process module 352, a seventh process module 353, and an eighth process module 354.

The second inline facility 300 is connected to the first inline facility 200 through the first buffer module 260. Specifically, the first facility front end module 220 of the first inline facility 200 and the second facility front end module 320 of the second inline facility 300 are the first buffer module 260. Are connected to opposite sides of each other). Thus, the second facility front end module 320 of the second inline facility 300 is connected to the first buffer module 260 from the first facility front end module 220 of the first inline facility 200. It is possible to receive the wafer through.

The configuration and function of the second loading unit 310, the second facility front end module 320, and the second inline processing unit 330 of the second inline facility 300 are the first inline facility 200. ) Is substantially the same as the configuration and function of the first loading unit 210, the first facility front end module 220 and the first in-line process unit 230, detailed description thereof will be omitted.

The second buffer module 360 is disposed between the second inline facility 300 and the third inline facility 400, from the second inline facility 300 and the third inline facility 400. The wafer is received and stored. For example, the second buffer module 360 may receive the wafer processed by the second inline process unit 330 from the second facility front end module 320.

The third inline facility 400 includes a third loading unit 410, a third facility front end module 420, and a third inline process unit 430. And a third transfer module 440, a ninth process module 451, a tenth process module 452, an eleventh process module 453, and a twelfth process module 454.

The third inline facility 400 is connected to the second inline facility 300 through the second buffer module 360. Specifically, the second facility front end module 320 of the second inline facility 300 and the third facility front end module 420 of the third inline facility 400 are the second buffer module 260. Are connected to opposite sides of each other). Thus, the third facility front end module 420 of the third inline facility 300 is the second buffer module 360 from the second facility front end module 320 of the second inline facility 300. It is possible to receive the wafer through.

The configuration and function of the third loading unit 410, the third facility front end module 420, and the third inline processing unit 430 of the third inline facility 400 are the first inline facility 200. ) Is substantially the same as the configuration and function of the first loading unit 210, the first facility front end module 220 and the first in-line process unit 230, detailed description thereof will be omitted.

The third buffer module 460 is disposed between the third inline facility 400 and the fourth inline facility 500, and from the third inline facility 400 and the fourth inline facility 500. The wafer is received and stored. For example, the third buffer module 460 may receive and store the wafer processed by the third inline process unit 430 from the third facility front end module 420.

The fourth inline facility 500 includes a fourth loading unit 510, a fourth facility front end module 520, and a fourth inline process unit 530. And a fourth transfer module 540, a thirteenth process module 551, a fourteenth process module 552, a fifteenth process module 553, and a sixteenth process module 554.

The fourth inline facility 500 is connected to the third inline facility 400 through the third buffer module 460. Specifically, the third facility front end module 420 of the third inline facility 400 and the fourth facility front end module 520 of the fourth inline facility 500 are the third buffer module 360. Are connected to opposite sides of each other). Thus, the fourth facility front end module 520 of the fourth inline facility 500 is the third buffer module 460 from the third facility front end module 420 of the third inline facility 400. It is possible to receive the wafer through.

The configuration and function of the fourth loading unit 510, the fourth facility front end module 520, and the fourth inline processing unit 530 of the fourth inline facility 500 may be the first inline facility 200. ) Is substantially the same as the configuration and function of the first loading unit 210, the first facility front end module 220 and the first in-line process unit 230, detailed description thereof will be omitted.

The first, second, third and fourth inline facilities 200, 300, 400, 500 may be arranged in opposite directions to adjacent inline facilities. Specifically, the first transfer module 240 of the first and third inline facilities (200, 400) of the first, second, third and fourth inline facilities (200, 300, 400, 500) ) And the third transfer module 440 extend in the first direction D1, and the second transfer module 340 and the fourth transfer module of the second and fourth inline facilities 300 and 500. 540 may extend in a second direction D2 opposite to the first direction D1. Therefore, even if the shape and size of the inline processing units are different, it is possible to prevent collisions and interference between adjacent inline processing units.

According to this embodiment, the first, second, third and fourth inline facilities 200, 300, 400, 500 via the first, second and third buffer modules 260, 360, 460. Since the wafer is transferred between the wafers, the transfer time of the wafer can be reduced, and the wafer can be prevented from being contaminated by external particles.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims. You will understand.

Since the wafer processing apparatus according to the present invention transfers wafers between inline facilities through a buffer module, it is possible to reduce wafer transfer time and improve wafer production efficiency.

In addition, the wafer can be prevented from being contaminated by external particles, thereby increasing the yield of the wafer.

100: wafer processing apparatus
200, 300, 400, 500: inline installation
210, 310, 410, 510: loading part
220, 320, 420, 520: Facility front end module
230, 330, 430, 530: Inline Process
240, 340, 540, 640: transfer module
251, 252, 253, 254, 351, 352, 353, 354, 451, 452, 453, 454, 551, 552, 553, 554: process module

Claims (2)

A plurality of inline installations each including an inline processing unit for processing a wafer and a facility front end module for transferring the wafer to or receiving the wafer from the inline processing unit; And
A buffer module disposed between the inline facilities, the buffer module receiving the wafer from the facility front end module and storing the wafer between the inline facilities. The method of claim 1, wherein the in-line process unit,
A plurality of process modules for processing the wafer; And
And a transfer module for transferring the wafer from the facility front end module to the process modules.
KR1020110104515A 2011-10-13 2011-10-13 Wafer processing apparatus KR20130039874A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110104515A KR20130039874A (en) 2011-10-13 2011-10-13 Wafer processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110104515A KR20130039874A (en) 2011-10-13 2011-10-13 Wafer processing apparatus

Publications (1)

Publication Number Publication Date
KR20130039874A true KR20130039874A (en) 2013-04-23

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KR1020110104515A KR20130039874A (en) 2011-10-13 2011-10-13 Wafer processing apparatus

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