KR20130027215A - Thin film transistor and preparing methode of the same - Google Patents

Thin film transistor and preparing methode of the same Download PDF

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KR20130027215A
KR20130027215A KR1020110090670A KR20110090670A KR20130027215A KR 20130027215 A KR20130027215 A KR 20130027215A KR 1020110090670 A KR1020110090670 A KR 1020110090670A KR 20110090670 A KR20110090670 A KR 20110090670A KR 20130027215 A KR20130027215 A KR 20130027215A
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self
thin film
substrate
assembled monolayer
film transistor
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KR1020110090670A
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Korean (ko)
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홍병희
김경은
박재성
김영수
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그래핀스퀘어 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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Abstract

The present application relates to a thin film transistor through surface modification of graphene using a self-assembled monolayer and a method of manufacturing the same.

Description

Thin film transistor and its manufacturing method {THIN FILM TRANSISTOR AND PREPARING METHODE OF THE SAME}

The present application relates to a thin film transistor using a channel region including a self-assembled monolayer and a graphene layer, and a method of manufacturing the same.

Graphene has received considerable attention as a potential alternative for use in next-generation semiconductor technology. Since the discovery of graphene, graphene-based electronic devices have been used for the use of optical contrast between monolayer graphene and SiO 2, and for the construction of devices with metal-oxide-semiconductor (MOS) structures. It was made on a SiO 2 / Si substrate because of its ease of manufacture. However, the performance of graphene field effect transistors (FETs) formed on SiO 2 substrates can be improved by charged impurity scattering, exogenous scattering by surface phonons, resonance scattering from atomic scale defects, and corrugation by residual adsorbents. Or limited by doping. To overcome this performance limitation, a dielectric with a high dielectric constant (k) has been used. Dielectric shielding induced by high-k media reduces long-range coulomb scattering, leading to improved electrical properties. However, high-k dielectrics do not always improve field effects because the unique interaction between graphene and the dielectric can dominate the charge transfer. Another approach involved the use of novel insulating layers (hexagonal boron nitride) that include dangling bonds and low density of charge traps.

On the other hand, a buffer layer can be inserted between the graphene and the gate dielectric to modify the surface properties of SiO 2 . This approach provides an alternative method for reducing charged impurity scattering or adsorbate-limited doping.

However, the mechanism by which the electrical properties of graphene FETs are affected is not clear, and a systematic study of the effect of the buffer layer on the performance of graphene FETs is needed. Previous experiments mainly tested mechanically exfoliated graphene flakes. Since the exfoliation process depends on the surface properties of the substrate, large sample-to-sample changes are expected from this source of graphene. Because of this, the chemical vapor deposition (CVD) method by Colombo, RS Ruoff, Science 2009, 324, 1312 recently published by Nature 2009, 457, 706 and KS Kim et al. It enabled the synthesis of uniform high quality graphene. The usefulness of CVD graphene is used in the systematic study of the buffer layer of graphene FETs.

The present invention relates to a thin film transistor using a channel region including a self-assembled monolayer and a graphene layer, and a method for manufacturing the same, wherein the device is improved by modifying the surface of graphene by the self-assembled monolayer to improve electrical properties of graphene. SUMMARY A thin film transistor having characteristics and a method of manufacturing the same are provided.

However, the problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

A first aspect of the present application, the substrate; A source electrode and a drain electrode formed on the substrate; And a channel region electrically connected between the source electrode and the drain electrode, wherein the channel region comprises a Self Assembled Monolyers (SAMs) and a graphene layer formed on the Self Assembled Monolayer. It can provide a thin film transistor.

According to one embodiment of the present application, the self-assembled monolayer may be hydrophobic, but is not limited thereto.

According to one embodiment of the present application, the self-assembled monolayer may be formed using a compound for forming a self-assembled monolayer including an alkyl group, but is not limited thereto.

According to the exemplary embodiment of the present application, the alkyl group included in the compound for forming the self-assembled monolayer may have about 1 to about 30 carbon atoms, but is not limited thereto. For example, the alkyl group may have a carbon number of about 1 to about 30, about 1 to about 25, about 1 to about 20, about 5 to about 30, or about 5 to about 25, or about 5 to about 20 However, it is not limited thereto.

According to the exemplary embodiment of the present application, the compound for forming the self-assembled monolayer may be an alkylsilane-based compound, but is not limited thereto. For example, the alkylsilane-based compound may include an alkyltrichlorosilane-based compound, but is not limited thereto.

According to one embodiment of the present invention, the compound for forming the self-assembled monolayer is octyltrichlorosilane (OCT), hexamethyldisilazane (HMDS), octadecyltrichlorosilane (Octadecyltrichlorosilane; ODTS), (3 -Aminopropyl) trimethoxysilane [(3-Aminopropyl) trimethoxysilane; APS], Perfluorodecyltrichlorosilane (PFS), Mercaptopropyltrimethoxysilane (MPTMS), Octadecyltrimethoxysilane (OTMS), (heptadecafluoro-1,1 , 2,2-tetrahydrodecyl) trichlorosilane [(Heptadecafluoro-1,1,2,2-tetrahydrodecyl) trichlorosilane; FDTS], perfluorodecyltrichlorosilane (1H, 1H, 2H, 2H-perfluorodecyltrichlorosilane; FOTS), dichlorodimethylsilane (DDMS) and combinations thereof, but may be selected from the group consisting of It is not limited to this.

According to the exemplary embodiment of the present application, the source electrode and the drain electrode are Au, Al, Ag, Be, Bi, Co, Cu, Cr, Hf, In, Mn, Mo, Mg, Ni, Nb, Pb, Pd, It may be selected from the group consisting of Pt, Rh, Re, Ru, Sb, Ta, Te, Ti, V, W, Zr, Zn, and combinations thereof, but is not limited thereto.

According to one embodiment of the present application, the substrate may be a metal oxide substrate, a semiconductor substrate, a glass substrate or a plastic substrate, but is not limited thereto.

According to the exemplary embodiment of the present application, the graphene layer may be formed by transferring graphene prepared by chemical vapor deposition on the hydrophobic self-assembled monolayer, but is not limited thereto.

A second aspect of the present application forms a self-assembled monolayer on the substrate; Forming a channel region by forming a graphene layer on the self-assembled monolayer; And forming a source electrode and a drain electrode electrically connected to both sides of the channel region, respectively.

According to one embodiment of the present application, the self-assembled monolayer may be hydrophobic, but is not limited thereto.

According to one embodiment of the present application, the self-assembled monolayer may be formed using a compound for forming a self-assembled monolayer including an alkyl group, but is not limited thereto.

According to the exemplary embodiment of the present application, the alkyl group included in the compound for forming the self-assembled monolayer may have about 1 to about 30 carbon atoms, but is not limited thereto. For example, the alkyl group may have a carbon number of about 1 to about 30, about 1 to about 25, about 1 to about 20, about 5 to about 30, or about 5 to about 25, or about 5 to about 20 However, it is not limited thereto.

According to the exemplary embodiment of the present application, the compound for forming the self-assembled monolayer may be an alkylsilane-based compound, but is not limited thereto. For example, the alkylsilane-based compound may include an alkyltrichlorosilane-based compound, but is not limited thereto.

According to one embodiment of the present application, the self-assembled monolayer is octyltrichlorosilane (OCT), hexamethyldisilazane (HMDS), octadecyltrichlorosilane (Octadecyltrichlorosilane (ODTS), (3-aminopropyl ) Trimethoxysilane [(3-Aminopropyl) trimethoxysilane; APS], Perfluorodecyltrichlorosilane (PFS), Mercaptopropyltrimethoxysilane (MPTMS), Octadecyltrimethoxysilane (OTMS), (heptadecafluoro-1,1 , 2,2-tetrahydrodecyl) trichlorosilane [(Heptadecafluoro-1,1,2,2-tetrahydrodecyl) trichlorosilane; FDTS], perfluorodecyltrichlorosilane (1H, 1H, 2H, 2H-perfluorodecyltrichlorosilane; FOTS), dichlorodimethylsilane (DDMS) and combinations thereof, but may be selected from the group consisting of It is not limited to this.

According to the exemplary embodiment of the present application, the source electrode and the drain electrode are Au, Al, Ag, Be, Bi, Co, Cu, Cr, Hf, In, Mn, Mo, Mg, Ni, Nb, Pb, Pd, It may be selected from the group consisting of Pt, Rh, Re, Ru, Sb, Ta, Te, Ti, V, W, Zr, Zn, and combinations thereof, but is not limited thereto.

According to one embodiment of the present application, the substrate may be a metal oxide substrate, a semiconductor substrate, a glass substrate or a plastic substrate, but is not limited thereto.

According to the exemplary embodiment of the present application, the graphene layer may be formed by transferring graphene prepared by chemical vapor deposition on the hydrophobic self-assembled monolayer, but is not limited thereto.

According to an embodiment of the present disclosure, forming the source electrode and the drain electrode may include depositing the source electrode and the drain electrode on the substrate, each of which is electrically connected to both sides on the channel region using a shadow mask. It may be included, but is not limited thereto.

By the present application, it is possible to improve the electrical properties of the graphene layer by modifying the surface of the graphene layer using a self-assembled monolayer. Specifically, the electron mobility of the graphene layer is reduced by forming a hydrophobic self-assembled molecule layer on the substrate and a graphene layer on the hydrophobic self-assembled molecule layer, thereby reducing the p-doping effect of the graphene layer caused by the substrate such as the SiO 2 substrate. Can be increased. Accordingly, the electrical characteristics of the device may be improved by manufacturing graphene FETs using a channel layer containing a surface-modified graphene layer using the self-assembled monolayer. In addition, the graphene layer surface-modified using the self-assembled monolayer may be applied to various semiconductor devices. A device such as a thin film transistor using a surface-modified graphene layer using the self-assembled monolayer may be used to control semiconductor properties and to be applied as a high-sensitivity sensor. It can be used as an organic solar cell due to its small advantage.

1A to 1C are schematic diagrams illustrating a manufacturing process of a thin film transistor including a graphene channel layer modified using a self-assembled monolayer according to one embodiment of the present application.
FIG. 2 shows, in one embodiment of the present application, (a) and (b) XPS spectra based on SiO 2 modified by various different SAMs, (c) FT-IR spectra of SAMs with different alkyl chain lengths, and (d) a schematic diagram showing the chemical structure of the HMDS with an organosilane of the above SiO 2.
Figure 3, in one embodiment of the present application, comparing the intensity ratio of (a) Raman spectrum and (b) 2D / G of monolayer graphene on a SiO 2 / Si substrate modified by various SAMs, 2D band width, various (C) UV photon emission spectrum and (d) graphene work function comparison graph of a graphene on a SiO 2 / Si substrate modified with SAMs.
Figure 4, in one embodiment of the present application, (a) graphene and SiO 2 Schematic of graphene FETs using SAMs as buffer layer between; Graph showing (b) conductivity according to V G , (c) dilock point voltage, (d) field effect mobility of electrons and holes of graphene FETs on various SAMs modified SiO 2 / Si substrates, (e) A graph showing conductivity according to charge density and (f) a graph showing conductivity according to gate voltage.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. It should be understood, however, that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the same reference numbers are used throughout the specification to refer to the same or like parts.

Throughout this specification, when a part is referred to as being "connected" to another part, it is not limited to a case where it is "directly connected" but also includes the case where it is "electrically connected" do.

Throughout this specification, when a member is " on " another member, it includes not only when the member is in contact with the other member, but also when there is another member between the two members.

Throughout this specification, when an element is referred to as "including " an element, it is understood that the element may include other elements as well, without departing from the other elements unless specifically stated otherwise. The terms "about "," substantially ", etc. used to the extent that they are used throughout the specification are intended to be taken to mean the approximation of the manufacturing and material tolerances inherent in the stated sense, Accurate or absolute numbers are used to help prevent unauthorized exploitation by unauthorized intruders of the referenced disclosure. As used throughout this specification, the term "step to" or "step of" does not mean "step for."

Throughout this specification, the term “combination of these” included in the expression of the makushi form means one or more mixtures or combinations selected from the group consisting of the constituents described in the expression of the makushi form, wherein the constituents It means to include one or more selected from the group consisting of.

Throughout this specification, "self-assembled monolayers" (SAMs) refer to monolayers of molecules in which molecules containing surface-active functional groups spontaneously adsorb to the surface of a specific substrate (metal or metal oxide, etc.) to form chemical bonds. As a single molecule, it has the property to control and modify its shape and physical properties. The self-assembled monolayer is a regularly ordered monomolecular organic molecular membrane spontaneously coated on the surface of a given substrate. The self-assembled material used for the self-assembled monolayer consists of three parts. For example, the compound forming the self-assembled monolayer may include a reactor in the head portion that binds to the substrate, a long alkyl chain in the body portion that enables regular molecular membrane formation, and a tail that governs the function of the molecular membrane. May include a functional group of the moiety. The functional group may be a hydrogen atom or an alkyl group, but may include various other groups such as NH 2 , OH, or COOH in order to impart specific functions to the molecular membrane, but is not limited thereto.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. However, the present application is not limited to these embodiments and examples.

1A to 1C are schematic diagrams illustrating a method of manufacturing a thin film transistor and a structure of the thin film transistor according to the exemplary embodiment of the present application. Hereinafter, a method of manufacturing a thin film transistor and a thin film transistor according to the exemplary embodiment of the present application will be described in detail with reference to FIGS. 1A to 1C.

First, as shown in FIG. 1A, the self-assembled monolayer 200 may be formed on the substrate 100.

The substrate 100 may be used without particular limitation as long as it is a substrate generally used for semiconductor devices. For example, as the substrate 100, a transparent inorganic substrate such as glass, quartz, Al 2 O 3 , SiC, MgO; Polyethylenedioxythiopene (PEDOT), polystyrenesulfonate (PSS), PEDOT / PSS, polyvinylpyrrolidone (PVP), polyethylene terephthalate (PET), polybutylene terephthalate (PBT), Polysilane, polysiloxane, polysilazane, polyethylene (PE), polycarbosilane, polyacrylate, polymethacrylate, polymethylacrylate ( polymethylacrylate, polymethyl methacrylate (PMMA), polyethylacrylate, cyclic olefin copolymer (COC), polyethylmethacrylate, cyclic olefin polymer (COP), polypropylene (PP ), Polyimide (PI), polystyrene (PS), polyvinyl chloride (PVC), polyacetal (POM), polyether ether ketone (PEEK), polyester sulfone (PES), polyte Organic substrates having one or more of transparency, flexibility, and stretchability, such as trifluoroethylene (PTFE), polyvinylidene fluoride (PVDF), and perfluoroalkyl (PFA) polymer; Or substrates such as Si, Ge, GaAs, InP, InSb, InAs, AlAs, AlSb, CdTe, ZnTe, ZnS, CdSe, CdSb, GaP, but are not limited thereto.

The self-assembled monolayer 200 may be hydrophobic, but is not limited thereto. For example, the self-assembled monolayer 200 is about 1 to about 30, about 1 to about 25, about 1 to about 20, about 3 to about 30, or about 3 to about 25, or about 3 to about 20 It may be formed using a compound for forming a self-assembled monolayer comprising an alkyl group having a carbon number, but is not limited thereto. The compound for forming the self-assembled monolayer may be an alkylsilane-based compound, but is not limited thereto. For example, the alkylsilane-based compound may include octyltrichlorosilane (OCS), hexamethyldisilazane (HMDS), octadecyltrichlorosilane (ODTS), and (3-aminopropyl) trimethol. Methoxysilane [(3-Aminopropyl) trimethoxysilane; APS], Perfluorodecyltrichlorosilane (PFS), Mercaptopropyltrimethoxysilane (MPTMS), Octadecyltrimethoxysilane (OTMS), (heptadecafluoro-1,1 , 2,2-tetrahydrodecyl) trichlorosilane [(Heptadecafluoro-1,1,2,2-tetrahydrodecyl) trichlorosilane; FDTS], perfluorodecyltrichlorosilane (1H, 1H, 2H, 2H-perfluorodecyltrichlorosilane; FOTS), dichlorodimethylsilane (DDMS) and combinations thereof, but may be selected from the group consisting of It is not limited to this.

The alkylsilane-based compound for forming the self-assembled monolayer may include an alkyltrichlorosilane compound, but is not limited thereto. For example, the carbon number of the alkyl group included in the alkyltrichlorosilane compound is about 1 to about 30, about 1 to about 25, about 1 to about 20, about 3 to about 30, or about 3 to about 25, or about About 3 to about 20, or about 3 to about 20, but is not limited thereto. Non-limiting examples of the alkyltrichlorosilane compound include octyltrichlorosilane (OTS), octadecyltrichlorosilane (ODTS), hexamethyldisilazane (HMDS), allyltrichlorosilane (Allyltrichlorosilane) And the like, but is not limited thereto.

In the self-assembled monolayer 200, organic molecules are arranged in a predetermined direction, thereby adjusting the molecular arrangement of the layer on which the self-assembled monolayer 200 is deposited or improving the microstructure of the layer to improve electrical mobility. Specifically, the graphene layer may be modified by the hydrophobic self-assembled monolayer and the graphene layer may be improved by forming a hydrophobic self-assembled monolayer on the substrate and a graphene layer on the hydrophobic self-assembled monolayer. That is, the hydrophobic self-assembled monolayer formed between the substrate and the graphene layer acts as a buffer layer to make SiO 2 The electron mobility can be increased by modifying the graphene layer by reducing the p-doping effect of the graphene layer due to the substrate such as the substrate. In addition, by modifying the carbon number or the structural group of the alkyl group included in the hydrophobic self-assembled monolayer, it is possible to adjust the degree of modification of the graphene layer and the degree of improvement of electrical properties.

According to one embodiment of the present application, the self-assembled monolayer 200 may be formed by a coating method, a dipping method or a printing method, but is not limited thereto. In one embodiment, the self-assembled monolayer may be formed by applying to the substrate by a spin coating method in the form of a solution or may be applied on the substrate by dipping the substrate in a bath in which the self-assembled monolayer is in solution . For example, OTS may be dissolved in toluene solvent to form a concentration of about 10 mM and submerged for about 20 seconds at a temperature of about 300 K. In addition, the self-assembled monolayer may be formed by printing at a desired position by a printing method, but is not limited thereto.

Subsequently, as illustrated in FIG. 1B, a graphene layer 300 may be formed on the self-assembled monolayer 200 to form a channel region.

The graphene refers to a polycyclic aromatic molecule formed by coupling a plurality of carbon atoms covalently to each other, wherein the covalently linked carbon atoms form a 6-membered ring as a basic repeating unit, but a 5-membered ring and / or a 7-membered ring It is also possible to include more. Thus, the graphene appears as a single layer of covalently bonded carbon atoms (usually sp2 bonds). The graphene may have a variety of structures, such a structure may vary depending on the content of 5-membered and / or 7-membered rings that may be included in the graphene. The graphene may be formed of a single layer, but they may be stacked with each other to form a plurality of layers, and form a thickness up to about 100 nm.

The graphene layer 300 may be prepared by a method known in the art. For example, the graphene may be formed by using chemical vapor deposition (CVD), but is not limited thereto, and may be used without particular limitation. . When the graphene is formed using a chemical vapor deposition method, for example, any method commonly used for growing a graphene layer using chemical vapor deposition on a metal catalyst layer may be used without particular limitation. For example, the graphene layer may use chemical vapor deposition on a metal catalyst layer, and the chemical vapor deposition may include rapid thermal chemical vapor deposition (RTCVD) and inductively coupled plasma chemical vapor deposition (Inductively Coupled Plasma-Chemical). Vapor Deposition (ICP-CVD), Low Pressure Chemical Vapor Deposition (LPCVD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), Metal Organic Chemical Vapor Deposition (MOCVD) , And plasma-enhanced chemical vapor deposition (PECVD), but is not limited thereto.

The metal catalyst layer serves as a catalyst for facilitating the growth of the graphene layer 300, and may be used without particular limitation in terms of its material, thickness, and shape. For example, the metal catalyst layer is Ni, Co, Fe, Pt, Au, Al, Cr, Cu, Mg, Mn, Mo, Rh, Si, Ta, Ti, W, U, V, Zr, brass It may include, but is not limited to, one or more metals or alloys selected from the group consisting of bronze, copper, copper, stainless steel, and Ge.

Subsequently, as shown in FIG. 1C, a source electrode 420 and a drain electrode 440 may be formed on both sides of the substrate 100 to be electrically connected to the channel region.

The source electrode 420 and the drain electrode 440 are Au, Al, Ag, Be, Bi, Co, Cu, Cr, Hf, In, Mn, Mo, Mg, Ni, Nb, Pb, Pd, Pt, Rh , Re, Ru, Sb, Ta, Te, Ti, V, W, Zr, Zn, and combinations thereof may be included.

The source electrode 420 and the drain electrode 440 may be formed by chemical vapor deposition, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition using a shadow mask. It may be formed by a deposition method such as physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD), evaporation, and the like, but is not limited thereto.

For example, p-doping of the graphene channel region is reduced by reducing the use of photoresist used in an etching process by directly forming a source electrode and a drain electrode on both sides of the graphene channel region, respectively, using a shadow mask. The effect can be reduced.

In the thin film transistor fabricated as described above, as the distance between the substrate and the graphene layer increases through the self-assembled monolayer 200, the p-doping effect is decreased, thereby reducing the interference of the graphene layer and increasing the charge mobility. You can see the effect to make. Therefore, it is possible to fabricate a high performance thin film transistor having improved electrical characteristics of the transparent electrode and the graphene thin film transistor using the self-assembled monolayer, and by manufacturing such a high performance thin film transistor to improve device performance to control semiconductor properties and to provide a high sensitivity sensor. It can be used as an organic solar cell because of the advantage that the application of display, touch screen, OLED and work function between organic materials is not big.

Hereinafter, the present invention will be described in detail with reference to embodiments and drawings. However, the present invention is not limited to these embodiments and drawings.

Materials and device  Produce

For the production of SAMs on SiO 2 / Si substrate was cleaned in a hot solution consisting of blood Rana the SiO 2 / Si substrate with 70% H 2 SO 4 and 30% H 2 O 2. After washing with distilled water, the substrate was placed in a vacuum drying reaction flask. 20 ml of toluene was then added to the reaction flask with 10 mM of a silane coupling agent. Subsequently, hydrophobic self-assembled monolayers (SAMs) were formed on the substrate using octyl trichlorosilane (OTS), octadecyl trichlorosilane (ODTS), and hexamethyldisilane (HMDS), respectively. Formation of self-assembled monolayers (SAMs) using octyl trichlorosilane (OTS) and octadecyl trichlorosilane (ODTS), respectively, was performed for 1 hour under argon atmosphere. After the reaction was over, the SAMs treated substrate was baked at 120 ° C. for 20 minutes, sonicated for 2 minutes, washed with toluene and dried under vacuum. HMDS, on the other hand, was spin coated onto a clean SiO 2 / Si substrate, which was baked at 150 ° C. for 1 hour. The HMDS treated substrate was then washed with ethanol and dried under vacuum.

Graphene was synthesized by CVD process. The monolayer graphene film grown on copper foil was coated with polymethylmethacrylate (PMMA, Mw = 240 kg mol -1 ) and in an aqueous solution of 0.1 M ammonia persulfate ((NH 2 ) 4 S 2 O 8 ) solution. Floated. After etching all the copper layers, the graphene film with PMMA support was transferred to various SAM - modified SiO 2 (300 nm, capacitance = 10.8 nFcm −2 ) / Si substrates. After removing the PMMA support layer with acetone, the graphene film remained on the silicon substrate. As source / drain electrodes in graphene FETs, Au was thermally deposited through a shadow mask (channel length 30 μm, channel width 300 μm).

Measure

The surface energy of the prepared SAMs was measured by measuring the contact angle of two probe liquids (deionized water and diiodomethane). The thickness of the SAMs was measured using an ellipsometer (M-2000V, JA Woollam), and the root-mean-square (rms) roughness was determined by atomic force microscopy (AFM, Digital Instrument). Was measured. The packing density of the alkyl chains contained in the SAMs was measured by X-ray photon emission spectroscopy using a VG ESCALAB 220i spectrometer with Al Kα X-ray line (1486.6 eV). The alkyl chains were examined by FT-IR spectroscopy (Bruker IFS 66v). The optical properties of the graphene film were obtained by Raman spectroscopy (Renishaw, RM-1000 Invia) with an excitation energy of 2.41 eV (514 nm, Ar + ion laser). The work function of the graphene film was measured by measuring the secondary electron blocking spectrum by UPS at 4B1 beamline of Pohang Accelerator Laboratory, Republic of Korea. The current-voltage characteristics of graphene FETs were analyzed using a Keithley 2636A semiconductor parameter analyzer.

A systematic analysis of the effect of the self-assembled monolayer as a buffer layer on the performance of graphene FETs was performed using CVD-grown large area graphene. The chemical and physical properties of the graphene / dielectric (SiO 2 ) interactions include two organic alkyl silanes, octyltrichloro, having various alkyl chain lengths (C8 or C18, respectively), as well as SiO 2 substrates with HMDS having an alkyl chain length of C1. Controlled by treatment with hydrophobic self-assembled monolayers (SAMs) of silane (OTS) and octadecyltrichlorosilane (ODTS). The buffer layer modified the chemical and physical properties of the graphene interactions that modulated the electrical response of the graphene FETs. Thus, the performance of the graphene FET is significantly improved due to the presence of the SAM buffer layer.

SAMs were prepared in a simple and straightforward manner. OTS and ODTS-SAMs spontaneously self-assemble on the gate dielectric (SiO 2 ) surface through surface reactions including hydrolysis and condensation. The HMDS buffer layer was prepared on the SiO 2 surface by spin coating. The physical properties of the SAMs and the surface wettability of the SAM-modified SiO 2 surface are shown in Table 1 below. As expected, the thickness of SAMs increased with increasing alkyl chain length.

Figure pat00001

FIG. 2 shows the XPS spectra for determining the chain packing density of SAMs in anticipation of increasing the thickness of SAMs as the alkyl chain length increases. The C 1s peak of FIG. 2A was observed at 284.6 eV, showing that the peak increased with increasing alkyl chain length (HMDS <OTS <ODTS). Si 2p Peaks were observed at 99.3 (Si 0 ) and 103.3 (Si 4 + ) eV and showed a decrease in peak with increasing alkyl chain length.

The C 1s / Si 2p peak ratio normalized by the thickness of the SAMs was used as a standard for the relevant alkyl chain packing density. ODTS-SAMs showed high packing density (10%) with respect to the packing density of HMDS and OTS-SAMs. This observation was studied by characterizing the physical structures of OTS and ODTS-SAMs by Fourier Transform Infrared (FT-IR) spectroscopy. As the number of C atoms increases from 8 (OTS) to 18 (ODTS), the CH 2 symmetrical vibration is from 2855 to 2851 cm -1 and the asymmetrical vibration is from 2927 to 2920 cm -1 with the lower wavelength of the peak. Moved. The shift in peak indicates that the arrangement of alkyl chains in SAMs has changed from disordered (OTS) to ordered (ODTS). Changes in the alkyl chains were affected by van der Waals forces between the longer alkyl chains. SiO 2 surfaces with HMDS, on the other hand, do not contain CH 2 oscillations because of the characteristic of having one alkyl chain as shown in FIG. 2D. HMDS reacts only with silanol groups in SiO 2 and is not made by a self-condensation process. Due to the limitation of one alkyl chain length and the reaction point of HMDS, the surface energy of SiO 2 with HMDS is much higher than that of SiO 2 modified with OTS and ODTS-SAMs.

FIG. 3A is a Raman spectra analysis on SiO 2 modified with various SAMs to analyze the chemical and physical properties of graphene. As the alkyl chain length increases (Untreated <HMDS <OTS <ODTS), the 2D band intensity increases. In addition, the O-band and ODTS SAMs showed that the position of the G band in modified SiO 2 was clearly red-shifted from the peak position of the untreated SiO 2 substrate. The intensity ratio of the 2D / G band and the full width at half maximum (FWHM) of the 2D band are usually used to identify doping in graphene. The 2D / G band intensity ratio increased with increasing alkyl chain length, and the 2D band width showed the opposite trend. This change in peak intensity and width demonstrates that doping can be effectively reduced by using SAMs with long alkyl chain lengths as buffer layers.

The doping characteristics were measured by calculating the work function of the graphene film from the ultraviolet photon emission spectra, as shown in FIG. 2C. The change in onset of the secondary electron is consistent with the change in work function during graphene:

Figure pat00002

Where ħω = 21.2 eV (He I source), Esec is onset of secondary emission, and EFE is Fermi edge (22.0 eV from valence band spectrum, under a sample bias of -5 V, 4B1 beamline in Pohang Accelerator Laboratory). Measured at).

Graphene work function is decreased with no unprocessed SiO 2 was 4.5 eV, with SiO 2 modified with an alkyl chain length of SAMs ODTS is increased to 4.25 eV of. Graphene of SiO 2 / Si SiO 2 described above is yes at pin Hole doping is known to occur due to charge transfer to various adsorbents such as oxygen and water molecules on the substrate. SAMs have SiO 2 When on a substrate, a buffer layer is to give the most reactive prevent a good spot in the SiO 2 effectively, SiO 2 Prevent the adsorbate coupling from above. The blocking effect could be varied by the binding characteristics. Well-arranged and tightly packed ODTS SAMs exhibited the highest blocking effect against hole doping and graphene on ODTS SAMs exhibited the lowest work function. On the other hand, HMDS on SiO 2 is a single alkyl chain with very low work function due to limitations in the self-condensation process. Therefore, hole doping, which can be seen from the work function of graphene, was increased in the order of ODTS <OTS <HMDS <Untreated.

Au source / drain electrodes were deposited directly onto graphene without using a photolithography process to test the effect of the SAMs buffer layer on the graphene's electrical properties (FIG. 4A). If the photoresist is left on the graphene, graphene doping is performed, so an electrode was made using a 300 μm wide and 30 μm long shadow mask. 4B shows the conductivity of graphene FETs on SiO 2 / Si modified with various SAMs. Conductivity at V G was found to be significantly affected by SAMs. V G of any unprocessed SiO 2 has a V G of the modified SiO 2 at 52 V to ODTS was gradually changed to V 24. Since this transition voltage is determined by the excess charge carriers remaining in the graphene, it is directly correlated with the doping type and size in the graphene film. As shown in FIG. 4C, V G Dirac further changed from V G = 0 V as alkyl chain length of increased SAMs. The positive value of V G Dirac in graphene FETs is due to the hole doping of graphene by PMMA polymer residues covering the graphene surface.

Carrier mobility was calculated in a linear regime using the following equation.

Figure pat00003

Where C i = 1.08 × 10 -8 Fcm -2 , g m = dI D / dV G , V D = 0.01 V, L = 30 µm and W = 300 µm.

As shown in FIG. 4D and Table 2 below, as the alkyl chain length of SAMs increases, electron and hole mobility increase (Untreated <HMDS <OTS <ODTS).

Figure pat00004

The asymmetry observed during hole and electron mobility may be due to scattering cross-sectional area differences for holes and electrons or drift in charged impurities from the substrate.

Clearly, both electron and hole mobility increased more than 3-folds for buffer layers made from SMAs with long alkyl chains. SiO2 Since the surface roughness observed after deposition of SMAs on the phase did not decrease (Table 1), the improved mobility was directly due to SiO2 SiO of the surface2 Surfaces correlate with effective screening that limits graphene mobility because of charged impurities. The mobility obtained in this example was relatively lower than that corresponding to the spreading transport regime. Charged impurity scattering can provide a predominant scattering mechanism if residual impurities in the graphene are responsible for carrier transport under electrons and hole puddles.

Carrier Density of Graphene Caused by VG in the Presence of Impurity Doping

Figure pat00005
Was calculated using the equation:

Figure pat00006

Where η = 7.2 × 10 10 cm -2 V - 1.

4E shows a plot of conductivity as a function of carrier density near V G Dirac . The minimum conductivity (ie σ (V G = V G Dirac )) and the plateau width at the minimum conductivity depended on the similarity of the SAMs inserted between the graphene and the SiO 2 surface. The trends in 1) V G Dirac , 2) electron and hole mobility, 3) minimum conductivity, and 4) plateau width are in good agreement with the carrier transport mechanism for charged impurity scattering. As the density of charged impurities decreased, FETs showed low V G Dirac values, higher hole / electron mobility, higher minimum conductivity, and narrower plateau widths.

Figure 4e is a graph showing the conductivity according to the charge density, it can be seen from the graph that the mobility of electrons and holes significantly increased as shown in Figure 4f of the graphene FETs.

The electrical properties of graphene FETs can be seen that the conductivity is gradually increased when surface treatment with HMDS, OTS, ODTS than the substrate treatment in the order of ODTS <OTS <HMDS <Untreated. In addition, sublinear conductivity at high V G is clearly observed in the transconductance gm curve for ODTS SAM, as shown in FIG. 4F, and correlates with changes in the scattering mechanism from long distance scattering to short distance scattering. Electrical measurements confirmed that SAMs with long alkyl chain lengths effectively screened the charged impurities from the adsorbents on the SiO 2 surface, reduced graphene doping when inserted between graphene and SiO 2 , and The electrical properties of FETs have been improved.

In conclusion, various hydrophobic SAMs effects inserted between CVD grown large-area graphene and SiO 2 substrates have been reported. The chemical and physical properties of graphene and the electrical properties of graphene FETs were studied for various SAMs. As the alkyl chain length of SAMs increases, graphene FETs are less affected by surface induced doping of graphene, and graphene FETs show higher hole / electron mobility where they have lower values of de-lock point voltage.

In addition, the change in electrical properties in the existing SAMs can be explained by charged impurity scattering, indicating that the charged impurities in graphene could be controlled by the alkyl chain length of the SAM inserted between the graphene and SiO 2 substrate. have.

Surface modification using various SAMs was found to play a big role in enhancing the graphene device characteristics by enhancing the electrical properties of graphene FETs.

It will be understood by those of ordinary skill in the art that the foregoing description of the embodiments is for illustrative purposes and that those skilled in the art can easily modify the invention without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

100: substrate
200: self-assembled monolayer
300: graphene layer
420: source electrode
440: drain electrode

Claims (18)

materials;
A source electrode and a drain electrode formed on the substrate; And
A channel region formed on the substrate to be electrically connected between the source electrode and the drain electrode:
As a thin film transistor,
The channel region includes self-assembled monolayers (SAMs) and a graphene layer formed on the self-assembled monolayers,
Thin film transistor.
The method of claim 1,
The self-assembled monolayer has a hydrophobic, thin film transistor.
The method of claim 1,
The self-assembled monolayer is a thin film transistor formed using a compound for forming a self-assembled monolayer comprising an alkyl group.
The method of claim 3, wherein
The alkyl group is a thin film transistor having 1 to 30 carbon atoms.
The method of claim 3, wherein
The compound for forming a self-assembled monolayer is a thin film transistor comprising an alkylsilane-based compound.
The method of claim 3, wherein
The compound for forming the self-assembled monolayer is octyltrichlorosilane (OCS), hexamethyldisilazane (HMDS), octadecyltrichlorosilane (Octadecyltrichlorosilane (ODTS), (3-aminopropyl) trimethoxysilane [ (3-Aminopropyl) trimethoxysilane; APS], Perfluorodecyltrichlorosilane (PFS), Mercaptopropyltrimethoxysilane (MPTMS), Octadecyltrimethoxysilane (OTMS), (heptadecafluoro-1,1 , 2,2-tetrahydrodecyl) trichlorosilane [(Heptadecafluoro-1,1,2,2-tetrahydrodecyl) trichlorosilane; FDTS], perfluorodecyltrichlorosilane (1H, 1H, 2H, 2H-perfluorodecyltrichlorosilane; FOTS), dichlorodimethylsilane (DDMS) and thin film, including those selected from the group consisting of transistor.
The method of claim 1,
The source electrode and the drain electrode are Au, Al, Ag, Be, Bi, Co, Cu, Cr, Hf, In, Mn, Mo, Mg, Ni, Nb, Pb, Pd, Pt, Rh, Re, Ru, A thin film transistor comprising one selected from the group consisting of Sb, Ta, Te, Ti, V, W, Zr, Zn and combinations thereof.
The method of claim 1,
And the substrate is a metal oxide substrate, a semiconductor substrate, a glass substrate, or a plastic substrate.
The method of claim 1,
The graphene layer is a thin film transistor formed by transferring the graphene prepared by chemical vapor deposition on the hydrophobic self-assembled monolayer.
Forming a hydrophobic self-assembled monolayer on the substrate;
Forming a channel region by forming a graphene layer on the hydrophobic self-assembled monolayer; And
Forming a source electrode and a drain electrode on the substrate, each of which is electrically connected to both sides of the channel region;
A manufacturing method of a thin film transistor comprising a.
11. The method of claim 10,
The hydrophobic self-assembled monolayer is formed using a compound for forming a self-assembled monolayer containing an alkyl group, a thin film transistor manufacturing method.
The method of claim 11,
The alkyl group has a carbon number of 1 to 30, the manufacturing method of the thin film transistor.
The method of claim 11,
The compound for forming a self-assembled monolayer is a method of manufacturing a thin film transistor comprising an alkylsilane-based compound.
The method of claim 11,
The compound for forming the self-assembled monolayer is octyltrichlorosilane (OCS), hexamethyldisilazane (HMDS), octadecyltrichlorosilane (Octadecyltrichlorosilane (ODTS), (3-aminopropyl) trimethoxysilane [ (3-Aminopropyl) trimethoxysilane; APS], Perfluorodecyltrichlorosilane (PFS), Mercaptopropyltrimethoxysilane (MPTMS), Octadecyltrimethoxysilane (OTMS), (heptadecafluoro-1,1 , 2,2-tetrahydrodecyl) trichlorosilane [(Heptadecafluoro-1,1,2,2-tetrahydrodecyl) trichlorosilane; FDTS], perfluorodecyltrichlorosilane (1H, 1H, 2H, 2H-perfluorodecyltrichlorosilane; FOTS), dichlorodimethylsilane (DDMS) and thin film, including those selected from the group consisting of Method of manufacturing a transistor.
11. The method of claim 10,
The source electrode and the drain electrode are Au, Al, Ag, Be, Bi, Co, Cu, Cr, Hf, In, Mn, Mo, Mg, Ni, Nb, Pb, Pd, Pt, Rh, Re, Ru, Sb, Ta, Te, Ti, V, W, Zr, Zn, and combinations thereof.
11. The method of claim 10,
The substrate is a metal oxide substrate, a semiconductor substrate, a glass substrate or a plastic substrate, the manufacturing method of the thin film transistor.
11. The method of claim 10,
The graphene layer is formed by transferring the graphene prepared by chemical vapor deposition on the hydrophobic self-assembled monolayer, a method of manufacturing a thin film transistor.
11. The method of claim 10,
Forming the source electrode and the drain electrode includes depositing the source electrode and the drain electrode on the substrate, the source electrode and the drain electrode respectively electrically connected to both sides on the channel region using a shadow mask. Manufacturing method.
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US20160005881A1 (en) * 2013-04-18 2016-01-07 Fuji Electric Co., Ltd. Stacked films and method for producing stacked films
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Publication number Priority date Publication date Assignee Title
US20160005881A1 (en) * 2013-04-18 2016-01-07 Fuji Electric Co., Ltd. Stacked films and method for producing stacked films
CN103482622A (en) * 2013-09-18 2014-01-01 武汉理工大学 Preparing method for single-layer graphene film with strong stability and high conductivity
CN104330929A (en) * 2014-11-05 2015-02-04 华中科技大学 Light control chip based on electric control liquid crystal dual-mode micro lens
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