KR20130022799A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
KR20130022799A
KR20130022799A KR1020110085716A KR20110085716A KR20130022799A KR 20130022799 A KR20130022799 A KR 20130022799A KR 1020110085716 A KR1020110085716 A KR 1020110085716A KR 20110085716 A KR20110085716 A KR 20110085716A KR 20130022799 A KR20130022799 A KR 20130022799A
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KR
South Korea
Prior art keywords
conductive
trench
epitaxial layer
silicon
column
Prior art date
Application number
KR1020110085716A
Other languages
Korean (ko)
Inventor
홍기석
Original Assignee
주식회사 케이이씨
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Application filed by 주식회사 케이이씨 filed Critical 주식회사 케이이씨
Priority to KR1020110085716A priority Critical patent/KR20130022799A/en
Publication of KR20130022799A publication Critical patent/KR20130022799A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation

Abstract

One embodiment of the present invention relates to a power semiconductor device, the technical problem to be solved is to provide a power semiconductor device in a low cost and simple process.
To this end, the present invention is a first conductive semiconductor substrate; A first conductive epitaxial layer formed on the first conductive semiconductor substrate and having a trench having a depth; A second conductive column formed in the trench of the first conductive epitaxial layer; A second conductive body connected to the second conductive column and formed in the first conductive epitaxial layer; A first conductive source region formed in the second conductive body; A gate oxide layer formed over the first conductive epitaxial layer, the second conductive body, and the first conductive source region; And a gate electrode formed over the gate oxide film.

Description

Power semiconductor device {POWER SEMICONDUCTOR DEVICE}

One embodiment of the invention is directed to a power semiconductor device.

In general, super junction power semiconductor devices based on the charge compensation principle have been widely used as switches such as inverters due to low on resistance (Ron).

Such power semiconductor devices use various methods to make super junction structures. For example, the super junction structure may be formed by forming the first conductive region and the second conductive region by a plurality of epitaxial processes. In this case, there is a problem that the manufacturing cost increases considerably by using a plurality of epitaxial processes. In addition, a deep trench may be formed in the first conductive region, and a second junction region may be formed in the trench by an optional epitaxial process to form a super junction structure. In this case as well, there is a problem in that an additional epitaxial process is performed to significantly increase the manufacturing cost.

One embodiment of the present invention provides a power semiconductor device capable of implementing a super junction structure at a low cost and in a short time.

A power semiconductor device according to an embodiment of the present invention includes a first conductive semiconductor substrate; A first conductive epitaxial layer formed on the first conductive semiconductor substrate and having a trench having a depth; A second conductive column formed in the trench of the first conductive epitaxial layer; A second conductive body connected to the second conductive column and formed in the first conductive epitaxial layer; A first conductive source region formed in the second conductive body; A gate oxide layer formed over the first conductive epitaxial layer, the second conductive body, and the first conductive source region; And a gate electrode formed on the gate oxide film.

The second conductive column may be formed by crystallization after injecting a second conductive impurity into amorphous silicon.

The second conductive column may be formed by crystallization after injecting a second conductive impurity into polysilicon.

The second conductive column may have at least one grain boundary.

A method of manufacturing a power semiconductor device according to another embodiment of the present invention includes a first conductive semiconductor substrate, a first conductive epitaxial layer is formed on the first conductive semiconductor substrate, and the first conductive epitaxial layer. Forming a trench having a depth in the textural layer; Depositing silicon on the surface of the trench; Implanting a second conductive impurity into the deposited silicon; Forming a second conductive column by depositing additional silicon on the surface of the silicon into which the second conductive impurity is implanted to completely fill the trench, thereby forming a second conductive column; And forming a second conductive body, a first conductive source region, a gate oxide layer, and a gate electrode on the second conductive column.

The silicone may be amorphous silicon or polysilicon.

In the second conductive column forming step, the additional silicon is deposited to fill the trench, and then heat treated for 10 to 50 minutes in a temperature atmosphere of 600 ° C to 700 ° C. At least one grain boundary may be formed in the second conductive column by the heat treatment.

According to an embodiment of the present invention, by forming a trench in the first conductive epitaxial layer and forming a second conductive column, that is, a super junction structure, through a process such as deposition, impurity implantation, and heat treatment inside the trench, Provided is a power semiconductor device having a super junction in a low cost and simple manner.

1 is a cross-sectional view illustrating a power semiconductor device according to an embodiment of the present invention.
2A to 2G are sequential cross-sectional views illustrating a method of manufacturing a power semiconductor device according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

1 is a cross-sectional view illustrating a power semiconductor device 100 according to an embodiment of the present invention.

As shown in FIG. 1, the power semiconductor device 100 according to the present invention may include a first conductive semiconductor substrate 110, a first conductive epitaxial layer 120, a second conductive column 130, and a first conductive semiconductor substrate 110. And a second conductive body 140, a first conductive source region 150, a gate oxide layer 160, and a gate electrode 170.

The first conductive semiconductor substrate 110 may be a silicon semiconductor substrate containing a generally flat first conductive impurity.

The first conductive epitaxial layer 120 is formed on the first conductive semiconductor substrate 110 to have a predetermined thickness, and may be silicon containing a conventional first conductive type impurity. The first conductive epitaxial layer 120 is provided with a trench 121 having a predetermined depth.

The second conductive column 130 is formed to be embedded in the trench 121, which may be silicon containing a second conductive impurity. In particular, the second conductive column 130 may be crystallized by injecting a second conductive impurity into amorphous silicon or polysilicon. Of course, since amorphous silicon or polysilicon is crystallized in this manner, the second conductive column 130 may have at least one grain boundary.

Here, the second conductive column 130 and the first conductive epitaxial layer 120 positioned on the side of the second conductive column 130 form a super junction structure. The amount of charges is compensated for, thereby having a low on resistance (Ron). Since the charge compensation by the super junction structure and the low on-resistance are already well known to those skilled in the art, the description thereof is omitted here.

The second conductive body 140 is formed over a predetermined depth in the inward direction from the surface of the first conductive epitaxial layer 120 and is electrically connected to the second conductive column 130. do. The second conductive body 140 is formed by ion implanting and heat treating a second conductive impurity on the surface of the first conductive epitaxial layer 120.

The first conductive source region 150 is formed at a predetermined depth from the surface of the second conductive body 140 toward the inner side. The first conductive source region 150 is formed by ion implanting and heat treating a first conductive impurity on the surface of the second conductive body 140.

The gate oxide layer 160 is formed over the first conductive epitaxial layer 120, the second conductive body 140, and the first conductive source region 150. In addition, the gate electrode 170 is formed to have a predetermined thickness on the gate oxide layer 160. This gate electrode 170 may be formed of conventional doped polysilicon.

In addition, although not illustrated in the drawings, an interlayer insulating film may be formed to cover the gate oxide film 160 and the gate electrode 170, and a source metal may be formed outside the interlayer insulating film. The source metal is electrically connected to the second conductive body 140 and the first conductive source region 150. In addition, a drain metal may be formed on the bottom surface of the first conductive semiconductor substrate 110. In addition, a gate metal is formed at a predetermined position spaced apart from the source metal.

Therefore, when a predetermined potential difference is applied between the source metal and the drain metal, and a voltage equal to or greater than a threshold voltage is applied to the gate metal, a channel is formed in the second conductive body 140 and the gap between the source metal and the drain metal. An electric current flows in.

In this way, according to the present invention, a trench 121 is formed in the first conductive epitaxial layer 120, and the amorphous silicon or polysilicon in which the second conductive impurity is doped is embedded in the trench 121. After the heat treatment, the second conductive column 130 is naturally formed. The second conductive column 130 forms a super junction structure together with the first conductive epitaxial layer 120. Thus, the present invention provides a power semiconductor device 100 having a super junction structure in a low cost and simple process. Will be implemented. Here, the first conductivity type usually means a conductivity type with n-type impurities, and the second conductivity type usually means a conductivity type with p-type impurities.

2A-2G are sequential cross-sectional views illustrating a method of manufacturing the power semiconductor device 100 according to another embodiment of the present invention.

In another embodiment, a method of manufacturing a power semiconductor device 100 may include a trench formation step, a silicon deposition step, a second conductive impurity implantation step, a second conductive column formation step, an etching step, a heat treatment step, and a device formation. Steps. This will be described with reference to FIGS. 2A to 2G.

As shown in FIG. 2A, in the trench forming step, the first conductive semiconductor substrate 110 is first provided, and the first conductive epitaxial layer 120 having a predetermined thickness is formed on the first conductive semiconductor substrate 110. And a trench 121 having a predetermined depth in the first conductive epitaxial layer 120. Of course, a mask 101 having a trench pattern is formed on the surface of the first conductive epitaxial layer 120 before the formation of the trench 121.

As shown in FIG. 2B, in the silicon deposition step, silicon 130a having a predetermined thickness is deposited along the surface of the trench 121. Here, the silicon 130a may be any one selected from conventional amorphous silicon, polysilicon, and the like, and the material is not limited thereto. In this case, the silicon 130a is thinly formed along the surface of the trench 121, and thus the trench 121 is not completely filled by the silicon 130a.

As illustrated in FIG. 2C, in the second conductive impurity implantation step, the second conductive impurity 130c is ion-implanted on the surface of the silicon 130a thinly formed on the surface of the trench 121. Through this process, the entire surface of the silicon 130a includes the second conductive impurity 130c at a predetermined concentration.

As shown in FIG. 2D, in the second conductive column forming step, the trench 121 is further formed by depositing additional silicon 130b on the surface of the silicon 130a into which the second conductive impurity 130c is implanted. By completely embedding, the second conductive column 130 is formed.

As shown in FIG. 2E, in the etching step, all silicon 130a and 130b remaining on the surface of the first conductive epitaxial layer 120 are etched and removed. At this time, the mask 101 remaining on the surface of the first conductive epitaxial layer 120 is also removed by etching.

As shown in FIG. 2F, in the heat treatment step, heat treatment is performed for about 10 to 50 minutes in a temperature atmosphere of about 600 ° C. to 700 ° C. FIG. By such a heat treatment, not only the second conductive impurities 130c injected into the silicon 130a and 130b are diffused and distributed in the entire second conductive column 130, but the amorphous silicon or polysilicon is crystallized. do. As described above, the aphos silicon or the polysilicon may have at least one grain boundary unlike the first conductive semiconductor substrate 110 or the first conductive epitaxial layer 120.

As shown in FIG. 2G, in the device forming step, the second conductive body 140, the first conductive source region 150, the gate oxide layer 160, and the gate are disposed on the second conductive column 130. The electrodes 170 are sequentially formed. Of course, the device is completed by forming an interlayer insulating film, a source metal, a drain metal, and a gate metal.

Thus, the present invention utilizes a super-junction structure using a low cost process consisting of silicon deposition, ion implantation and heat treatment instead of using conventional multi-epitaxial processes or complex and expensive processes such as deep trench and selective epitaxial processes. It is to provide a power semiconductor device having a.

What has been described above is only one embodiment for implementing the power semiconductor device according to the present invention, and the present invention is not limited to the above-described embodiment, and as claimed in the following claims, the gist of the present invention Without departing from the scope of the present invention, any person having ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

100; Power semiconductor device according to the present invention
110; A first conductive semiconductor substrate 120; First conductive epitaxial layer
130; Second conductive column 140; Second conductive body
150; First conductive source region 160; Gate oxide film
170; Gate electrode

Claims (8)

A first conductivity type semiconductor substrate;
A first conductive epitaxial layer formed on the first conductive semiconductor substrate and having a trench having a depth;
A second conductive column formed in the trench of the first conductive epitaxial layer;
A second conductive body connected to the second conductive column and formed in the first conductive epitaxial layer;
A first conductive source region formed in the second conductive body;
A gate oxide layer formed over the first conductive epitaxial layer, the second conductive body, and the first conductive source region; And
And a gate electrode formed over the gate oxide film. The method of claim 1,
And the second conductive column is crystallized after implanting a second conductive impurity into amorphous silicon. The method of claim 1,
And wherein the second conductive column is formed by crystallization after injecting a second conductive impurity into polysilicon. The method of claim 1,
And the second conductive column has at least one grain boundary. Forming a trench having a first conductive semiconductor substrate, forming a first conductive epitaxial layer on the first conductive semiconductor substrate, and forming a trench having a depth in the first conductive epitaxial layer;
Depositing silicon on the surface of the trench;
Implanting a second conductive impurity into the deposited silicon;
Forming a second conductive column by depositing additional silicon on the surface of the silicon into which the second conductive impurity is implanted to completely fill the trench, thereby forming a second conductive column; And
And forming a second conductive body, a first conductive source region, a gate oxide film, and a gate electrode over the second conductive column. The method of claim 1,
And said silicon is amorphous silicon or polysilicon. The method of claim 1,
The second conductive column forming step is a method of manufacturing a power semiconductor device, characterized in that the heat treatment for 10 to 50 minutes in a temperature atmosphere of 600 ℃ to 700 ℃ after the additional deposition of silicon to fill the trench. The method of claim 7, wherein
And at least one grain boundary is formed in the second conductive column by the heat treatment.
KR1020110085716A 2011-08-26 2011-08-26 Power semiconductor device KR20130022799A (en)

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KR1020110085716A KR20130022799A (en) 2011-08-26 2011-08-26 Power semiconductor device

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Application Number Priority Date Filing Date Title
KR1020110085716A KR20130022799A (en) 2011-08-26 2011-08-26 Power semiconductor device

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KR20130022799A true KR20130022799A (en) 2013-03-07

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