KR20130020476A - Array substrate for advanced high in plane switching mode liquid crystal display device and method for fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate for an advanced high in plane switching mode liquid crystal display device and a method for fabricating the same are provided to save power consumption by using a photo-acryl layer. CONSTITUTION: A thin film transistor is formed in the intersection point of a data line(115c) and a gate line. A pixel electrode(121a) is directly connected to the thin film transistor. A photosensitive organic insulating film(127a) is formed in the upper part of the thin film transistor and the data line. A passivation film(129) is formed on the photosensitive organic insulating film. Common electrodes(131a) are formed on the passivation film.

Description

AR-SUBSTRATE FOR ADVANCED HIGH IN PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for an advanced high in plane switching (AH-IPS) type liquid crystal display device and a method of manufacturing the same.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

Currently, an active matrix liquid crystal display (AM-LCD: liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and moving picture performance, It is attracting attention.

The liquid crystal display comprises a color filter substrate (i.e., an upper substrate) on which a common electrode is formed, an array substrate (i.e., a lower substrate) on which pixel electrodes are formed, and a liquid crystal filled between the upper substrate and the lower substrate. In the device, the liquid crystal is driven by an electric field in which the common electrode and the pixel electrode are arranged in an up-down direction, and the characteristics such as transmittance and aperture ratio are excellent.

However, liquid crystal driving by an electric field applied in an up-down direction has a disadvantage that the viewing angle characteristic is not excellent. Therefore, in order to overcome the above disadvantages, a newly proposed technique is a liquid crystal driving method using a transverse electric field. The liquid crystal driving method using the transverse electric field has an advantage of excellent viewing angle characteristics.

The transverse type liquid crystal display device includes a color filter substrate and an array substrate facing each other, and a liquid crystal layer is interposed between the color filter substrate and the array substrate.

The array substrate includes a thin film transistor, a common electrode, and a pixel electrode for each of a plurality of pixels defined in a transparent insulating substrate.

In addition, the common electrode and the pixel electrode are configured to be spaced apart from each other in parallel on the same substrate.

In the color filter substrate, a black matrix is formed at a portion corresponding to a gate wiring, a data wiring, and a thin film transistor on a transparent insulating substrate, and a color filter is formed corresponding to the pixel.

The liquid crystal layer is driven by a horizontal electric field of the common electrode and the pixel electrode.

In the transverse electric field type liquid crystal display device having the above configuration, the common electrode and the pixel electrode are typically formed of transparent electrodes in order to secure luminance.

Therefore, the proposed technique to maximize the effect of improving the brightness is the FFS (Fringe Field Switching) technology. The FFS technology has a characteristic that high contrast ratio can be obtained without color shift by precisely controlling the liquid crystal.

A method of manufacturing a FFS (Fringe Field Switching) type liquid crystal display device according to the related art will be described with reference to FIGS. 1 to 3.

1 is a schematic plan view of a FFS (Fringe Field Switching) type liquid crystal display device according to the prior art.

FIG. 2 is an enlarged plan view of part “A” of FIG. 1 and schematically illustrates a black matrix (BM) that covers a drain contact hole in consideration of a bonding margin.

FIG. 3 is a cross-sectional view taken along line III-III of FIG. 1 and is a schematic cross-sectional view of a FFS (Fringe Field Switching) type liquid crystal display device.

As shown in FIGS. 1 to 3, a plurality of gate wirings extending in one direction and spaced in parallel to each other are arranged on the transparent insulating substrate 11 as shown in FIGS. 1 to 3. (13) and common wiring 13b spaced in parallel with the gate wiring 13; A plurality of data wirings 21c intersecting the gate wirings 13 and defining pixel regions in the crossing regions; A gate electrode 13a, a gate insulating film 15, an active layer 17, and a source electrode provided at the intersection of the gate wiring 13 and the data wiring 21c and extending vertically from the gate wiring 13; A thin film transistor (T) consisting of a 21a and a drain electrode 21b; A photosensitive photoacryl layer 27 formed on the entire surface of the substrate including the thin film transistor T and exposing the drain electrode 21b; A pixel electrode 29 formed on the photoacrylic layer 27 and electrically connected to the drain electrode 21b; The passivation layer 31 is formed on the pixel electrode 29 and the photoacryl layer 27, and the common electrode 33 is formed on the passivation layer 31.

Here, a transparent pixel electrode 29 having a large area is disposed on the front surface of the pixel area with a space spaced apart from the gate wiring 13 and the data wiring 21c.

In addition, a plurality of rod-shaped common electrodes 33 are disposed on the pixel electrode 29 with the passivation layer 31 interposed therebetween. In this case, the plurality of common electrodes 33 and the pixel electrode 29 are formed of indium tin oxide (ITO), which is a transparent conductive material.

The pixel electrode 29 is electrically connected to the drain electrode 21b through a drain contact hole 27a formed in the photosensitive photoacrylic layer 27.

Further, although not shown in the drawing, the common electrode 33 is electrically connected to the common wiring 13b through a common wiring contact hole (not shown). In this case, the common wiring contact hole (not shown) is formed in the passivation layer 31, the photoacryl layer 27, and the lower passivation layer 25 formed under the passivation layer 31.

Although not shown in the drawings, a color filter layer (not shown) and a color filter layer are disposed on a color filter substrate (not shown) that is spaced apart and bonded to the insulating substrate 11 on which the pixel electrode 29 and the plurality of common electrodes 33 are formed. The black matrix BM is disposed between the color filter layers (not shown) to block light transmission.

A liquid crystal layer (not shown) is formed between the color filter substrate (not shown) and the insulating substrate 11.

 As described above, according to the FSF type liquid crystal display device according to the prior art, since the recent demand for smartbook products of high resolution and low power consumption while reducing the weight of the slim, due to the flow of the market High resolution and low power consumption products have been proposed, along with the reduction of parasitic capacitances using an acryl layer.

However, according to the related art, a photoacrylic layer is used to reduce parasitic capacitance. In this case, a drain contact hole 27a must be formed in the photoacryl layer to connect the pixel electrode and the drain electrode of the thin film transistor, and the drain contact When the hole 27a is formed, light leakage occurs due to the occurrence of a liquid crystal disclination region around the drain contact hole.

Therefore, according to the related art, in order to block light leakage caused by the occurrence of the liquid crystal disclination region around the drain contact hole, the black matrix BM must be masked to reduce the transmittance.

Particularly, according to the related art, as shown in FIG. 2, the adhesion margin is increased by the distance d1 in the black matrix BM to block light leakage caused by the declining region of the liquid crystal generated by the drain contact hole 27a. Since the transmission area of the pixel is reduced accordingly, the transmittance is lowered.

Accordingly, the present invention is to improve the above problems, an object of the present invention is to implement a low power consumption by reducing the parasitic capacitance in the Advanced High In Plane Switching (AH-IPS) type liquid crystal display device, The present invention provides an Advanced High In Plane Switching (AH-IPS) type liquid crystal display device capable of improving transmittance and a method of manufacturing the same.

According to an aspect of the present invention, an array substrate for an AH-IPS type liquid crystal display device includes: a gate wiring formed on one surface of a substrate in one direction; A data line crossing the gate line to define a pixel area; A thin film transistor formed at a point of intersection of the gate line and the data line; A pixel electrode formed in the pixel region of the substrate and directly connected to the thin film transistor; A photosensitive organic insulating layer formed on the thin film transistor and the data line; A protective film formed on the photosensitive organic insulating film; And a plurality of common electrodes formed on the passivation layer and spaced apart from each other.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for an AH-IPS type liquid crystal display device, comprising: forming a gate wiring on one surface of a substrate in one direction; Forming a thin film transistor at the intersection of the data line defining the pixel area crossing the gate line and the gate line and the data line; Forming a pixel electrode directly connected to the thin film transistor in a pixel region of the substrate; Forming a photosensitive organic insulating layer on the thin film transistor and the data line; Forming a protective film on the photosensitive organic insulating film; And forming a plurality of common electrodes spaced apart from each other on the passivation layer.

According to the H-IPS array substrate and the manufacturing method thereof according to the present invention has the following effects.

 According to the array substrate for AH-IPS type liquid crystal display device according to the present invention and a manufacturing method thereof, power consumption is reduced by using a photosensitive photo acryl layer which is used to reduce the parasitic capacitance. By eliminating the drain contact hole formed to connect the existing drain electrode and the pixel electrode, by directly connecting the drain electrode and the pixel electrode, eliminating the portion where the transmittance is reduced due to the existing drain contact hole formation. This can increase the transmittance by about 10% or more.

In addition, according to the AH-IPS array substrate and a method of manufacturing the same according to the present invention, by leaving the photosensitive layer (Photo Acryl) on the gate wiring and the data wiring, the parasitic Capacitance can be reduced.

In addition, according to the array substrate for AH-IPS type liquid crystal display device according to the present invention and a method of manufacturing the same, the photoacryl layer is not formed in the pixel area, whereby a portion having a lower transmittance can be prevented. Can be.

1 is a schematic plan view of a FFS (Fringe Field Switching) type liquid crystal display device according to the prior art.
FIG. 2 is an enlarged plan view of part “A” of FIG. 1 and schematically illustrates a black matrix (BM) that covers a drain contact hole in consideration of a bonding margin.
FIG. 3 is a cross-sectional view taken along line III-III of FIG. 1 and is a schematic cross-sectional view of a FFS (Fringe Field Switching) type liquid crystal display device.
4 is a schematic plan view of an AH-IPS type liquid crystal display device according to the present invention.
FIG. 5 is an enlarged plan view of the portion “B” of FIG. 4 and schematically illustrates a black matrix BM covering the contact portions of the drain electrode and the pixel electrode in consideration of the bonding margin.
FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 4, and is a schematic cross-sectional view of an AH-IPS type liquid crystal display device.
7A to 7U are cross-sectional views illustrating a manufacturing process of an array substrate for an AH-IPS type liquid crystal display device according to the present invention.

Hereinafter, an array substrate for an AH-IPS type liquid crystal display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a schematic plan view of an AH-IPS type liquid crystal display device according to the present invention.

FIG. 5 is an enlarged plan view of the portion “B” of FIG. 4 and schematically illustrates a black matrix BM covering the contact portions of the drain electrode and the pixel electrode in consideration of the bonding margin.

FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 4, and is a schematic cross-sectional view of an AH-IPS type liquid crystal display device.

The array substrate for an AH-IPS type liquid crystal display device according to the present invention includes a gate wiring 103a formed on one surface of the insulating substrate 101 in one direction, as shown in FIGS. 4 to 6. ; A data line 115c crossing the gate line 103a to define a pixel area; A thin film transistor (T) formed at the intersection of the gate wiring (103a) and the data wiring (115c); A pixel electrode 121a formed in the pixel region of the substrate and directly connected to the thin film transistor T; A photosensitive organic insulating film 127a formed on the thin film transistor T, the data wiring 115 and the gate wiring 103a; A protective film 129 formed on the photosensitive organic insulating film 127a; And a plurality of common electrodes 131a formed on the passivation layer 129 and spaced apart from each other.

Here, a transparent pixel electrode 121a having a large area is disposed on the front surface of the pixel area with a space spaced apart from the gate line 103a and the data line 115c, and a gate insulating layer on the pixel electrode 121a. A plurality of rod-shaped transparent common electrodes 131a are disposed to be spaced apart from each other by a predetermined distance with the inter-layer 107, the lower passivation layer 125, the photosensitive organic insulation layer 127a, and the upper passivation layer 129 interposed therebetween. In this case, the plurality of common electrodes 131a are electrically connected to the common wiring 103c spaced in parallel with the gate wiring 103a.

In addition, the pixel electrode 121a is electrically connected directly to the drain electrode 115b without a separate drain contact hole.

The photosensitive organic insulating layer 127a is formed only on the data line 115c and the gate line 103a including the thin film transistor T and is not formed in the pixel region.

Although not shown in the drawings, a color filter layer (not shown) and a color filter layer may be disposed on a color filter substrate (not shown) spaced apart from and bonded to the insulating substrate 101 on which the pixel electrode 121a and the plurality of common electrodes 131a are formed. The black matrix BM is disposed between the color filter layers (not shown) to block light transmission. In this case, as shown in FIG. 5, the black matrix BM is spaced apart by the distance d2 in consideration of the bonding margin with the insulating substrate 101. Here, the interval d2 between the drain electrode 115b and the black matrix BM is shorter than the interval d1 between the existing drain electrode and the black matrix BM. In this case, since the area of the pixel region covered by the black matrix BM in consideration of the bonding margin in the case of the present invention is smaller than before, the decrease in transmittance is prevented.

A liquid crystal layer (not shown) is formed between the color filter substrate (not shown) and the insulating substrate 101 to form an AH-IPS type liquid crystal display device according to the present invention.

Through the above configuration, the large area common electrode 131a supplies a reference voltage for driving the liquid crystal, that is, a common voltage to each pixel.

The plurality of common electrodes 131a overlap the pixel electrode 121a with a lower passivation layer 125 and an upper passivation layer 129 interposed therebetween to form a fringe field.

In this manner, when a data signal is supplied to the pixel electrode 121a through the thin film transistor T, the common electrode 131a supplied with the common voltage forms a fringe field to form a fringe field. As the liquid crystal molecules arranged in the horizontal direction between the filter substrates (not shown) are rotated by dielectric anisotropy, the light transmittance of the liquid crystal molecules passing through the pixel region is changed according to the degree of rotation, thereby realizing gradation.

Therefore, according to the AH-IPS type liquid crystal display device according to the present invention having the above configuration, the power consumption is reduced by using the photosensitive photo acryl layer used to reduce the existing parasitic capacitance as it is. do.

In addition, by directly connecting the drain electrode 115b and the pixel electrode 121a by omitting the drain contact hole formed to connect the existing drain electrode and the pixel electrode, the transmittance is reduced due to the existing drain contact hole. The part is removed, thereby increasing the transmittance.

The photoacryl layer is left in the upper portion of the gate wiring and the data wiring without forming a photoacryl layer in the pixel region, thereby reducing a parasitic capacitance and preventing a decrease in transmittance.

A method of manufacturing an array substrate for an AH-IPS type liquid crystal display device according to the present invention having the above configuration will be described with reference to FIGS. 7A to 7U.

7A to 7U are cross-sectional views illustrating a manufacturing process of an array substrate for an AH-IPS type liquid crystal display device according to the present invention.

As shown in FIG. 7A, a plurality of pixel regions including a switching region are defined on the transparent insulating substrate 101, and the first conductive metal layer 103 is sputtered on the transparent insulating substrate 101. Deposit. In this case, as the first conductive metal layer 103, aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten (MoW), molybdenum At least one selected from the group of conductive metals, including titanium (MoTi), copper / mortitanium (Cu / MoTi), is used.

Next, a photoresist having high transmittance is coated on the first conductive metal layer 103 to form a first photoresist layer 105.

Subsequently, as illustrated in FIG. 7B, an exposure process is performed on the first photoresist film 105 using a photolithography process technique using an exposure mask (not shown), and then the first photoresist film 105 is subjected to a development process. It is selectively removed to form the first photoresist pattern 105a.

Next, as shown in FIG. 7C, the first conductive metal layer 103 is selectively etched using the first photoresist layer pattern 105a as a blocking layer, and the gate wiring 103a (see FIG. 4) and the gate wiring ( The gate electrode 103b extending from 103a and the common wiring 103c spaced apart from the gate wiring 103a are simultaneously formed.

Subsequently, as shown in FIG. 7D, after the first photoresist layer pattern 105a is removed, the gate insulating layer (SiNx) or silicon oxide layer (SiO ₂ ) is formed on the entire surface of the substrate including the gate electrode 103b. 107 is formed, and an amorphous silicon layer (a-Si: H) 109 and an amorphous silicon layer (n + or p +) 111 containing impurities are sequentially stacked on the gate insulating layer 107. In this case, the amorphous silicon layer (a-Si: H) 109 and the amorphous silicon layer (n + or p +) 111 containing impurities are deposited by a chemical vapor deposition method (CVD).

Next, a second photosensitive layer 113 is formed by applying a photo-resist having high transmittance on the amorphous silicon layer 111 including the impurity.

Subsequently, as shown in FIG. 7E, an exposure process is performed on the second photoresist layer 113 through a photolithography process technique using an exposure mask (not shown), and then the second photoresist layer 113 is subjected to a developing process. It selectively removes to form a second photoresist pattern 113a.

Subsequently, as shown in FIG. 7F, the amorphous silicon layer 111 and the amorphous silicon layer 109 including the impurities are selectively etched using the second photoresist layer pattern 113a as a blocking layer to form an ohmic contact layer ( 111a and active layer 109a are formed.

Subsequently, as shown in FIG. 7G, after the second photoresist layer pattern 113a is removed, the second conductive layer 115 is deposited on the entire surface of the substrate including the ohmic contact layer 111a by a sputtering method. In this case, as the second conductive metal layer 115, aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten (MoW), molybdenum At least one selected from the group of conductive metals including titanium (MoTi) and copper / mortium (Cu / MoTi) is used.

 Subsequently, a third photoresist layer 117 is formed by applying a photo-resist having high transmittance on the second conductive metal layer 115.

Next, an exposure process is performed on the third photosensitive film 117 by using a diffraction mask 119 or a half-tone mask including a light blocking part 119a, a transflective part 119b, and a transmission part 119c. Proceed. At this time, the semi-transmissive portion 119b is provided with a diffraction pattern (not shown) in the diffraction mask 119, the light transmitted through the diffraction pattern is made of a structure so that the amount of light can be reduced by the diffraction phenomenon. . In addition, the semi-transmissive portion 119b is formed with a halftone material in which the amount of light is halved and transmitted through the halftone mask (not shown).

The second photosensitive film 117 at the portion corresponding to the semi-transmissive portion 119b is semi-exposed by the diffraction mask 119 or the half-tone mask including the semi-transmissive portion 119b so that only a partial thickness remains. do. Here, by adjusting the numerical value or the halftone degree of the diffraction pattern of the semi-transmissive portion 119b, it remains after exposure and development of the transparent third photosensitive film 117 when the diffraction mask 119 or the halftone mask is used. You can adjust the thickness.

In addition, the light blocking portion 119a of the diffraction mask 119 is positioned above the third photoresist layer 117 corresponding to the source and drain electrode forming regions, and the transflective portion 119b of the diffraction mask 119 is formed. The second photoresist layer 117 is positioned above the channel formation region of the thin film transistor.

 Subsequently, as shown in FIG. 7H, after the exposure process, the third photoresist layer 117 is selectively removed through the developing process, so that the source and drain electrode forming regions 117a and the channel forming regions 117b are removed. Form. At this time, since the source and drain electrode forming region 117a is not transmitted through the light, the thickness of the third photoresist layer 117 is maintained as it is, but the channel forming region 117b is partially transmitted to a predetermined thickness. Removed. That is, the channel forming region 117b has a thickness thinner than that of the source and drain electrode forming region 117a. At this time, the portion of the third photoresist layer 117 in the data line formation region does not transmit light.

Next, as shown in FIG. 7I, the second conductive metal layer 115 is selectively etched using the source and drain electrode formation region 117a and the channel formation region 117b as a mask. In this case, when the second conductive metal layer 115 is etched, the data line 115c is also formed at the same time.

Subsequently, as shown in FIG. 7J, the channel forming region 117b is completely removed along with a part of the thickness of the source and drain electrode forming region 117a through an ashing process. In this case, an upper surface of the second conductive metal layer 115 overlapping the channel region is exposed to the outside.

Next, as shown in FIG. 7K, the exposed portions of the second conductive metal layer 115 are etched using the source and drain electrode forming regions 119a of the second photoresist film having a portion of the thickness removed as a mask. The spaced source electrode 115a and the drain electrode 115b are formed, respectively.

Subsequently, the ohmic contact layer 111a exposed between the source electrode 115a and the drain electrode 115b is further etched and spaced apart from each other. In this case, a channel region is formed in the active layer 109a under the etched ohmic contact layer 111a.

Next, as shown in FIG. 7L, the source and drain electrode forming regions 119a of the third photoresist layer are completely removed, and then ITO (Indium) is formed on the entire surface of the substrate including the source electrode 115a and the drain electrode 115b. The first transparent conductive material layer 121 is deposited by DC magnetron sputtering using a composition target of any one of a transparent conductive material group including tin oxide) and indium zinc oxide (IZO).

Subsequently, a fourth photoresist layer 123 is formed by applying a photo-resist having high transmittance on the first transparent conductive material layer 121.

Subsequently, as shown in FIG. 7M, an exposure process is performed on the fourth photoresist film 123 through a photolithography process technology using an exposure mask (not shown), and then the fourth photoresist film 123 is developed through a developing process. Is selectively removed to form a fourth photoresist pattern 123a. In this case, the fourth photoresist pattern 123a is covered only on the first transparent conductive material layer 121 positioned in the pixel electrode formation region overlapping a portion of the drain electrode 115b.

Subsequently, as shown in FIG. 7N, the first transparent conductive material layer 121 is selectively etched using the fourth photoresist pattern 123a as a blocking layer to directly contact the drain electrode 115b. Pixel electrode 121a is formed. In this case, the pixel electrode 121a is formed over the entire pixel area. In this case, the pixel electrode 121a is directly connected to the drain electrode 115c on the same layer.

Next, as shown in FIG. 7O, after removing the fourth photoresist pattern 123a, a lower passivation layer 125 made of an inorganic insulating material or an organic insulating material is deposited on the entire surface of the substrate including the pixel electrode 121a. do.

Subsequently, as shown in FIG. 7P, a photoacryl material, which is a photosensitive material, is coated on the lower passivation layer 125 to form a photosensitive organic insulating layer 127. In this case, as the material of the photosensitive organic insulating layer 127, other photosensitive organic insulating materials may be used in addition to the photoacrylic material.

Next, as shown in FIG. 7Q, after performing an exposure process using an exposure mask (not shown), the photosensitive organic insulating layer 127 is selectively removed through a developing process, thereby forming a photosensitive organic layer having an opening 128. The insulating film pattern 127a is formed. In this case, since the organic insulating layer 127 exhibits a photosensitive characteristic, it may be selectively removed through an exposure process without applying a separate photosensitive material. In addition, the opening 128 is formed in an area except the upper portion of the thin film transistor T, the data line 115c and the gate line 103a, and the upper portion of the pixel area. That is, the photosensitive organic insulating layer pattern 127a is formed only on the thin film transistor T, the data line 115c, and the gate line 103a.

Subsequently, as shown in FIG. 7R, an upper protective layer 129 made of an inorganic insulating material or an organic insulating material is deposited on the entire surface of the substrate including the photosensitive organic insulating film pattern 127a.

Next, as illustrated in FIG. 7S, a second transparent layer is formed on the upper passivation layer 129 by using a composition target of any one of a group of transparent conductive materials including indium tin oxide (ITO) and indium zinc oxide (IZO). The conductive material layer 131 is deposited by DC magnetron sputtering.

Subsequently, a fifth photoresist layer 133 is formed by applying a photo-resist having a high transmittance on the second transparent conductive material layer 131.

Subsequently, as shown in FIG. 7T, an exposure process is performed on the fifth photoresist film 133 through a photolithography process technology using an exposure mask (not shown), and then the fifth photoresist film 133 is developed through a development process. Is selectively removed to form a fifth photoresist pattern 133a.

Subsequently, as illustrated in FIG. 7U, the second transparent conductive material layer 131 is selectively etched using the fifth photoresist layer pattern 133a as a blocking layer to overlap the pixel electrode 121a while being spaced apart from each other. The common electrode 131a is formed. In this case, the common electrode electrode 131a is also formed on the thin film transistor T, the gate wiring 103a and the data wiring 115c. In addition, although not illustrated, the plurality of common electrodes 131a and the common wiring 103c may be formed through common wiring contact holes (not shown) formed in the upper passivation layer 129 and the lower passivation layer 125. Electrically connected.

Next, although not shown in the figure, the remaining fifth photoresist pattern 133a is removed, thereby completing the process of manufacturing an array substrate for an AH-IPS type liquid crystal display device according to the present invention.

Subsequently, although not shown in the drawing, a black matrix layer BM is formed on the color filter substrate (not shown) to block light in a portion other than the pixel region, and then a color filter layer is formed in the pixel region.

Thereafter, an alignment film (not shown) is formed on the entire surface of the color filter substrate including the color filter layer (not shown), thereby completing the manufacturing process of the color filter array substrate.

Subsequently, although not shown in the drawings, a process of forming a liquid crystal layer (not shown) between the insulating substrate 101 and the color filter substrate (not shown) is carried out according to the present invention. The process of manufacturing an anti-corrosive liquid crystal display device is completed.

As described above, according to the array substrate for AH-IPS type liquid crystal display device and the method of manufacturing the same, the photosensitive photoacryl layer used to reduce the existing parasitic capacitance is used as it is. By using this method, power consumption can be reduced, and the drain contact hole formed to connect the existing drain electrode and the pixel electrode is omitted, and the drain electrode and the pixel electrode are directly connected to each other. The reduced portion can be eliminated, thereby increasing the transmittance by about 10% or more.

In addition, according to the AH-IPS array substrate and a method of manufacturing the same according to the present invention, by leaving the photosensitive layer (Photo Acryl) on the gate wiring and the data wiring, the parasitic Capacitance can be reduced.

In addition, according to the array substrate for AH-IPS type liquid crystal display device according to the present invention and a method of manufacturing the same, the photoacryl layer is not formed in the pixel area, whereby a portion having a lower transmittance can be prevented. Can be.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

101: insulating substrate 103a: gate wiring
103b: gate electrode 103c: common wiring
107: gate insulating film 109a: active layer
111a: ohmic contact layer 115a: source electrode
115b: drain electrode 115c: data wiring
121a: pixel electrode 125: lower passivation layer
127: organic insulating film 127a: organic insulating film pattern
129: upper passivation layer 131a: common electrode

Claims (10)

A gate wiring formed on one surface of the substrate in one direction;
A data line crossing the gate line to define a pixel area;
A thin film transistor formed at a point of intersection of the gate line and the data line;
A pixel electrode formed in the pixel region of the substrate and directly connected to the thin film transistor;
A photosensitive organic insulating layer formed on the thin film transistor and the data line;
A protective film formed on the photosensitive organic insulating film; And
And a plurality of common electrodes formed on the passivation layer and spaced apart from each other. The array substrate of claim 1, wherein the photosensitive organic insulating layer is formed only on the thin film transistor, the gate wiring, and the data wiring except for the pixel area. The array substrate of claim 1, wherein the photosensitive organic insulating layer is a photo acryl layer. The array substrate of claim 1, wherein the common electrode is formed on the thin film transistor including the pixel region, the gate wiring, and the data wiring. The array substrate of claim 1, wherein the pixel electrode is directly connected to a drain electrode of the thin film transistor on the same layer. Forming a gate wiring in one direction on one surface of a substrate;
Forming a thin film transistor at the intersection of the data line defining the pixel area crossing the gate line and the gate line and the data line;
Forming a pixel electrode directly connected to the thin film transistor in a pixel region of the substrate;
Forming a photosensitive organic insulating layer on the thin film transistor and the data line;
Forming a protective film on the photosensitive organic insulating film; And
Forming a plurality of common electrodes spaced apart from each other on the passivation layer; and a method of manufacturing an array substrate for a liquid crystal display device. The method of claim 6, wherein the photosensitive organic insulating layer is formed only on the thin film transistor, the gate wiring, and the data wiring except for the pixel region. The method of claim 6, wherein the photosensitive organic insulating layer is a photo acryl layer. The method of claim 6, wherein the common electrode is formed on the thin film transistor including the pixel region, the gate wiring, and the data wiring. The method of claim 6, wherein the pixel electrode is directly connected to the drain electrode of the thin film transistor on the same layer.

Images