KR20130015463A - Semiconductor package and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor package and a manufacturing method thereof are provided to prevent the warpage of a molding layer by forming a rewiring layer along the molding layer. CONSTITUTION: A first rewiring layer(131) is electrically connected to a first semiconductor chip. A mold layer surrounds the first semiconductor chip. A second rewiring layer(132) is formed on the upper side of the first semiconductor chip. A mold wiring pattern(133) is formed on the side of the mold layer. The mold wiring pattern electrically connects the first rewiring layer to the second rewiring layer.

Description

Semiconductor package and manufacturing method therefor {SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME}

TECHNICAL FIELD The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a wafer level package having a redistribution layer formed along a molding layer and a method for manufacturing the same.

Recently, due to the miniaturization of electronic portable devices, the size of a semiconductor package is also becoming smaller, thinner, and quantified. In addition, recently, a POP (Package on Package) structure in which two or more different packages are stacked in a single package has been developed. In particular, as portable electronic products demand more and more light weight and small size, the demand for POP type packages is increasing.

While the POP-type package technology can reduce the manufacturing cost of the package by a simple process, and also has advantages such as mass production, wiring space for electrical connection inside the package according to the increase in the number and size of stacked chips. There is a drawback to this lack.

That is, the conventional laminated chip package is manufactured in a structure in which a plurality of chips are laminated and attached to the chip attaching region of the substrate, so as to be electrically connected with the wire between the bonding pad of each chip and the conductive circuit pattern of the substrate. A space for bonding is required, and a circuit pattern area of a substrate to which wires are connected is required, and thus, a size of a semiconductor package is increased.

In view of these shortcomings, a structure using through silicon vias as an example of a stack package has been proposed. Through bumps through the via silicon vias in which a plurality of vertical holes are processed in the chip and embedded with conductive materials in the vertical holes, conductive bumps are formed. In this connection, a method of electrically stacking chips has been proposed.

The method of stacking chips using the through silicon vias can reduce the size of the semiconductor package by eliminating the need for wire bonding. However, the process of forming the through silicon vias and electrically connecting the chips is complicated. There is a need for a simple new method of stacking chips.

Accordingly, the technical problem of the present invention was conceived in this respect, and an object of the present invention is to provide a semiconductor package including a mold wiring pattern.

In addition, another object of the present invention is to provide a method of manufacturing a semiconductor package including a mold wiring pattern.

According to an embodiment of the present invention, a semiconductor package includes a first semiconductor chip, a first redistribution layer electrically connected to the first semiconductor chip, and surrounds the first semiconductor chip. The branch includes a mold layer, a second redistribution layer formed on the first semiconductor chip, and a mold wiring pattern formed on a side surface of the mold layer to electrically connect the first redistribution layer and the second redistribution layer.

In example embodiments, the first semiconductor chip may further include a second semiconductor chip electrically connected to the second redistribution layer.

In example embodiments, the first semiconductor chip and the second semiconductor chip may be disposed to face each other with an inactive surface that does not include bumps.

In one embodiment, the mold layer may be characterized in that it comprises an inclined surface.

In example embodiments, the semiconductor device may further include an insulating layer positioned between the first semiconductor chip and the second semiconductor chip.

In one embodiment, the insulating layer may be characterized in that it comprises an adhesive material on the surface.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor package, the method including: mounting a first semiconductor chip on a carrier, forming a molding member surrounding the first semiconductor chip; Removing, forming a first redistribution layer formed on an active surface of the first semiconductor chip and a first surface of the molding member parallel to the active surface, and a second surface facing the first surface of the molding member. Forming a second redistribution layer on a surface and forming a mold wiring pattern on the side of the molding member, the mold wiring pattern being electrically connected to the first redistribution layer and the second redistribution layer.

According to the structure of the semiconductor package, in the stacking of the upper semiconductor chip, compared to the conventional electrical laminated connection method through the through silicon via and the electrical laminated connection method through the wire bonding, the electrical connection between the chips is easier than the conventional structure. Can be done.

In addition, by forming a redistribution having a relatively small coefficient of thermal expansion according to the grooves formed in the molding layer supporting the semiconductor chip, there is an advantage that the warpage of the molding layer can be prevented to some extent.

1A is a perspective view of a semiconductor package according to an embodiment of the present invention.
FIG. 1B is a cross-sectional view of the semiconductor package taken along the line II ′ of FIG. 1A.
FIG. 1C is a side view illustrating the side surface of the semiconductor package of FIG. 1A.
2 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.
3 is a flowchart illustrating a method of manufacturing a semiconductor package according to another embodiment of the present invention.
4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with the embodiment of FIG. 3.

Hereinafter, with reference to the accompanying drawings will be described in detail a substrate cleaning method and apparatus according to an embodiment of the present invention. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

1A is a perspective view of a semiconductor package according to an embodiment of the present invention. FIG. 1B is a cross-sectional view of the semiconductor package taken along the line II ′ of FIG. 1A. FIG. 1C is a side view illustrating the side surface of the semiconductor package of FIG. 1A.

1A to 1C, a semiconductor package according to an exemplary embodiment may include a first semiconductor chip 110, a mold layer 120, a first redistribution layer 131, a second redistribution layer 132, and a mold. The wiring pattern 133 is included. The first semiconductor chip 110 may be molded in the mold layer 120, and an active surface of the first semiconductor chip 110 may be electrically connected to the first redistribution layer 131. The second redistribution layer 132 is formed on an opposing surface of the mold layer 120 where the first redistribution layer 131 is located, that is, in an upper direction of the first semiconductor chip 110. The second redistribution layer 132 is electrically connected to the first redistribution layer 131 by the mold wiring pattern 133 formed on the side surface 122 of the mold layer 120. An upper semiconductor chip 140 may be mounted on the second redistribution layer 132 to be electrically connected to the second redistribution layer 132. The upper semiconductor chip 140 may be electrically connected not only to the semiconductor chip but also in a form in which the semiconductor chip is packaged. Conventionally, vias were formed in the molding layer 120 through a separate process, and a conductive material was filled in the vias to connect the upper and lower portions. However, in the present embodiment, the side of the molding part is connected to the upper and lower portions. I use it. In addition, the side surface 122 of the molding layer may have a predetermined inclination, thereby making it easier to form a mold wiring pattern.

Referring to FIG. 1A, in the semiconductor package 100 of the present exemplary embodiment, a plurality of mold wiring patterns 133 are formed on side surfaces 122 of the molding layer 120. The mold wiring pattern 133 may be formed as many as necessary for the circuit. Although a plurality of wiring patterns are formed in FIG. 1A, only a few wiring patterns may be formed when the number of wiring patterns required for the semiconductor package is small.

The mold wiring pattern 133 formed on the side surface 122 of the molding layer 120 is electrically connected to a first redistribution layer (not shown) formed at a lower portion thereof and is formed through a second redistribution layer (not shown). It is electrically connected to the upper semiconductor chip 140.

1B and 1C, the first semiconductor chip 110 is electrically connected to the first redistribution layer 131 formed below through a plurality of bumps 113 formed on an active surface. The first redistribution layer 131 is electrically connected to the mold wiring pattern 133 formed on the side surface of the molding layer 120, and the mold wiring pattern 133 is disposed on the first semiconductor chip 110. It is electrically connected to the second redistribution layer 132 formed. The upper semiconductor chip 140 is electrically connected to the upper semiconductor chip 140 through the plurality of bumps 143 formed on the active surface on the second redistribution layer 132.

In order to safer semiconductor packaging, a separate insulating layer 115 may be formed on the first semiconductor chip 110. The insulating layer 115 may be formed between the second redistribution layer 132 and the first semiconductor chip 110, and a pattern of the second redistribution layer 132 may be formed on the insulating layer 115. do. Although the pattern shapes of the first redistribution layer 131 and the second redistribution layer 132 are not specifically illustrated in FIG. 2B, the first and second redistribution layers 131 and 132 may be formed of patterns required for the semiconductor package. It is formed into a shape. A plurality of external connection terminals 150 are formed under the first redistribution layer 131 to serve as a passage for electrically connecting the semiconductor package and the outside.

2 is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

Referring to FIG. 2, the semiconductor package 200 according to the present embodiment includes a first semiconductor chip 211 and a second semiconductor chip 212. The first semiconductor chip 211 and the second semiconductor chip 212 face each other with an inactive surface, and an insulating layer 215 is provided between the first semiconductor chip 211 and the second semiconductor chip 212. Except that formed, the configuration is substantially the same as the semiconductor package of the embodiment shown in FIGS. 1A to 1C.

The first semiconductor chip 211 and the second semiconductor chip 212 are molded by the molding layer 220, and the active surface of the first semiconductor chip 211 is formed through a plurality of bumps 213. The first redistribution layer 231 is electrically connected to the first redistribution layer 231, and is electrically connected to the second redistribution layer 232 through a plurality of bumps 214 on the active surface of the second semiconductor chip 212. The first redistribution layer 231 and the second redistribution layer 232 are electrically connected by a mold wiring pattern 233 formed on the side of the molding layer 22, and the second redistribution layer 232 is Not only the second semiconductor chip 212 but also the upper semiconductor chip 240 may be electrically connected.

3 is a flowchart illustrating a method of manufacturing a semiconductor package according to another embodiment of the present invention.

Referring to FIG. 3, in the method of manufacturing a semiconductor package according to the present exemplary embodiment, a step of mounting a first semiconductor chip on a carrier (S110), forming a molding member surrounding the first semiconductor chip (S120), and forming a carrier Removing (S130), forming a first redistribution layer (S140), forming a second redistribution layer (S150), and forming a mold wiring pattern (S160). A mold wiring pattern electrically connecting the first and second redistribution layers is formed on the side surface of the molding member.

Forming a mold wiring pattern on the side of the molding member is to form a circuit pattern on the inclined surface, it is possible to form in a relatively easy process. In addition, since the mold wiring pattern includes a circuit pattern that is relatively simple as compared with the first or second redistribution layer, the mold wiring pattern may be formed by various methods.

 For example, when the molding member is formed on the side of the molding member, a separate wiring molding part for the mold wiring pattern is formed, and a conductive metal is injected onto the wiring molding part to form the mold wiring pattern. have. Alternatively, the wiring molding part may be formed on a side surface of the molding member through a separate etching process, and a conductive metal may be injected into the wiring molding part.

The mold wiring pattern formed on the side surface of the molding layer electrically connects the first redistribution layer and the second redistribution layer to electrically connect the upper package and the lower package to form a multilayer semiconductor package.

4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with the embodiment of FIG. 3.

Referring to FIG. 4A, a first semiconductor chip 110 including a plurality of bumps 113 is mounted on a carrier 170. The carrier 170 is a dummy panel for simply mounting the first semiconductor chip 110, and no separate electrical coupling is performed. Since the distance between the semiconductor chips 110 is required for the first semiconductor chip 110 to go through a molding process, the first semiconductor chips 110 may be arranged on the carrier 170 by arranging the first semiconductor chips 110 at such intervals. Two semiconductor chips 110 may be mounted to form a molding part in one process.

Referring to FIG. 4B, the molding layer 120 is formed on the first semiconductor chip 110 mounted on the carrier 170. The molding layer 120 is formed to have an inclined side surface 122, and the side surface 122 may be formed in various ways. The molding may be formed to have a side surface of the molding layer 120 itself, and in some cases, an inclined surface may be formed by cutting the side surface of the molding layer 120. The inclined surface of the molding layer 120 may be manufactured to have a sufficiently low slope to facilitate the formation of the mold wiring pattern.

Referring to FIG. 4C, the carrier 170 is removed from the first semiconductor chip 110 and the molding layer 120, and a first redistribution layer is formed on the first and second surfaces of the molding layer 120. 131 and the second redistribution layer 132 are formed. The first surface of the molding layer 120 is a surface sharing the same plane as the active surface of the first semiconductor chip 110, the second surface is a surface facing the first surface.

Referring to FIG. 4D, a mold wiring pattern 133 electrically connecting the first redistribution layer 131 and the second redistribution layer 132 is formed on the side surface 122 of the molding layer 120. In addition, the first redistribution layer 131 forms an external connection member 150 that can exchange signals by making an electrical connection with the outside. The mold wiring pattern 133 may be formed in a relatively simple form compared to the first redistribution layer 131 or the second redistribution layer 132. Therefore, the wiring molding part formed on the side surface 122 of the molding layer 120 may be formed by injecting a conductive metal into the wiring molding part, or the mold wiring pattern may be formed by another easy method.

Referring to FIG. 4E, an upper semiconductor chip 140 is mounted on the second redistribution layer 132. The second redistribution layer 132 is electrically connected to the upper semiconductor chip 140 through a plurality of bumps 143 formed on the upper semiconductor chip 140, and electrically connected to the plurality of bumps 143. Pads connected to each other are included in the second redistribution layer 132, and the second redistribution layer 132 is formed with formation.

As described above, according to the embodiment of the present invention, in stacking the upper semiconductor chip, the chip has a simple structure compared to the conventional electrical laminated connection method through the through-through silicon via and the electrical laminated connection method through wire bonding. The electrical connection between them can be made easily.

In addition, by forming a redistribution having a relatively small coefficient of thermal expansion according to the grooves formed in the molding layer supporting the semiconductor chip, there is an advantage that the warpage of the molding layer can be prevented to some extent.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

100: semiconductor package
110: first semiconductor chip 120: molding layer
131: first redistribution layer 132: second redistribution layer
133 mold wiring pattern 140 upper semiconductor chip
150: external connection member
200: semiconductor package
211: first semiconductor chip 212: second semiconductor chip
220: molding layer 231: first redistribution layer
232: second redistribution layer 233: mold wiring pattern
240: upper semiconductor chip 250: external connection member

Claims (7)

A first semiconductor chip;
A first redistribution layer electrically connected to the first semiconductor chip;
A mold layer formed to surround the first semiconductor chip and having a side surface;
A second redistribution layer formed on the first semiconductor chip; And
And a mold wiring pattern formed on a side of the mold layer to electrically connect the first and second redistribution layers. The method of claim 1,
And a second semiconductor chip electrically connected to the second redistribution layer on the first semiconductor chip. The method of claim 2,
The semiconductor package of claim 1, wherein the first semiconductor chip and the second semiconductor chip are disposed to face each other with an inactive surface including no bumps. The method of claim 1,
The side surface of the mold layer comprises a inclined surface. The method of claim 1,
The semiconductor package according to claim 1, further comprising an insulating layer located between the first semiconductor chip and the second semiconductor chip. The method of claim 5,
The insulating layer is a semiconductor package, characterized in that it comprises an adhesive material on the surface. Mounting a first semiconductor chip on a carrier;
Forming a molding member surrounding the first semiconductor chip;
Removing the carrier;
Forming a first redistribution layer formed on an active surface of the first semiconductor chip and a first surface of the molding member parallel to the active surface;
Forming a second redistribution layer on a second surface facing the first surface of the molding member; And
Forming a mold interconnection pattern electrically connected to the first redistribution layer and the second redistribution layer on a side surface of the molding member.

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