KR20130008274A - Semiconductor memory device and method of operating the same - Google Patents

Abstract

PURPOSE: A semiconductor memory device and an operating method thereof are provided to improve the reliability of data by compensating the change of a threshold voltage of an erase cell due to disturbance. CONSTITUTION: Memory blocks include memory cells connected to bit lines and word lines. Peripheral circuits program memory cells or read data stored in the memory cells. A control circuit(120) controls peripheral circuits to erase memory cells connected to a word line in which is not programmed near a drain selection line from the selected word line after a program is completed in memory cells connected to the selected word line. [Reference numerals] (120) Control circuit; (130) Voltage supply circuit; (140) X decoder; (160) Y decoder; (170) I/O circuit; (180) Counter; (200) External controller; (AA) Signal

Description

Semiconductor memory device and method of operation

The present invention relates to a semiconductor memory device and a method of operating the same.

Recently, there is an increasing demand for semiconductor memory devices that can be electrically programmed and erased and that do not require a refresh function that requires rewriting of data at regular intervals. In order to develop a large-capacity memory device capable of storing more data, a technology for high integration of memory devices has been studied. Accordingly, researches on semiconductor memory devices have been actively conducted.

A multi level cell (MLC) was developed for high integration of semiconductor memory devices. The threshold voltage of a multi-level cell can be changed to one of a plurality of threshold voltage distributions through a program, and different data is set for each threshold voltage distribution. When reading data stored in the multi-level cell, data stored in the multi-level cell can be read by checking the threshold voltage of the multi-level cell.

In addition, a method of increasing the number of memory cells connected to a cell string of a semiconductor memory device for high integration is also used. When the number of memory cells connected to the cell string is increased, when the program is executed, a disturbance or interference problem may occur in which a threshold voltage is changed by an operation of programming a memory cell in the vicinity.

In particular, an erase cell having a threshold voltage of 0 V or less may receive a large pass disturb due to a pass voltage applied to a word line that is not selected during a program or read operation, thereby changing the threshold voltage to 0 V or more.

This pass disturb is increased further during programming of peripheral memory cells connected to the same word line or while programming adjacent memory cells connected to other word lines, and more memory cells connected to word lines adjacent to the drain select line. It is greatly affected.

 When the threshold voltage of the erase cell is changed to 0 V or more due to the pass disturb, normal data reading becomes difficult.

An embodiment of the present invention provides a semiconductor memory device and a method of operating the same, which can compensate for a change in a threshold voltage of an erase cell due to a disturb.

In a semiconductor memory device according to an embodiment of the present invention,

Memory blocks including memory cells connected to word lines and bit lines; Peripheral circuits operative to program data into the memory cells or to read data stored in the memory cells; And after the program for the memory cells connected to the selected word line of the selected memory block is completed, controlling the peripheral circuits to erase the memory cells connected to the non-programmed word line toward the drain select line in the selected word line. It includes a control circuit for.

A semiconductor memory device according to another embodiment of the present invention,

 Memory blocks including memory cells connected to word lines and bit lines; Peripheral circuits operative to program data into the memory cells or to read data stored in the memory cells; And after the erase of the selected memory block is completed, divide the word lines in the selected memory block into at least two word line groups, apply a higher word line voltage to a group closer to the source select line, and erase the wells of the selected memory block. Control circuitry for controlling said peripheral circuitry to effect selective erase to apply a voltage.

A semiconductor memory device according to another embodiment of the present invention,

Memory blocks including memory cells connected to word lines and bit lines; Peripheral circuits operative to program the memory cells or to read data stored in the memory cells; Dividing the word lines in the memory block into at least two groups, and after the last word line of each word line group is programmed, performing an erase operation on the memory cells connected to the unlined word line group. It includes a control circuit for controlling the peripheral circuit.

In another embodiment, a method of operating a semiconductor memory device is provided.

Dividing word lines of the memory block into at least two word line groups; Program and verify memory cells connected to a selected word line of the memory block by a program command; Determining whether the selected word line is the last word line of the word line group after the program and the verification are completed; And if the selected word line corresponds to the last word line of the corresponding word line group, the word word adjacent to the drain selection line in the selected word line and erased for the word lines that are not programmed. An erasing step.

In another embodiment, a method of operating a semiconductor memory device is provided.

Performing hard erase and verification on the memory block selected for erasing; After the hard erase and verify is completed, performing a soft program and verify on the selected memory block; After the soft program and the verification are completed, dividing the word lines of the selected memory block into at least two word line groups; And applying a different voltage to the at least two word line groups and applying an erase voltage to a well of the selected memory block to perform selective erase.

The semiconductor memory device and the method of operating the same according to an embodiment of the present invention compensate for a threshold voltage of a memory cell to be kept in an erased state above 0 V due to a disturbance, thereby increasing reliability of data programmed into the memory cell. Can be.

1 is a block diagram of a semiconductor memory device for explaining the present invention.
2 illustrates threshold voltage distributions of memory cells when the memory cells of FIG. 1 are programmed.
3A illustrates a word line group of a memory block for performing an erase operation after a program according to a first embodiment of the present invention.
3B is a flowchart illustrating a program and erase operation according to a first embodiment of the present invention.
4 is a flowchart illustrating a method of selectively erasing a memory block according to a second embodiment of the present invention.
FIG. 5 illustrates a voltage applied to a word line group during selective erasing of FIG. 4.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 is a block diagram of a semiconductor memory device for explaining the present invention.

Referring to FIG. 1, the semiconductor memory device 100 includes an operation circuit group 130, 140, and 150 configured to perform a program operation or a read operation of the memory cell array 110 and the memory cells included in the memory cell array 110. 160, 170, and a control circuit 120 configured to control the operation circuit group 130, 140, 150, 160, 170 to set an optimal read voltage at which the error bit is minimized during the data read operation. Include. In addition, the semiconductor memory device 100 is connected to an external controller 200 for inputting a command, an address, data, and the like.

The operation circuit group includes a voltage supply circuit 130, an X decoder 140, a page buffer group 150, a Y decoder 160, and an input / output (I / O) circuit 170.

The memory cell array 110 includes a plurality of memory blocks. One memory block is shown in FIG. 1. Each memory block includes a plurality of strings ST0 to STk. Each string ST1 includes a source select transistor SST connected to a common source line CSL, a plurality of memory cells Ca0 to Can, and a drain select transistor DST connected to a bit line BL1. do. The gate of the source select transistor SST is connected to the source select line SSL, the gates of the memory cells Ca0 to Can are respectively connected to the word lines WL0 to WLn, and the gate of the drain select transistor DST. Is connected to the drain select line DSL. The strings ST1 to STk are respectively connected to the corresponding bit lines BL1 to BLk and commonly connected to the common source line CSL.

Each memory block may be divided into physical page units or logical page units. Pages (or even pages and odd pages) become basic units of a program operation or a read operation.

For example, memory cells Ca0 to Ck0 connected to one word line (eg, WL0) constitute one physical page. Also, even-numbered memory cells Ca0, Cc0, ..., Ck-10 connected to one word line (eg, WL0) constitute one even physical page, and odd-numbered memory cells Cb0, Cd0,. .., Ck0) may constitute a single physical page.

The control circuit 120 internally outputs the program operation signal PGM, the read operation signal READ or the erase operation signal ERASE in response to the command signal CMD input from the external controller 200, and According to the type, control signals PS SIGNALS for controlling the page buffers included in the page buffer group 150 are output. In addition, the control circuit 120 internally outputs the row address signal RADD and the column address signal CADD in response to the address signal ADD.

The voltage supply circuit 130 may include operating voltages (eg, Vpgm, for programming, reading, or erasing memory cells in response to operation signals PGM, READ, and ERASE, which are internal command signals of the control circuit 120). Vpass, R1, new_R1, etc.) are output as global lines, and when programming memory cells, operating voltages for programming are output as global lines.

At this time, the voltage supply circuit 130 changes and outputs the voltage levels of the operating voltages in response to the voltage control signal input from the control circuit 120.

In response to the row address signals RADD of the control circuit 120, the X decoder 140 may generate operating voltages output from the voltage supply circuit 130 of the selected memory block of the memory blocks of the memory cell array 110. Transfer to local lines DSL, WL0 to WLn, SSL.

The page buffer group 150 includes page buffers (not shown) connected to the bit lines BL1 to BLk, respectively. In response to the control signals PB SIGNALS of the control circuit 120, voltages necessary for storing data in the cells Ca0,..., Ck0 are applied to the bit lines BL1 to BL4, respectively. In detail, the page buffer group 150 may precharge the bit lines BL1 to BLk or may precharge the bit lines BL1 to BLk during the program operation, the erase operation, or the read operation of the cells Ca0,..., Ck0. Latches data corresponding to the threshold voltage levels of the detected memory cells Ca0,..., Ck0 according to the change in voltage. That is, the page buffer group 150 adjusts the voltages of the bit lines BL1 through BLk according to data stored in the memory cells Ca0,..., Ck0, and controls the memory cells Ca0,..., Ck0. Detects data stored in).

The Y decoder 160 selects the page buffers included in the page buffer group 150 in response to the column address signal CADD output from the control circuit 120. The latched data of the page buffer selected by the Y decoder 160 is output.

The I / O circuit 170 transfers data to the Y decoder 160 according to the control of the control circuit 120 to input data input from the outside into the page buffer group 150 during the program operation. When the Y decoder 160 sequentially transfers the transferred data to the page buffers of the page buffer group 150, the page buffers store the input data in an internal latch. In addition, in the read operation, the I / O circuit 170 outputs data transmitted through the Y decoder 160 from the page buffers of the page buffer group 150 to the outside.

After performing the program operation, the control circuit 120 controls the above operation circuit groups to erase the memory cells toward the drain select line.

On the other hand, when using the memory cells of the memory cell array 120 as a multi-level cell (Multi Level Cell), the threshold voltage of the memory cells as shown in the following distribution as the program is executed.

2 illustrates threshold voltage distributions of memory cells when the memory cells of FIG. 1 are programmed.

Referring to FIG. 2, when a program of memory cells is implemented, a threshold voltage of a memory cell is included in one of four threshold voltage distributions according to data stored in each memory cell.

For the following description, a memory cell having a threshold voltage of 0 V or less is called an erase cell, a memory cell having a threshold voltage of more than voltage PV1 and less than or equal to voltage PV2 is referred to as a PV1 cell, and a threshold voltage is greater than or equal to voltage PV2. A memory cell having a voltage of less than or equal to the voltage PV3 is referred to as a PV2 cell, and a memory cell having a threshold voltage greater than or equal to the voltage PV3 is referred to as a PV3 cell.

In FIG. 2, the erase cells may have a high threshold voltage due to a disturb caused by a program of peripheral memory cells. In particular, the closer the memory cell is to the drain select line, the greater the influence of the disturb.

Therefore, in the embodiment of the present invention, the memory cells must be erased so that the threshold voltage change due to the disturbance can be compensated.

The erasing of the memory cells for changing the threshold voltage may be performed in two ways.

First, when a word line is selected in order from the word line adjacent to the source select line of the selected memory block to the drain select line, the word lines on the drain select line are still not included in the program line. It is in a state not implemented. In this case, the word line is erased for the word lines which have not been programmed yet. As described above, the word line adjacent to the drain select line is more affected by the disturb. Therefore, the erase operation is performed to compensate for the disturb effect of the word lines on the drain select line.

Second, when the memory block is erased, the word line adjacent to the drain select line causes more erase.

The above method will be described in more detail as follows.

3A illustrates a word line group of a memory block for performing a post-program erase operation according to a first embodiment of the present invention, and FIG. 3B illustrates an operation for describing a program and erase operation according to a first embodiment of the present invention. Flowchart.

FIG. 3A illustrates dividing word lines of a memory block including the 0 th through 63 th word lines WL0 through WL63 into first through fourth groups.

The first group includes the 0 to 15th word lines WL0 to WL15, the second group includes the 16th to 31st wordlines WL16 to WL31, and the third group includes the 32nd to 47th words Lines WL32 to WL47 are included. The fourth group includes 48th to 63rd word lines WL48 to WL63.

The program proceeds from the 0th word line WL0 to the 63rd word line WL63. The zeroth word line WL0 is adjacent to the source select line, and the 63rd word line WL63 is adjacent to the drain select line.

Program and erase operations for each word line of the memory blocks divided into groups as shown in FIG. 3A are performed as shown in FIG. 3B.

Referring to FIG. 3B, first, word lines are divided into groups for each memory block (S301). The group of word lines is divided into at least two, each group consisting of adjacent word lines.

When a program command, an address, and data to be programmed are input (S303, S305), and a program check command (S307) is input, the program and verification for the word line selected by the address input in step S303 is performed (S309). .

Since the program operations in steps S303 to S309 are the same as the program operations already known, detailed description thereof will be omitted.

After the program of step S309 is completed, it is checked whether the selected word line that has completed the program is the last word line of the memory block, that is, the 63rd word line WL63 (S311).

If the selected word line is the last word line of the memory block, the program operation for the memory block is terminated. After the erase command is input to the memory block and the erase operation is performed, the program operation as shown in FIG. 3B may be performed again.

On the other hand, if it is determined in step S311 that the selected word line is not the last word line of the memory block, it is checked whether the selected word line corresponds to the last word line of each group (S311).

That is, it is checked whether the selected word line is one of the fifteenth, thirty-first, or forty-seventh word lines WL15, WL31, and WL47. As described above, since the 63rd word line WL63 corresponds to the last word line of the memory block, it is not necessary to confirm whether the 63rd word line WL63 corresponds to the last word line of the group.

If the selected word line is one of the fifteenth, thirty-first, or forty-seventh word lines WL15, WL31, and WL47, selective erase of word lines adjacent to the drain selection line is performed in the selected word line (S315). ).

The erase of the step S315 uses a well erase method. The well erase method is a method of changing a threshold voltage of a memory cell below 0V by applying a high voltage for erasing to a well of a memory block.

When the above well erasing is performed, memory cells connected to the word line in which the program operation has been previously completed should not be erased.

To do this, the word line in which the program is processed is floated and 0 V is applied to the word lines to be erased. When the erase voltage is applied to the well, the memory cells in which the word line is floated are not erased due to the boosting effect, and the memory cells in which 0 V is applied to the word line are erased.

For example, if the program and the verification are performed on the fifteenth word line WL15 at step S309, selective erasure is performed on the sixteenth to 63rd word lines WL16 to WL63. For this purpose, the 0 th to 15 th word lines WL15 are floated, and 0 V is applied to the 16 th to 63rd word lines WL16 to WL63.

When the erase voltage having the high voltage level is applied to the well of the memory block, the memory cells connected to the sixteenth through sixty-third word lines WL16 through WL63 are erased.

If the word line subjected to the program and verification in step S309 is the thirty first word line WL31, selective erasing of the thirty-second to sixty-third word lines WL32 to WL63 is performed.

In addition, if the word line that has been programmed and verified in step S309 is the forty-seventh word line WL47, selective erasing for the forty-eighth to sixty-third word lines WL48 to WL63 is performed.

By the above operation, the group of word lines adjacent to the drain select line performs more selective erase. That is, the erase is further performed on the word line group affected by the disturb, so that the threshold voltages of the erase cells become 0V or less.

After step S315, it is determined whether a new program command is input (S317). When a new program command is input, the operations from step S303 to step S315 are repeated. If a new program command is not input in step S317, it is kept in a standby state until a new program command is continuously input.

In addition to performing the partial erasing as described above, in another exemplary embodiment, the word line group adjacent to the drain select line may be erased more than other word line groups in order to reduce the influence of the disturb.

4 is a flowchart illustrating a method of selectively erasing a memory block according to a second embodiment of the present invention.

Referring to FIG. 4, when an erase command is input (S401), the control circuit 120 performs hard erase and verification on the memory block BK selected by the erase command (S403).

By hard erasing and verifying, the threshold voltage of all the memory cells of the memory block BK is 0V or less.

After hard erase of the memory block BK, a soft program and verification are performed to bring the threshold voltages of the memory cells closer to 0V (S405).

Since the hard erase and verify and soft program and verify operations performed in steps S403 and S405 are performed in an erase operation of a general memory block, a detailed description thereof will be omitted.

After the soft program and verification are completed, the word lines of the selected memory block BK are divided into two or more groups (S407).

In the embodiment of the present invention, it is assumed that word lines are divided into first to fourth groups as shown in FIG. 3A.

After dividing word lines into first to fourth groups, selective erasure is performed for each group (S409).

The selective erasing of step S409 controls the degree to which the memory cells of each group are erased by applying different voltages to the word lines of each group and then applying a high voltage to the wells.

Subsequently, when a program command is input to word lines of the memory block in which the degree of erasure is adjusted, the program is executed in the same manner as in a general program method. Since each word line is erased according to its position in the erase operation, subsequent program operations may reduce the effects of program disturb that are different for each word line even when using a general program method.

On the other hand, when performing selective erasing, the voltage applied to each group can be set as follows.

FIG. 5 illustrates a voltage applied to a word line group during selective erasing of FIG. 4.

Referring to FIG. 5, 1.5V is applied to word lines of a first group and 1V is applied to word lines of a second group. 0.5V is applied to the word lines of the third group, and 0V is applied to the word lines of the fourth group.

The first group is closer to the source select line and closer to the fourth group is closer to the drain select line. In other words, the fourth group is most affected by the disturbance, and the smaller the disturbance is, the closer to the first group.

When the erase is performed, the larger the difference between the erase voltage applied to the well and the voltage applied to the gate of the memory cell, the larger the erase.

That is, since the fourth group is closest to the drain select line, 0V is applied to be the most erased, and the first group is farthest from the drain select line, so 1.5V is applied to the smallest.

By the selective erasing, the threshold voltages of the memory cells connected to the fourth group of word lines have lower threshold voltages than the memory cells connected to the other group of word lines. In addition, even if the threshold voltage increases due to the disturbance during the program, the probability of raising the voltage to 0V or more decreases.

A memory block that has been selectively erased as shown in FIG. 5 does not need to be erased while the program is progressing as shown in FIG. 3B.

On the other hand, the verification for the selective erasure can be selectively performed. In addition, the operation of lowering the threshold voltage may be performed by performing a voltage application as shown in FIG. 5 without performing verification separately.

When the selective erasing is performed, the threshold voltage of the memory cell adjacent to the drain select line, which is relatively affected by the disturbance, is lower than 0V, so the probability that the threshold voltage is changed by the disturbance is lower than 0V.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

100 semiconductor device 110 memory cell array
120: control circuit 130: voltage supply circuit
140: X decoder 150: page buffer group
160: Y decoder 170: I / O circuit

Claims (10)

Memory blocks including memory cells connected to word lines and bit lines;
Peripheral circuits operative to program the memory cells or to read data stored in the memory cells; And
A control circuit for controlling the peripheral circuits so that after the programming of the memory cells connected to the selected word line is completed, the memory cells connected to the non-programmed word line adjacent to the drain selection line in the selected word line are erased. A semiconductor memory device. The method of claim 1,
The control circuit is configured to erase the memory cells adjacent to the drain select line in the selected word line and connected to an unprogrammed word line.
Including the selected word line, a word line adjacent to a source select line is floated, a ground voltage is applied to a word line adjacent to a drain select line in the selected word line, and then to a well of a memory block including the selected word line. And controlling the peripheral circuit to apply an erase voltage. The method of claim 2,
The control circuit,
Dividing the word lines in the memory block including the selected word line into at least two groups, and after the last word line of each word line group is programmed, the erasing is performed on the group of unprogrammed word lines. A semiconductor memory device, characterized in that for controlling a peripheral circuit. Memory blocks including memory cells connected to word lines and bit lines;
Peripheral circuits operative to program the memory cells or to read data stored in the memory cells; And
After the erase operation on the selected memory block is completed, divide the word lines in the selected memory block into at least two word line groups, apply a higher word line voltage to a group closer to the source select line, and erase the wells of the selected memory block. And a control circuit for controlling the peripheral circuit to perform selective erasure of applying a voltage. Memory blocks including memory cells connected to word lines and bit lines;
Peripheral circuits operative to program the memory cells or to read data stored in the memory cells; And
Dividing the word lines in the memory block into at least two groups, and after the last word line of each word line group has been programmed, the periphery to perform an erase operation on memory cells connected to an unprogrammed word line group. A semiconductor memory device comprising a control circuit for controlling the circuit. 6. The method of claim 5,
The control circuit erases the memory cells connected to the word line group in which the program is not implemented.
Applying the ground voltage to the word line group where the program is not implemented, plotting the remaining word line groups except the word line group where the program is not implemented, and applying the erase circuit to the well of the memory block. And controlling the semiconductor memory device. Dividing word lines of the memory block into at least two word line groups;
Program and verify memory cells connected to a selected word line of the memory block by a program command;
Determining whether the selected word line is the last word line of the word line group after the program and the verification are completed; And
If the selected word line corresponds to the last word line of the corresponding word line group, the selective word line adjacent to the drain selection line in the selected word line and erased for the word lines not programmed are performed. A method of operating a semiconductor memory device comprising the step. 8. The method of claim 7,
The selective erasing step,
Applying a ground voltage to word lines adjacent to the drain select line in the selected word line and not programmed, floating the remaining word lines, and then applying an erase voltage to the well of the memory block. A method of operating a semiconductor memory device. Performing hard erase and verification on the memory block selected for erasing;
After the hard erase and verify is completed, performing a soft program and verify on the selected memory block;
After the soft program and the verification are completed, dividing the word lines of the selected memory block into at least two word line groups;
And applying a different voltage to the at least two word line groups and applying an erase voltage to a well of the selected memory block to perform selective erasure. The method of claim 9,
In the selective erasing, different voltages are applied to the at least two word line groups, but ground voltages are applied to the word line group closest to the drain select line. And applying an erase voltage to a well of the selected memory block after applying a voltage higher than the voltage.

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