KR20130005433A - Method for manufacturing 3d structured non-volatile memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing 3D structured non-volatile memory device is provided to easily drive a memory cell by using two control gate electrodes. CONSTITUTION: Multiple first interlayer insulating film(21) are formed on a substrate(20). Multiple first conductive films(25) are formed on the substrate. A recess process is performed on the first interlayer insulating films. A charge barrier film is formed in the recessed first interlayer insulating films. A second conductive film is formed along the inner surface of a first trench(T1).

Description

METHODS FOR MANUFACTURING 3D STRUCTURED NON-VOLATILE MEMORY DEVICE

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a nonvolatile memory device having a three-dimensional structure.

A non-volatile memory device is a memory device in which stored data is retained even if power supply is interrupted. Recently, as the degree of integration of a memory device having a two-dimensional structure that manufactures a memory device in a single layer on a silicon substrate has reached a limit, a non-volatile memory device having a three-dimensional structure in which memory cells are stacked vertically from a silicon substrate has been proposed. .

Hereinafter, a structure and a problem thereof of a nonvolatile memory device having a three-dimensional structure according to the prior art will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a structure and a manufacturing method of a charge trap type nonvolatile memory device having a three-dimensional structure according to the prior art.

As illustrated in FIG. 1, a plurality of interlayer insulating layers 11 and conductive layers 12 are alternately formed on a substrate 10 on which a source region (not shown) is formed, and then etched to form a substrate 10. To form a trench that exposes the surface of the substrate. Subsequently, after the gate insulating film 13 is formed on the inner wall of the trench, the channel film is embedded to form the channel CH. As a result, a lower select trench LST is formed.

Subsequently, a plurality of interlayer insulating layers 14 and a plurality of conductive layers 15 are alternately formed on the resultant formed lower select transistor LST. Here, the number of the interlayer insulating film 14 and the conductive film 15 to be stacked is determined according to the number of memory cells to be stacked.

Subsequently, the plurality of interlayer insulating layers 14 and the plurality of conductive layers 15 are etched to form trenches that expose the channel CH of the lower select transistor LST. Subsequently, the charge blocking film, the charge trap film, and the tunnel insulating film 16 are sequentially formed on the inner wall of the trench, and the channel film is embedded to form the channel CH. Here, the charge trap film is used as a kind of data storage for storing / erasing data by trapping / discharging charges, and is generally made of a nitride film. As a result, a plurality of memory cells MC are formed.

Next, a plurality of interlayer insulating layers 17 and conductive layers 18 are alternately formed on the plurality of memory cells MC, and the trenches are etched to expose the channels CH of the memory cells MC. To form. Subsequently, after the gate insulating film 19 is formed on the inner wall of the trench, the channel film is embedded to form the channel CH. As a result, the top select transistor UST is formed.

Here, the plurality of memory cells MC are connected in series between the lower select transistor LST and the upper select transistor UST to form one string ST, and each channel CH is a bit line BL. Connected with

According to the prior art as described above, it is possible to form a charge trap type nonvolatile memory device having a three-dimensional structure. However, the charge trap type nonvolatile memory device has a problem in that its characteristics are worse than that of the floating gate type nonvolatile memory device which stores data by injecting / emitting charges into the floating gate electrode.

In particular, the charge trapping nonvolatile memory device has a slower program / erase operation and poorer data retention characteristics than the floating gate type nonvolatile memory device. Furthermore, due to the structural characteristics of the nonvolatile memory device having a three-dimensional structure, since the charge trap layers of the plurality of memory cells stacked along the channel are interconnected, there is a problem in that the data retention characteristic is further reduced.

The present invention has been proposed to solve the above problems, and an object thereof is to provide a method of manufacturing a floating gate type nonvolatile memory device having a three-dimensional structure.

In order to achieve the above object, the present invention provides a method of manufacturing a nonvolatile memory device having a three-dimensional structure, comprising: alternately forming a plurality of first interlayer insulating layers and a plurality of first conductive layers on a substrate; Etching the plurality of first interlayer insulating layers and the plurality of first conductive layers to form a plurality of first trenches; Partially recessing the plurality of first interlayer insulating layers exposed on the inner wall of the first trench; Forming a charge blocking film along an inner surface of the first trench in which the plurality of first interlayer insulating films are recessed; Forming a second conductive film along an inner surface of the first trench so as to fill a recess region of the first interlayer insulating film; The plurality of first interlayer insulating layers between the upper inner wall of the plurality of first trenches and the plurality of first trenches to cover the openings of the plurality of first trenches and expose the bottom surfaces of the plurality of first trenches. Forming a buffer film on the plurality of first conductive films; And removing the second conductive layer and the charge blocking layer formed on the bottoms of the plurality of first trenches.

According to the present invention, by providing a floating gate type nonvolatile memory device having a three-dimensional structure, it is possible to improve the performance and reliability of the memory device compared to the conventional charge trapping nonvolatile memory device having a three-dimensional structure. In particular, by including one floating gate electrode and two control gate electrodes in one memory cell, the memory cell may be more easily driven using a low voltage program voltage and an erase voltage. In addition, since the charge blocking film is formed to surround the entire surface of the floating gate electrode, the interference effect can be reduced as compared with the related art.

Further, according to the present invention, since the charge blocking film and the floating gate conductive film on the bottom of the trench are removed after the buffer film covering the opening of the trench is formed, it is possible to prevent the upper floating gate and the charge blocking film from being damaged. Therefore, it is possible to prevent the floating gate formed on the upper portion from being damaged and the coupling ratio of the upper memory cell from decreasing. In addition, the charge blocking layer formed on the upper portion may be damaged to prevent the floating gate and the control gate from being electrically connected to each other.

1 is a cross-sectional view illustrating a structure and a manufacturing method of a charge trap type nonvolatile memory device having a three-dimensional structure according to the prior art.
2A to 2G are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a first embodiment of the present invention.
3 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a second embodiment of the present invention.
4 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a third embodiment of the present invention.

Hereinafter, the most preferred embodiment of the present invention will be described. In the drawings, thicknesses and intervals are expressed for convenience of description and may be shown to be processed compared to actual physical thicknesses. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. It should be noted that, in the case of adding the reference numerals to the constituent elements of the drawings, the same constituent elements have the same number as much as possible even if they are displayed on different drawings.

2A to 2G are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a first embodiment of the present invention.

As shown in FIG. 2A, after forming the first interlayer insulating film 21 on the substrate 20, the pipe gate 22 is formed on the first interlayer insulating film 21. Here, the first interlayer insulating film 21 may be formed of an oxide film, and the pipe gate 22 may be formed of a polysilicon film.

Subsequently, after the pipe gate 22 is etched to form the first trenches T1, the sacrificial layer 23 is embedded in the first trenches T1. Here, the first trenches T1 are for securing the formation region of the pipe channel. The sacrificial layer 23 may be formed of a nitride layer.

Subsequently, a plurality of second interlayer insulating layers 24 and a plurality of first conductive layers 25 are alternately formed on the entire structure of the resultant material in which the sacrificial layer 23 is embedded.

The second interlayer insulating film 24 is to separate the stacked memory cells from each other, and may be formed of an oxide film. Here, the uppermost second interlayer insulating layer 24 may be formed thicker than the lower second interlayer insulating layers 24 to serve as an etch stop layer in a subsequent planarization process. The first conductive layer 25 is formed to form a word line, and may be formed of a polysilicon layer.

As illustrated in FIG. 2B, the plurality of second interlayer insulating layers 24 and the plurality of first conductive layers 25 are etched to form a plurality of second trenches T2. In this case, the pair of second trenches T2 are formed to be connected to one first trench T1.

As illustrated in FIG. 2C, the plurality of second interlayer insulating layers 24 exposed on the inner wall of the second trench T2 are partially recessed to form recesses and protrusions on the inner wall of the second trench T2. In the drawing, the etched second interlayer insulating film is denoted by reference numeral 24A, and the second trench in which the unevenness is formed on the inner wall is denoted by reference numeral T2 '.

Here, the recessed region of the first interlayer insulating layers 24A is a region for forming a floating gate in a subsequent process. Therefore, in consideration of the thickness of the floating gate, the first interlayer dielectric layer 24A is etched, and for example, the first interlayer dielectric layer 24A is etched by 250 to 500 Å by a wet etching process.

As shown in FIG. 2D, the plurality of second interlayer insulating films 24 form a charge blocking film 26 along the entire surface of the resultant recessed portion. The charge blocking layer 26 is to prevent the charge stored in the floating gate from being transferred to the control gate. The charge blocking layer 26 may be formed of a high dielectric constant material or an ONO layer in which an oxide film, a nitride film, and an oxide film are stacked.

Next, the second conductive film 27 is formed along the entire surface of the resultant product in which the charge blocking film 26 is formed. The second conductive film 27 is buried in the recess region of the second interlayer insulating film 24A on which the charge blocking film 26 is formed. The second conductive layer 27 is for forming a floating gate and may be formed of a polysilicon layer. The second conductive film 27 is preferably formed to a thickness of 100 to 500 kPa.

Subsequently, a buffer layer 28 is formed to cover the opening of the second trench T2 'and to expose the bottom surface of the second trench T2'. Here, the buffer layer 28 is used as a kind of protective film in a subsequent front dry etching process, and is formed such that the inside of the second trench T2 'is hollow.

The subsequent dry etching process is to expose the lower sacrificial layer 23 by removing the second conductive layer 27 and the charge blocking layer 26 formed on the bottom of the second trench T2 ′. The second conductive layer 28 and the charge blocking layer 26 formed on the second trench T2 ′ may be damaged. In particular, the protruding edge A of the second conductive layer 28 may be damaged in the entire dry etching process in the region where the opening of the second trench T2 ′ or the uppermost first conductive layer 25 protrudes. high.

Therefore, the buffer layer 28 is formed in the openings of the plurality of second trenches T2 'to cover the corners A of the second conductive layer 27 due to the unevenness of the second trenches T2'. It is preferable that the uppermost of the plurality of first conductive films 25 is formed to a height at which the first conductive film 25 is formed. That is, the buffer layer 28 has a shoulder region of the plurality of second trenches T2 ′, that is, an upper inner wall of the plurality of second trenches T2 ′ and a plurality of second trenches T2. It is preferably formed on the plurality of second interlayer insulating films 24A and the plurality of first conductive films 25 between ').

The buffer layer 28 is preferably formed of a material having poor step coverage due to the nature of the material. For example, the buffer layer 28 may be formed of one of a PE-TEOS film formed by USG (Undoped Silicate Glass), a plasma enhanced method, and an HDP film formed using a silane gas, or a combination thereof. It can be formed as. In addition, the buffer film 28 may be formed to a thickness of 300 to 1000Å.

The buffer film 28 is preferably formed under the condition that the step coverage is 50% or less. That is, it is preferable to form the buffer film 28 under the condition that the amount deposited in the side region is 50% or less compared to the top region. For example, in the plasma type chamber, the buffer film 28 is formed using a fast deposition rate of 400 to 600 ° C. and a pressure of 3 to 5 Torr, thereby forming the upper portion of the second trench T2 ′. Only the buffer film 28 can be formed.

As illustrated in FIG. 2E, the second conductive layer 27 and the charge blocking layer 26 formed on the bottom of the plurality of second trenches T2 ′ are removed by a front dry etching process.

At this time, the charge blocking layer 26 and the second conductive layer 27 formed on the upper inner walls of the plurality of second trenches are protected by the buffer layer 28, and are formed on the bottom surfaces of the plurality of second trenches T2 ′. The second conductive layer 27 and the charge blocking layer 26 are removed. Therefore, it is possible to prevent the charge blocking layer 26 and the second conductive layer 27 formed on the upper inner walls of the plurality of second trenches in the front dry etching process.

In addition, the buffer layer 28 is removed together in the process of removing the second conductive layer 27 and the charge blocking layer 26 formed on the bottom surfaces of the plurality of second trenches T2 ′ by the front dry etching process. do. That is, the buffer layer 28 is etched instead of the second conductive layer 27 and the charge blocking layer 26 formed on the upper inner walls of the plurality of second trenches T2 ′ in the front dry etching process. Therefore, it is not necessary to perform a separate process for removing the buffer layer 28 after the entire dry etching process.

In the drawing, the etched charge blocking film is denoted by reference numeral 26A, and the etched second conductive film is denoted by reference numeral 27A.

As shown in FIG. 2F, the second conductive layer 27A remaining on the inner walls of the plurality of second trenches T2 ′ is etched by a wet etching process to form a recess region of the second interlayer insulating layer 24A. The second conductive film 27A embedded in the film is separated. As a result, a plurality of floating gates 27B stacked on the substrate 20 are formed.

As illustrated in FIG. 2G, after removing the sacrificial layer 23 exposed on the bottom of the pair of second trenches T2 ′, the first trench T1 and the pair of second trenches T2 ′ are removed. A tunnel insulating film 29 is formed on the inner surface of the tunnel. The tunnel insulating layer 29 may be provided as an energy barrier layer for F-N tunneling of charges and may be formed of an oxide layer.

Subsequently, the first channel layer 30 is formed on the entire structure of the resultant structure in which the tunnel insulating layer 29 is formed so that the first trenches T1 and the pair of second trenches T2 'are completely buried. Do this. As a result, a plurality of memory cells stacked on the substrate 20 are formed. Here, one memory cell includes one floating gate 27B and two control gates. That is, the floating gate 27B is controlled by a control gate formed above and below the floating gate 27B. In the drawing, the first conductive film 25 serves as a control gate.

At this time, during the planarization process, the uppermost second interlayer insulating layer 24A may be partially etched. In this drawing, the uppermost second interlayer insulating film etched in the planarization process is denoted by reference numeral 24B.

Next, the third conductive film 31 and the third interlayer insulating film 32 are formed on the entire structure of the resultant flattening process. The third conductive layer 31 may be formed of a polysilicon layer to form a selection line. In addition, the third interlayer insulating film 32 may be formed of an oxide film.

As shown in FIG. 2H, the third interlayer insulating layer 32 and the third conductive layer 31 are etched to form a third trench that exposes the channel layer 30. Subsequently, after the gate insulating layer 33 is formed on the inner wall of the third trench, the second channel layer 34 is formed in the third trench. As a result, a select gate is formed on the plurality of memory cells stacked on the substrate 20.

Subsequently, the third interlayer insulating film 32, the third conductive film 31, the plurality of first conductive films 24A and the plurality of second interlayer insulating films between the pair of second trenches T2 ′ 24A and 24B are etched to form slits separating the source side word line and the drain side word line. Next, the insulating film 35 is embedded in the slit.

In the drawing, the third interlayer insulating film etched in the third trench and slit formation process is denoted by reference numeral 32A, the etched third conductive layer is denoted by reference numeral 31A, and the etched first conductive layer is denoted by reference numeral 24B. ", And the etched second interlayer insulating film is denoted by reference numeral" 24B "or" 24C ".

Subsequently, a source line SL and a bit line BL are formed on the selection gate.

As a result, a nonvolatile memory device having a three-dimensional structure in which one memory cell includes one floating gate electrode and two control gate electrodes is manufactured. As described above, when one memory cell is driven using two control gates, the memory cell may be more easily driven using a low voltage program voltage and an erase voltage. In addition, since the charge blocking film is formed to surround the entire surface of the floating gate electrode, the interference effect can be reduced as compared with the related art.

In addition, by forming a buffer layer on the second trench, the second conductive layer and the charge blocking layer formed on the upper portion of the second trench may be prevented from being damaged during the removal of the second conductive layer and the charge blocking layer on the bottom of the second trench. Can be. Therefore, cell distribution characteristics can be secured by keeping the coupling ratio of the memory device uniform.

3 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a second embodiment of the present invention.

The second embodiment relates to a non-volatile memory device having a three-dimensional structure including a channel of a through type having an open central region, and the configuration other than the channel is the same as described in the first embodiment.

As shown, the first channel layer 36 and the second channel layer 38 are formed so that the center region is open. The first insulating layer 37 is buried in the center region of the open first channel layer 36, and the second insulating layer 39 is buried in the open second channel layer 38.

4 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a third embodiment of the present invention.

The third embodiment relates to a non-volatile memory device having a three-dimensional structure in which a channel of a memory cell is formed in an open center area, and a channel of the selection gate is formed in a buried center area. The same as described in the first embodiment.

As shown, the first channel layer 40 is formed so that the center region is opened, and the first insulating layer 41 is buried in the center region of the opened first channel layer 40. In addition, the second channel layer 42 is formed to be completely embedded up to the center region. As such, when the second channel layer 42 of the selection gate is formed to be completely filled up to the center region, the contact areas of the source line SL and the bit line BL may be sufficiently secured.

It is to be noted that the technical spirit of the present invention has been specifically described in accordance with the above-described preferred embodiments, but it is to be understood that the above-described embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

10: substrate 11, 14, 17: interlayer insulating film
12, 15, and 18: conductive films 13 and 19: gate insulating films
16: charge blocking film, charge trap film and tunnel insulating film
20 substrate 21 first interlayer insulating film
22: pipe gate 23: sacrificial film
24: second interlayer insulating film 25: first conductive film
26: charge blocking film 27: second conductive film
28: buffer film 29: tunnel low smoke film
30, 36, 40: first channel film 31: third interlayer insulating film
32: third conductive film 33: gate insulating film
34, 38, 42: second channel film 35: insulating film
37, 41: first insulating film 39: second insulating film
BL: bit line SL: source line

Claims (14)

Alternately forming a plurality of first interlayer insulating films and a plurality of first conductive films on a substrate;
Etching the plurality of first interlayer insulating layers and the plurality of first conductive layers to form a plurality of first trenches;
Partially recessing the plurality of first interlayer insulating layers exposed on the inner wall of the first trench;
Forming a charge blocking film along an inner surface of the first trench in which the plurality of first interlayer insulating films are recessed;
Forming a second conductive film along an inner surface of the first trench so as to fill a recess region of the first interlayer insulating film;
Forming a buffer layer on the plurality of first trenches to cover the openings of the plurality of first trenches and to expose bottom surfaces of the plurality of first trenches; And
Removing the second conductive layer and the charge blocking layer formed on the bottoms of the plurality of first trenches
Method of manufacturing a non-volatile memory device having a three-dimensional structure comprising a.
The method of claim 1,
Forming a buffer layer on the upper inner walls of the plurality of first trenches and the plurality of first interlayer insulating layers and the plurality of first conductive layers between the plurality of first trenches;
The method of claim 1,
The buffer layer is formed to a height at which a first conductive layer on the top of the plurality of first conductive layers is formed.
A method of manufacturing a nonvolatile memory device having a three-dimensional structure.
The method of claim 1,
The buffer layer is formed under a step coverage of 50% or less.
A method of manufacturing a nonvolatile memory device having a three-dimensional structure.
The method of claim 1,
The buffer layer is formed of USG (Undoped Silicate Glass)
A method of manufacturing a nonvolatile memory device having a three-dimensional structure.
The method of claim 1,
Removing the second conductive film and the charge blocking film,
Removing the second conductive film and the charge blocking film formed on the bottoms of the first trenches while protecting the charge blocking film and the second conductive film formed on the upper inner walls of the plurality of first trenches by the buffer film.
A method of manufacturing a nonvolatile memory device having a three-dimensional structure.
The method of claim 1,
The buffer layer is removed together in the process of removing the second conductive layer and the charge blocking layer.
A method of manufacturing a nonvolatile memory device having a three-dimensional structure.
The method of claim 1,
After removing the second conductive film and the charge blocking film,
Etching the second conductive layer remaining on inner walls of the plurality of first trenches to separate the second conductive layer embedded in the recessed region, respectively.
Non-volatile memory device manufacturing method of the three-dimensional structure further comprising.
The method of claim 1,
The first conductive layer is a control gate and the second conductive layer is a floating gate.
A method of manufacturing a nonvolatile memory device having a three-dimensional structure.
The method of claim 1,
Before the step of alternately forming the plurality of first interlayer insulating films and the plurality of first conductive films,
Forming a second interlayer insulating film on the substrate;
Forming a pipe gate on the second interlayer insulating film;
Etching the pipe gate to form a second trench connected to the pair of first trenches; And
Filling a sacrificial layer in the second trench
Non-volatile memory device manufacturing method of the three-dimensional structure further comprising.
The method of claim 10,
After removing the second conductive film and the charge blocking film,
Removing the sacrificial film;
Forming a tunnel insulating layer on the pair of first trenches and an inner surface of the first trench; And
Forming a first channel film on the tunnel insulating film
Non-volatile memory device manufacturing method of the three-dimensional structure further comprising.
The method of claim 11,
After forming the first channel film,
Filling an insulating film in the pair of first trenches and the second trench in which the first channel layer is formed;
Non-volatile memory device manufacturing method of the three-dimensional structure further comprising.
The method of claim 11,
After forming the first channel film,
Forming a third conductive film and a third interlayer insulating film on the resultant product on which the first channel film is formed;
Etching the third interlayer insulating layer and the third conductive layer to form a third trench;
Forming a gate insulating film on an inner wall of the third trench;
Forming a second channel layer on the gate insulating layer
Non-volatile memory device manufacturing method of the three-dimensional structure further comprising.
The method of claim 13,
After the forming of the second channel film,
Filling an insulating film in the third trench in which the second channel film is formed
Non-volatile memory device manufacturing method of the three-dimensional structure further comprising.

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