KR20130001502A - Semiconductor memory device and method of driving the semiconductor memory device - Google Patents

Semiconductor memory device and method of driving the semiconductor memory device Download PDF

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Publication number
KR20130001502A
KR20130001502A KR1020110062294A KR20110062294A KR20130001502A KR 20130001502 A KR20130001502 A KR 20130001502A KR 1020110062294 A KR1020110062294 A KR 1020110062294A KR 20110062294 A KR20110062294 A KR 20110062294A KR 20130001502 A KR20130001502 A KR 20130001502A
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South Korea
Prior art keywords
word line
line driving
signal
sub word
address signal
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KR1020110062294A
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Korean (ko)
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최용진
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에스케이하이닉스 주식회사
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Publication of KR20130001502A publication Critical patent/KR20130001502A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

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  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)

Abstract

According to the present invention, when the precharge operation is performed on a plurality of word lines, the sub word line driving voltage may be shifted after sequentially shifting the main word line potential to shift the plurality of word lines. This prevents inrush current from being provided to memory cells connected to adjacent word lines. The semiconductor memory device according to the present invention is activated in response to a test signal, and generates a test address signal to sequentially deactivate a plurality of main word lines on which a precharge operation is performed based on the address signal, and the plurality of main word lines An address control unit for generating a sub word line driving voltage control address signal for providing a sub word line driving voltage that is activated after all are deactivated, and a main word line driving for sequentially deactivating a plurality of main word lines based on a test address signal A main wordline driver for generating a signal, and a subwordline driver for generating a plurality of subwordline driving signals based on the subwordline driving voltage and the subwordline driving voltage control address signal.

Description

Semiconductor memory device and method of driving semiconductor memory device {Semiconductor memory device and method of driving the semiconductor memory device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a method of driving a semiconductor memory device capable of improving operation reliability by controlling a driving time of the semiconductor memory device.

The semiconductor memory device may be classified into a volatile memory device and a non-volatile memory device according to whether stored data is lost when the power supply is interrupted. The nonvolatile memory device includes an electrically erasable and programmable ROM (EEPROM).

SUMMARY OF THE INVENTION The present invention provides a semiconductor memory device that reads data written to a memory cell by performing a precharge operation prior to activation to detect and amplify data. The present invention provides a semiconductor memory device and a method of driving the semiconductor memory device capable of improving operation reliability of a memory cell by controlling a driving time to minimize inflow currents to adjacent memory cells.

The semiconductor memory device according to an embodiment of the present invention is activated in response to a test signal, sequentially deactivating a plurality of main word lines on which a precharge operation is performed based on an address signal, and deactivating all of the plurality of main word lines. An address control unit for generating a test address signal for providing a sub word line driving voltage that is activated after being activated, and a main word line driving signal for sequentially deactivating the plurality of main word lines based on the test address signal And a sub word line driver generating a plurality of sub word line driving signals based on the sub word line driving voltage and the main word line driving signal.

A method of driving a semiconductor memory device according to an embodiment of the present invention may include sequentially deactivating a plurality of main word line driving signals based on an address signal in response to a precharge command signal, and driving the plurality of main word lines. After all of the signals are deactivated, deactivating the sub wordline driving voltage based on the address signal.

According to at least one example embodiment of the inventive concepts, a semiconductor memory device and a method of driving the same may sequentially deactivate the main word line when precharging a memory cell connected to the plurality of main word lines, and after the main word line is deactivated. By translating the word line driving voltage, a plurality of main word line driving voltages may be simultaneously shifted to prevent an inflow current from occurring in adjacent memory cells, thereby improving operational reliability of the memory cells.

1A is a circuit diagram illustrating a write and read operation of a semiconductor memory device according to an exemplary embodiment of the present invention.
1B is a waveform diagram illustrating an operation of a semiconductor memory device according to an embodiment of the present invention.
2A is a diagram illustrating a wordline driver of a semiconductor memory device according to an embodiment of the present invention.
2B is a partial circuit diagram illustrating a connection relationship of the sub word line driving transistor unit of FIG. 2A.
3 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
4 is a flowchart illustrating a method of driving a semiconductor memory device according to an embodiment of the present invention, and FIG. 5 illustrates a voltage change of each signal by the method of driving a semiconductor memory device according to an embodiment of the present invention. It is a waveform diagram.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The DRAM memory device may precharge a pair of bit lines to a predetermined precharge voltage, activate a word line, and read out charges stored in a memory cell through the bit line pair.

According to an embodiment, the read operation may be initiated in response to the active command signal ACTIVE, and the precharge operation may be initiated in response to the precharge command signal PRECHARGE. After a read operation is started in response to the active command signal ACTIVE and data written to the memory cell is read, a precharge command signal PRECHARGE is provided in preparation for another operation to shift the bit line pair to a predetermined voltage level. The precharge operation may be performed as part of a read operation or a write operation initiated by an active command signal ACTIVE.

In a typical operation of a DRAM memory device, read and write operations are not performed on a plurality of memory cell arrays, but during the testing phase of the DRAM memory device, the entire main wordline is activated and a sub wordline driver connected thereto is connected. By selectively activating the memory cells corresponding to about 1/4, 1/8, or 1/16 of the memory cell array, the battery cells may be precharged. However, as will be seen below, after a significant number of word lines are activated, an inflow current may be generated through the word line driver during the deactivation process, which may affect the reliability of other adjacent word lines.

1A is a circuit diagram illustrating a write and read operation of a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, the write and sense driving circuit may include a precharge circuit portion PRCG, a memory cell MC, and a sense amplifier SA.

The precharge circuit unit PRCG may include first to third NMOS transistors MN1, MN2, and MN3. The first and second NMOS transistors MN1 and MN2 are connected in series between the bit line pairs BL and / BL so that one terminal of the first NMOS transistor MN1 is connected to the bit line BL. The other terminal of the first NMOS transistor MN1 is connected to one end of the second NMOS transistor MN2, and the other end of the second NMOS transistor MN2 is connected to a bit line bar (/ BL). Is connected to. In addition, the first NMOS transistor MN1 and the second NMOS transistor MN2 may receive the bit line equalization signal BLEQ through the gate. The precharge voltage VBLP is applied to a node to which the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected.

The first NMOS transistor MN3 is connected between the bit line pairs BL and / BL to connect the bit line pairs BL and / BL in response to the bit line equalization signal BLEQ.

Therefore, when all of the first to third NMOS transistors MN1, MN2, and MN3 are turned on in response to the bit line equalization signal BLEQ, the precharge circuit part PRCG turns on the bit line precharge voltage. VBLP) is provided to the bit line pairs BL and / BL to perform the precharge operation.

The memory cell MC may include a fourth NMOS transistor MN4 and a data capacitor DC1. The fourth NMOS transistor MN4 may include a gate connected to the sub word line SWL, a first terminal connected to the bit line BL, and a second terminal connected to the data capacitor DC1. The memory cell MC is configured in response to the sub word line driving signal SWLD provided to the sub word line SWL.

The data capacitor DC1 receives the charge of the bit line BL through the fourth NMOS transistor MN4 activated in response to the sub word line driving signal SWLD, and stores or writes the charge in the case of a read operation. In the case of an operation, the stored charge is provided to the bit line BL.

The sense amplifier SA may include first and third PMOS transistors MP1 and MP2 and fifth and sixth NMOS transistors MN5 and MN6.

The first PMOS transistor MP1 may include a gate connected to the bit line bar / BL, a first terminal receiving a first power supply voltage RTO, and a second terminal connected to the bit line BL. The second PMOS transistor MP2 may include a gate connected to the bit line BL, a first terminal receiving the first power voltage RTO, and a second terminal connected to the bit line bar / BL.

The fifth NMOS transistor MN5 may include a gate connected to the bit line bar / BL, a first terminal receiving a second power supply voltage SB, and a second terminal connected to the bit line BL. The sixth NMOS transistor MN6 may include a gate connected to the bit line BL, a first terminal receiving a second power supply voltage SB, and a second terminal connected to the bit line bar / BL.

The sense amplifier SA reads data in response to a control signal such as a sense activation signal. The data read operation may simply be performed during the data read operation or may also be performed in the verify operation in the data write operation.

Hereinafter, the case of reading data '1' will be described.

The sense amplifier SA is a bit line BL when the charge provided from the memory cell MC has a positive value with respect to the bit line pairs BL and / BL precharged with the bit line precharge voltage VBLP. The sixth NMOS transistor MN6 is turned on so that the second power supply voltage SB is provided to the bit line bar / BL, and the first PMOS transistor MP1 is turned on to turn on the bit line. The voltage of BL is increased to the first power supply voltage RTO level. Accordingly, the first PMOS transistor MP1 and the sixth NMOS transistor MN6 are turned on, and the second PMOS transistor MP2 and the fifth NMOS transistor MN5 are turned off so that the voltage of the bit line BL is zero. The voltage of the bit line bar / BL corresponds to the first power supply voltage RTO, and is developed to correspond to the second power supply voltage SB.

1B is a waveform diagram illustrating an operation of a semiconductor memory device according to an embodiment of the present invention. In FIG. 1B, the X axis represents time (s) and the Y axis represents voltage (V).

When the active command signal ACTIVE is applied at the time t1, the sub word line SWL transitions to the boosted voltage VPP level to be activated and is precharged based on the data stored in the memory cell MC. The voltage difference between the bit line pairs BL and / BL that have been precharged gradually increases, so that the voltages of the bit line pairs BL and / BL become the levels of the first power supply voltage RTO and the second power supply voltage SB, respectively. Transition to. In FIG. 1B, the second power supply voltage SB corresponds to the ground voltage VSS, but the second power supply voltage SB may correspond to the negative power supply voltages VBB and VBBW. Voltage may be less than or equal to (VSS). When the data reading is completed, the precharge command signal PRECHARGE is applied at time t2. In response, the sub word line SWL is deactivated to the ground voltage VSS, and the bit line pairs BL and / BL are also bitwise. It is precharged to the line precharge voltage VBLP.

However, as shown in FIG. 1B, the bit line pairs BL and / BL are precharged after the sub word line SWL is deactivated at the time t3, but the SWL2 is the bit line pairs BL and / BL. The timing at which the potential of and the potential of the word line transition is not appropriate. At the time t3 before the sub word line SWL2 is deactivated to the ground voltage VSS, the voltages of the bit line pairs BL and / BL transition to the bit line precharge voltage VBLP, and the sub word at time t4. When the line SWL2 is inactivated, a voltage of a bit line may flow into the data capacitor DC1 of the memory cell MC connected to the sub word line SWL2, thereby causing a data write error.

In the case of activating and precharging a plurality of main word lines, the above-described problem may occur because a time when the voltage of the word line falls to the ground voltage VSS may be delayed due to the capacitance of the word line itself.

2A is a diagram illustrating a wordline driver of a semiconductor memory device according to an embodiment of the present invention.

The word line driver may include a main word line driver 100 and a sub word line driver 200. A plurality of sub word lines SWL may be connected to one main word line MWL. In FIG. 2A, one main word line and four sub word lines are connected by a 1: 4 decoding method. However, the structure is not limited thereto.

The main wordline driver 100 may provide a plurality of main wordline driving signals MWLD <0>, MWLD <1>, ..., MWL <n> based on the address signal ADDR. The plurality of main word line driving signals MWLD <0>, MWLD <1>, ..., MWL <n> may be connected to the sub word line driving circuit 210 included in the sub word line driver 200, respectively. Can be.

The sub word line driver 200 may include sub word line driver circuits 210 corresponding to the number of main word lines MWL, and each sub word line driver circuit 210 drives a plurality of sub word line drivers. The transistor units 211, 213, 215, and 217 may be included.

The sub wordline driver circuit 210 is activated in response to the corresponding main wordline driver signal MWLD <0>. For example, the main wordline driving signal MWLD may correspond to a low activation signal and, when activated, may correspond to a logic state fellow. The first sub word line driving transistor unit 211 may include a first driving PMOS transistor DP1 and first and second driving NMOS transistors DN1 and DN2.

The first driving PMOS transistor DP1 may include a gate to which the first main wordline driving signal MWLD <0> is applied, a first terminal to which the first sub wordline driving voltage FX <0> is applied, and a first terminal. It includes a second terminal connected to the sub word line (SWL0). The first driving NMOS transistor DN1 may include a gate receiving the first main word line driving signal MWLD <0>, a first terminal connected to the inactive node VN, and a first sub word line SWL0. It may include two terminals. The second driving NMOS transistor DN2 may include a gate to which the first sub word line compensation driving voltage / FX <0> is applied, a first terminal connected to the deactivation node VN, and a first sub word line SWL0. It may include a second terminal connected.

When the active command signal ACTIVE is applied and the first main word line driving signal MWLD <0> is activated, the first driving PMOS transistor DP1 is turned on and the first driving NMOS transistor DN1 is turned on. OFF, the first sub wordline driving voltage FX <0> is provided as the first subwordline driving signal SWLD <0>. The first sub word line driving voltage FX <0> may have a boosted voltage VPP level, so that the first sub word line compensation driving voltage / FX <0> may have a ground voltage VSS level. Can have Accordingly, the first sub word line driving signal SWLD <0> corresponds to the boosted voltage VPP level and the second driving NMOS transistor DN2 is turned off.

When the precharge command signal PRECHARGE is applied, the first main wordline driving signal MWLD <0> is inactivated to turn off the first driving PMOS transistor DP1, and the first driving NMOS transistor DN1 is turned off. Is turned on. The first sub wordline driving voltage FX <0> corresponds to the ground voltage VSS level, and the first subwordline compensation driving voltage / FX <0> corresponds to the boost voltage VPP level. The two driving NMOS transistor DN2 is turned on. Therefore, the first sub word line driving signal SWLD <0> is inactivated.

The second to fourth sub wordline driving transistor units 213, 215, and 217 may operate in substantially the same manner as the first sub wordline driving transistor unit 211. However, when the first sub word line driving signal SWLD <0> is activated based on the address signal, the second to fourth sub word line driving signals SWLD <1>, SWLD <2>, and SWLD <3>. ) May be deactivated. In this case, since the first main wordline driving signal MWLD <0> is equally activated, the second to fourth subwordline driving voltages FX <1> and FX are concluded. <2> and FX <3> are inactivated to deactivate the second to fourth sub wordline driving signals SWLD <1>, SWLD <2>, and SWLD <3>.

2B is a partial circuit diagram illustrating a connection relationship of the sub word line driving transistor unit of FIG. 2A.

Referring to FIG. 2B, the inactive nodes VN of the first to fourth sub wordline driving transistor units 211, 213, 215, and 217 may be connected to one.

For example, it is assumed that the precharge operation is performed after the fourth sub word line SWL3 is activated.

When the third sub word line is activated in response to the active command signal, the first main word line driving signal MWLD <0> is activated so that the fourth driving PMOS transistor DP4 is turned on and the seventh driving is performed. NMOS transistor DN7 is turned off. The first to third sub word line driving voltages FX <0> FX <1> and FX <2> are deactivated, and the fourth sub word line driving voltages FX <3> are activated to form an eighth driving NMOS transistor. DN8 is turned off, and the second, fourth and sixth driving NMOS transistors DN2, DN4, and DN6 are turned on. For the convenience of description, other driving transistors are not shown.

Subsequently, when the first main wordline driving signal MWLD <0> is inactivated in response to the precharge command signal PRECHARGE, the fourth driving PMOS transistor DP4 is turned off and the seventh driving NMOS transistor DN7. Is turned on, and the eighth driving NMOS transistor DN8 is turned on to draw the potential of the fourth sub word line SWL3 to the ground voltage VSS level.

However, as described with reference to FIG. 1B, the time at which the potential of the fourth sub word line SWL3 is lowered to the ground voltage VSS level is delayed due to parasitic components such as capacitance of the word line itself, thereby driving the eighth drive. When the NMOS transistor DN8 is turned on, the charges of the memory cells connected to the third sub word line SWL3 may flow into the inactivation node VN. In addition, when simultaneously deactivating memory cells connected to a plurality of sub word lines, an inflow current is generated according to the parasitic components of the word line in the process of lowering the boost voltage VPP to the ground voltage VSS, and the inflow current May increase the voltage level of the deactivation node VN through the eighth driving NMOS transistor DN8. As a result, an elevated voltage is provided through the second driving NMOS transistor DN2, the fourth driving NMOS transistor DN4, and the sixth driving NMOS transistor DN6 that are turned on to provide the first to third sub word lines. The potentials of (SWL0, SWL1, SWL2) are raised and unwanted memory cells can be activated.

In the case of the general write and read operations, the number of activated sub word lines is relatively small, so that the potential increase due to the word line capacitance may not affect the operation of the semiconductor memory device. If the lines are activated and they are precharged, the voltage rise due to the capacitance of the wordline can be a data error.

Accordingly, the semiconductor memory device according to an embodiment of the present invention sequentially deactivates a plurality of word lines instead of simultaneously deactivating the plurality of word lines to increase the voltage transition rate of each word line, thereby reducing the first to third sub word lines SWL0, SWL1, and the like. The current flows into adjacent memory cells such as those connected to SWL2 to prevent data from being different.

In addition, since the inflow current path may be generated through the eighth driving NMOS transistor DN8 in the process of lowering the voltage of the main word line, which has been activated, to the power supply voltage VSS, after the voltage of the main word line is deactivated. The fourth sub word line driving voltage FX <3> may be shifted to turn on the eighth driving NMOS transistor DN8 to block the current inflow path to the inactive node VN.

3 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, the semiconductor memory device 300 may include a command controller 310, an address controller 320, an address decoder 330, a main wordline driver 100, a subwordline driver 200, and a subwordline. The driving voltage providing unit 340 and the memory cell array 350 may be included.

The command controller 310 receives a clock signal CLK, a row address strobe signal RAS, a column address strobe signal CAS, a status signal STT, and the like from an external device such as a host, and executes a command signal through a logic operation. CMD).

In some embodiments, the command signal CMD may include an active signal ACTIVE, a precharge signal PRECHARGE, and a test signal TEST.

The address controller 320 is activated in response to the test signal TEST included in the command signal CMD, and generates and provides a test address signal TADDR to the address decoder 330.

The test address signal TADDR provides the main word line driving signals for the plurality of word lines for which the precharge operation is performed in the case of a test operation. The test address signal TADDR is provided without sequentially deactivating the plurality of main word line driving signals. Activate it. The main word line driving signals may be sequentially deactivated one by one or at predetermined intervals. In addition, even if the main word line driving signals are sequentially deactivated, since the potential change in the sub word line driver 200 is caused by the sub word line driving voltage, the sub word line driving voltage is in response to the precharge command signal PRECHARGE. The sub word line driving signals may transition after all of the main word line driving signals MWLD in which the precharge operation is performed are deactivated without being transitioned.

During normal operation, the address decoder 330 may provide the address signal ADDR to the main wordline driver 100 in response to the address signal ADDR and provide the sub wordline driving voltage control address signal BAX. have.

During the test operation, the address decoder 330 may receive the address signal ADDR and the sub word line driving voltage control address in response to the test address signal TADDR provided from the address controller 320 activated in response to the test signal TEST. It can provide a signal BAX. For example, the test address signal TADDR may be generated to classify the row address signals among the address signals ADDR according to a predetermined unit and sequentially deactivate the main word lines at predetermined delay time intervals.

In addition, during the test operation, the address decoder 300 provides the sub wordline driving voltage control address signal BAX to the subwordline driving voltage providing unit 340 in response to the test address signal TADDR. The sub word line driving voltage control address signal BAX may shift the sub word line driving voltage FX after all of the main word lines to which the precharge is performed, that is, the main word lines that are activated and deactivated, are deactivated. Can be. As a result, even in this case, the test address signal TADDR may be generated to delay the transition time of the sub word line driving voltage FX.

The main wordline driver 100 provides a plurality of main wordline driving signals MWLD in response to the address signal ADDR, and the sub wordline driver 200 responds to a corresponding main wordline driving signal MWLD. The sub word line driving signal SWLD is provided to the memory cell array 350 through the sub word line. The sub word line driver 200 may be driven based on the sub word line driving voltage FX provided by the sub word line driving voltage providing unit 340. Each sub word line driving voltage FX may be provided to correspond to a sub word line driver connected in units of a main word line MWL.

A method of driving a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 4 and 5.

4 is a flowchart illustrating a method of driving a semiconductor memory device according to an embodiment of the present invention, and FIG. 5 illustrates a voltage change of each signal by the method of driving a semiconductor memory device according to an embodiment of the present invention. It is a waveform diagram.

When the command signal CMD is configured to perform an active operation, that is, when the active command signal ACTIVE is applied at a time t1, the first to fourth main word lines are activated based on the address signal ADDR at a time t2. The first to fourth first main wordline driving signals MWLD <0> provided to are activated to transition to a logic state fellow.

When the third sub word line is to be activated among the plurality of sub word lines respectively connected to the first to fourth main word lines based on the address signal ADDR, the third sub word line driving voltage FX at time t3. <2> may be activated and provided to the sub wordline driver 200. Accordingly, in the first to fourth main word lines, memory cells connected to the third connected sub word lines are activated.

When the active operation is completed and the precharge command signal PRECHARGE is applied at time t4 (step S410), the first to fourth main word lines are driven to sequentially deactivate the first to fourth main word lines that are activated. Signals MWLD <0>, MWLD <1>, MWLD <2>, and MWLD <3> are sequentially deactivated at time points t5, t6, t7, and t8 to transition to a logic state “high”.

However, this is exemplary and the first and second main word line driving signals MWLD <0> and MWLD <1> are inactivated at time t5 and the third and fourth main word line driving signals at time t6 ( MWLD <2>, MWLD <3>) may be deactivated, and thus the deactivation time may be adjusted in a different manner depending on the design, and the illustration of FIG. 5 is merely exemplary. However, in the present invention, even when a plurality of main word line driving signals are activated at the same time, when performing the precharge operation, each word is classified by a predetermined unit and the inactive time is sequentially distributed to minimize the inflow current due to the capacitance of the main word line. The voltage transition time at which the lines are deactivated to have a voltage below ground voltage VSS can be reduced.

When all of the main word line driving signals MWLD are inactivated (step S430, YES), the sub word line driving voltage FX is shifted at step t9 (step S440). In the case of the sub word line driving voltages FX <0>, FX <1>, and FX <3>, which are not activated, the level of the ground voltage VSS is maintained in the same manner, and the third sub word line driving voltage which is activated is activated. (FX <2>) transitions.

After all of the word lines are deactivated and the sub word line driving voltage FX is also deactivated, the bit line equalization signal BLEQ is converted to convert the bit line pairs BL and / BL to the bit line precharge voltages. VBLP) (step S450). When the bit line equalization signal BLEQ is activated before the main word line MWL is inactivated, a problem may occur in the driving circuit along the word line in which the bit line precharge voltage VBLP is activated.

In the method of driving a semiconductor memory device according to an embodiment of the present invention, adjusting the transition time of the main word line driving signals MWLD is sequentially performed by a shift register operating in response to a clock signal or by a delay circuit. The sub word line driving voltage FX is transitioned after all the main word line driving signals are inactivated so that the voltage level of each of the main word line driving signals is changed or is preset. It may be implemented by delaying the transition time of the sub word line driving voltage FX.

In a semiconductor memory device according to an embodiment of the present invention, in the process of deactivating a plurality of main word lines in an activated state for precharge operation, the main word lines are sequentially deactivated, or the main word lines are classified by a predetermined unit. By sequentially deactivating the classified main word lines, it is possible to prevent inrush current from flowing into a specific node due to the capacitance of the main word lines in an instant, and to reduce the time for the main word lines to transition below the ground voltage VSS. .

In addition, the method of driving a semiconductor memory device according to an exemplary embodiment of the present invention shifts the sub word line driving voltage after all of the word lines are inactivated in the precharge operation to perform the sub word line of the activated word line. The driving circuit may prevent the charge from flowing through the ground voltage VSS or the negative power voltage VBBW node to increase the potential, thereby improving the safety of operation of memory cells connected to adjacent word lines.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

100: main wordline driver
200: sub wordline driver
310: command control unit
320: address control unit
330: address decoder
340: sub word line driving voltage providing unit
350: memory cell array

Claims (10)

A sub address, which is activated in response to the test signal, generates a test address signal to sequentially deactivate the plurality of main word lines on which the precharge operation is performed based on the address signal, and is activated after the plurality of main word lines are all deactivated An address control unit for generating a sub word line driving voltage control address signal to provide a word line driving voltage;
A main word line driver to generate a main word line driving signal to sequentially deactivate the plurality of main word lines based on the test address signal; And
And a sub word line driver generating a plurality of sub word line driving signals based on the sub word line driving voltage and the sub word line driving voltage control address signal. The method according to claim 1,
And a plurality of word lines are driven based on the sub word line driving signal, and a pair of bit lines is precharged in response to a bit line equalization signal. The method according to claim 1,
The address control unit,
And delaying the row address signal sequentially based on the address signal to generate the test address signal. The method according to claim 1,
The sub word line driver,
The sub word line driving voltage is provided as the sub word line driving signal in response to the main word line driving signal, and the sub word line driving voltage is lower than or equal to the ground voltage VSS based on the sub word line driving voltage. A semiconductor memory device characterized by lowering to a level. The method according to claim 1,
And a sub word line driving voltage providing unit configured to generate the sub word line driving voltage based on the test address signal. Sequentially deactivating the plurality of main word line driving signals based on the address signal in response to the precharge command signal; And
And inactivating a sub word line driving voltage based on the address signal after all of the plurality of main word line driving signals are inactivated. The method of claim 6,
In order to sequentially deactivate the plurality of main word line driving signals,
Classifying a plurality of main word line addresses to which the precharge operation is to be performed, based on the address signal, in predetermined units;
And generating a test address signal such that a plurality of main word line driving signals are sequentially deactivated based on the classified main word line addresses. The method of claim 6,
And precharging the bit line pair by activating a bit line equalization signal after the sub word line driving voltage transitions. The method of claim 6,
And the word line driving signal inactivated has a value equal to or less than a ground voltage. The method of claim 6,
Simultaneously activating the deactivated main wordline driving signals based on the address signal in response to an active command signal; And
And simultaneously activating the sub word line driving voltage in response to the active command signal.
KR1020110062294A 2011-06-27 2011-06-27 Semiconductor memory device and method of driving the semiconductor memory device KR20130001502A (en)

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