KR20120138939A - Testmode control circuit for semiconductor device - Google Patents

Testmode control circuit for semiconductor device Download PDF

Info

Publication number
KR20120138939A
KR20120138939A KR1020110058381A KR20110058381A KR20120138939A KR 20120138939 A KR20120138939 A KR 20120138939A KR 1020110058381 A KR1020110058381 A KR 1020110058381A KR 20110058381 A KR20110058381 A KR 20110058381A KR 20120138939 A KR20120138939 A KR 20120138939A
Authority
KR
South Korea
Prior art keywords
test mode
signal
test
circuit unit
circuit
Prior art date
Application number
KR1020110058381A
Other languages
Korean (ko)
Inventor
박민수
김재일
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110058381A priority Critical patent/KR20120138939A/en
Publication of KR20120138939A publication Critical patent/KR20120138939A/en

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A test mode control circuit is disclosed. The test mode control circuit generates and outputs a test mode enable signal in response to a plurality of test group select code signals TANL code and a test mode set signal TMGRSET for selecting a target circuit to be tested. A signal generator; And a test mode selection signal controller configured to receive a test mode selection signal TCM for selecting one of a plurality of test modes, and selectively output or block based on the test mode enable signal level.

Description

Test mode control circuit for semiconductor device

The present invention relates to a semiconductor device, and more particularly, to a test mode control circuit of a semiconductor device capable of reducing power consumption during a test mode operation of a semiconductor device and preventing a malfunction during the test mode operation.

In general, in the test mode of the semiconductor device, a test mode corresponding to the address combination is enabled among a plurality of test modes by combining addresses input from the outside to perform a test.

By the way, the size of the semiconductor device is gradually reduced, the design is changed to reduce the metal lines of the semiconductor device, and various methods for reducing the metal line required in circuits related to the test mode of the semiconductor device have been studied.

Selecting a Test Mode of the Semiconductor Device Among the test mode control circuits, a method of coding and using a test group selection code for selecting a target circuit to be tested from among various circuits of the semiconductor device is used.

1 is a diagram illustrating a test mode control circuit of a general semiconductor device. Referring to FIG. 1, the test mode control circuit includes a test mode enable signal generation unit 11, a reset circuit unit 12, a transfer gate circuit unit 13, a latch circuit unit 14, and an output circuit unit 15. do. The test mode enable signal generator 11 decodes the received test group selection signal TANL code using a decoder, and when the decoding signal is enabled, receives the test mode set signal TMGRSET and outputs the output terminal net0. ) To the High level to enable the test mode.

The reset circuit unit 12 receives the test mode enable signal of the decoding circuit unit 11 and maintains the enable state until the reset signal is input, and initializes the test mode when the reset signal is input.

However, in the test mode control circuit, the output signal of the reset circuit unit 12 maintains a low level in an initial state, and through one of the control input terminals of one of the control input terminals net1 of the transfer gate circuit unit 13 through an inverter. The potential is maintained at a high level.

As a result, the transfer gate circuit unit 13 maintains the enabled state until the reset signal is input to the reset circuit unit 12, and latches data for the test mode selection signal TCM received by the latch circuit unit 14. The test mode signal TM_OUT is output through the output circuit 15.

When the test mode set TMGRSET signal is applied, the transfer gate circuit 13 is disabled and outputs the data stored in the latch circuit 14 as a test mode signal TM_OUT until the test mode is reset. do.

However, since the transfer gate circuit unit 13 is always enabled in an initial state, a lot of driving capability is required when a signal latched by the latch circuit unit 14 is changed into a newly input test mode selection signal TCM. .

However, as the test mode of the semiconductor device increases, corresponding test mode control circuits are required, and more power is required to drive the plurality of test mode control circuits.

That is, in the general test mode control circuit shown in FIG. 1, since the transfer gate circuit unit 13 is always enabled, when the data latched in the latch circuit unit 14 is replaced with a newly input test mode signal TCM. Many driving capacities are required, and there is a problem that the signal level latched in the latch circuit unit 14 included in each test mode control circuit cannot be changed, resulting in malfunction.

Accordingly, an object of the present invention is to provide a test mode control circuit for a semiconductor device which can reduce power consumption in the test mode control circuit and can prevent malfunction.

The test mode control circuit of the semiconductor device according to an exemplary embodiment of the present invention generates a test mode enable signal in response to a plurality of test group selection code signals TANL code and a test mode set signal TMGRSET for selecting a target circuit to be tested. A test mode enable signal generation unit generating and outputting the test mode enable signal generation unit; And a test mode selection signal controller configured to receive a test mode selection signal TCM for selecting one of a plurality of test modes, and selectively output or block based on the test mode enable signal level.

The test mode enable signal generation unit may further include: a decoder configured to decode the test group selection code signal (TANL code) and output a decoded test group selection code signal; And a logic operation unit configured to perform a logic operation on the decoded test group selection code signal and the test mode set signal TMGRSET to generate the test mode enable signal. The logic operation unit is implemented with a NAND gate.

The test mode selection signal controller may include a first latch circuit unit; And a transfer gate circuit unit configured to transfer the test mode selection signal TCM received by being enabled to the test mode enable signal to the first latch circuit unit, wherein the first latch circuit unit is transferred from the transfer gate circuit unit. The test mode selection signal TCM is latched, and the latched test mode selection signal is inverted and output.

The transmission gate circuit unit further includes an inverter for inverting the test mode enable signal and supplying the test mode enable signal to one of the control terminals of the control gate circuit unit.

The test mode control circuit further includes a reset circuit unit for initializing the test mode control circuit in response to a test mode reset signal TMGRPRSTB.

A second latch set by the test mode enable signal and reset by the test mode reset signal TMGRPRSTB to output a control signal for enabling or initializing the test mode circuit Circuit section; And an output circuit unit configured to perform a logic operation on the control signal and the inverted test mode selection signal output from the first latch circuit.

The reset circuit unit further includes an inverter for inverting the control signal and outputting the control signal to the output circuit unit.

The second latch circuit portion is implemented with an S-R latch. The output circuit unit is implemented as a NOR gate.

The test mode control circuit of the semiconductor device according to the present invention can reduce power consumed when driving the test mode and can prevent malfunctions caused by insufficient power.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.
1 is a diagram illustrating a general test mode control circuit.
2 is a schematic block diagram illustrating a test method of a general semiconductor device.
3 is a block diagram schematically illustrating a test mode control circuit shown in FIG. 1.
4 is a diagram illustrating a test mode control circuit according to the present invention.
FIG. 5 is a timing diagram illustrating an operation of a test mode control circuit according to the present invention shown in FIG. 4.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

FIG. 2 is a schematic block diagram illustrating a test method of a general semiconductor device, and FIG. 3 is a block diagram illustrating a test mode control circuit unit illustrated in FIG. 2. 2 and 3, when a semiconductor device is generally tested, the test mode control circuit unit 10 includes a plurality of test mode control circuits 100, 200, and 300, and each test mode control circuit. (100, 200, 300) is a test mode signal (TM_out) for selecting a test mode through any one of a plurality of test mode circuit 30 based on a plurality of control signals (TMGRPSET, TMGRPRSTB, TCM, TANL) 1 ~ TM_out n) is outputted.

The test mode driving unit 20 includes a plurality of test mode driving circuits for performing the plurality of test modes, and receives a test mode signal output from the test mode control circuit unit 10 and enables the test mode test circuit. signal) is output to the test target circuit 30.

The test target circuit 30 selects a target circuit to be tested based on a TANL code signal for selecting a circuit to be tested among a plurality of test target circuits, and is input from the test mode driver 20. The test is performed by receiving a test signal.

The test mode control circuit unit 10 includes a plurality of test mode control circuits 100, 200, and 300, and each of the plurality of test mode control circuits 100, 200, and 300 selects a target circuit to be tested. A test group selection code (TANL code) signal and a test mode selection signal TCM for selecting a test method of a target circuit to be tested are received to output a plurality of test signals TM_OUT_1 to TM_OUT_N.

Since each of the plurality of test mode control circuits 100, 200, and 300 has the same configuration and operation method, the test mode control circuit will be described as an example.

4 is a diagram illustrating a test mode control circuit according to the present invention, and FIG. 5 is a timing diagram illustrating an operation method of the test mode control circuit according to the present invention shown in FIG. 4. 4 and 5, the test mode control circuit 100 includes a test mode enable signal generator 110 and a test mode selection signal controller 120. The test mode control circuit 100 further includes a reset circuit unit 130,

The test mode enable signal generator 110 receives a test group select code signal (TANL code) and enables a test mode to enable a test mode in response to a test mode set signal TMGRSET output from a controller. Output the signal TM_EN.

The test group select code signal TANL is a signal for selecting any one of a plurality of circuits to be tested.

The test mode enable signal generator 110 includes a decoder 111 and a logic operator 112.

The decoder 111 decodes and outputs the test group selection code signal. That is, the test group selection code signal TANL code signal including information for selecting a specific circuit to be tested is decoded to output a high level decoded test mode selection code signal. The decoder 111 may be implemented using a general decoder.

The logic operation unit 112 receives and decodes the decoded test group selection signal and the test mode set signal TMGRSET output from the decoder 111 to generate and output the test mode enable signal TM_EN. do.

The logic operation unit 112 receives the decoded test group selection signal of a high level, and in response to the test mode set signal TMGRPSET of a high level, the logic operation unit 112 receives a test mode of a low level. Outputs the enable signal TM_EN.

In more detail, when the output signal of the decoder 111 is at a high level, when the test mode set signal TMGRSET is enabled, the logic operation unit 112 enters a low level test mode. The enable signal TM_EN is output and the output node net0 is changed from the high level of the initial state to the low level. The logic operation unit 112 may be implemented as a NAND gate circuit.

The test mode selection signal controller 120 receives the test mode selection signal TCM output from an externally connected controller (not shown) and based on the signal level of the test mode enable signal TM_EN, The test mode selection signal TCM is selectively output. The test mode selection signal TCM is a signal for selecting any one of a plurality of test modes to test a test target circuit.

The test mode selection signal controller 120 includes a transfer gate circuit 121 and a first latch circuit 122.

The transfer gate circuit unit 121 further includes an inverter IV1 connected to any one of a control signal input terminal IN and a complementary input terminal INB of the transfer gate circuit unit 121. In the present invention, the inverter IV1 is preferably positioned in front of the control signal input terminal IN of the transfer gate circuit unit 121.

The transmission gate circuit unit 121 receives the test mode selection signal TCM and selectively receives the test mode selection signal TCM based on the signal level of the test mode enable signal. 122) or block.

That is, the transfer gate circuit unit 121 transmits the test mode selection signal TCM enabled and received to the latch circuit unit 122 in response to the low level test mode enable signal TM_EN. In response to the high level test mode enable signal TM_EN, the signal is disabled to block the received test mode selection signal TCM.

That is, in the initial state, the transfer gate circuit unit 121 maintains the off state by the test mode enable signal being at the high level and the output node net0 at the high level.

Accordingly, only the transmission gate circuit unit 121 included in the test mode control circuit selected from among the plurality of test mode control circuits shown in FIG. 2 based on the test group selection code (TANL code) signal is enabled, thereby enabling the transmission gate. Power consumption for changing the level of the signal stored in the first latch circuit portion 122 connected to the output terminal of the circuit portion 121 is reduced. That is, by inputting a test group selection code for selecting a target circuit to be tested only to a test mode circuit for enabling a test driving circuit, only a transmission gate included in the test mode control circuit to be enabled among the plurality of test mode control circuits. Enable it.

Compared with the general test mode control circuit shown in FIG. 1, since the general test mode control circuit receives a control signal output from the latch circuit constituting the reset circuit unit 12, the transmission gate circuit unit is turned on in the initial state. do. As a result, when the test mode control circuit is enabled, a plurality of transmission gate circuits included in the plurality of test mode control circuits are all operated, which consumes a lot of power and causes an error in which a signal level does not change. there was.

On the other hand, the test mode control circuit 100 according to the present invention maintains the off state in the initial state, the test mode is changed among the plurality of test circuits (100, 200, 300) shown in Figure 3 according to the test mode By enabling only the transmission gate circuit unit 121 of the control circuit, power consumption can be reduced, and malfunctions due to power shortage can be prevented.

The first latch circuit unit 122 latches the test mode selection signal TCM transmitted from the transfer gate unit 121 or outputs an existing latched test mode selection signal. The first latch circuit unit 132 includes two inverters IV2 and IV3, latches a test mode selection signal TCM transmitted from the transfer gate circuit unit 121, and inverts the test mode selection signal. Output

The reset circuit unit 130 initializes the test mode control circuit in response to a test mode reset signal TMGRPRSTB output from the test mode enable signal generator.

The reset circuit unit 130 includes a second latch circuit unit 131, an inverter 132, and an output circuit unit 133.

The second latch circuit unit 131 is set to the test mode enable signal TM_EM to output a high level control signal, and is one of the input terminals of the output circuit through the inverter 132. The 'net1' is kept at a low level and the test mode is enabled until the reset signal TMGRPRSTB is input.

In this case, the second latch circuit 131 may be implemented without the inverter by outputting a control signal for maintaining 'net1' at a low level through the complementary output terminal QB. The second latch circuit unit 131 may be implemented as an S-R latch.

The output circuit unit 133 performs a logic operation on the control signal received through the inverter 132 and the output signal of the test mode selection signal controller 120 to output a test mode signal, or to initialize the output test mode signal. do.

That is, when the control signal of the low level is received, the output signal of the first latch circuit unit 122 included in the test mode selection signal controller 120 is inverted to convert the test mode selection signal TCM to the test signal. The test signal TM_OUT is initialized to a low level based on a high level control signal. The output circuit unit 140 may be implemented as a NOR GATE circuit.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

100: test mode control circuit 110: test mode enable signal generator
111: decoder 112: logical operation unit
120: test mode selection signal control unit 121: transmission gate circuit unit
122: first latch circuit portion 130: reset circuit portion
131: second latch circuit portion 132: inverter
133: output circuit

Claims (10)

A test mode enable signal generation unit configured to generate and output a test mode enable signal in response to a plurality of test group selection code signals TANL code and a test mode set signal TMGRSET for selecting a target circuit to be tested; And
A test mode of a semiconductor device including a test mode selection signal controller for receiving a test mode selection signal TCM for selecting one of a plurality of test modes, and selectively outputting or cutting off based on the test mode enable signal level. Control circuit. The method of claim 1,
The test mode enable signal generator,
A decoder for decoding the test group selection code signal TANL code and outputting a decoded test group selection code signal; And
And a logic calculator configured to logically operate the decoded test group selection code signal and the test mode set signal TMGRSET to generate the test mode enable signal. The method of claim 2,
The logic operation unit is a test mode control circuit of a semiconductor device implemented as a NAND gate. The method of claim 1,
The test mode selection signal control unit,
A first latch circuit unit; And
A transmission gate circuit unit configured to transfer the test mode selection signal TCM, which is received and enabled by the test mode enable signal, to the first latch circuit unit;
The first latch circuit unit,
A test mode control circuit of a semiconductor device which latches the test mode selection signal (TCM) transmitted from the transfer gate circuit unit and inverts and outputs the latched test mode selection signal. 5. The method of claim 4,
And the inverter further comprises an inverter for inverting the test mode enable signal and supplying the test mode enable signal to one of the control terminals of the control gate circuit unit. 5. The method of claim 4,
The test mode control circuit,
And a reset circuit section for initializing the test mode control circuit in response to a test mode reset signal TMGRPRSTB. The method according to claim 6,
The reset circuit unit,
A second latch circuit unit which is set by the test mode enable signal and reset by the test mode reset signal TMGRPRSTB to output a control signal for enabling or initializing the test mode circuit; And
And an output circuit unit configured to logically output the control signal and an inverted test mode selection signal output from the first latch circuit. The method of claim 7, wherein
The reset circuit unit,
And an inverter for inverting the control signal and outputting the control signal to the output circuit unit. The method of claim 7, wherein
The second latch circuit part of the test mode control circuit of the semiconductor device implemented by the SR latch The method of claim 7, wherein
The output circuit unit is a test mode control circuit of a semiconductor device implemented as a NOR gate.
KR1020110058381A 2011-06-16 2011-06-16 Testmode control circuit for semiconductor device KR20120138939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110058381A KR20120138939A (en) 2011-06-16 2011-06-16 Testmode control circuit for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110058381A KR20120138939A (en) 2011-06-16 2011-06-16 Testmode control circuit for semiconductor device

Publications (1)

Publication Number Publication Date
KR20120138939A true KR20120138939A (en) 2012-12-27

Family

ID=47905504

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110058381A KR20120138939A (en) 2011-06-16 2011-06-16 Testmode control circuit for semiconductor device

Country Status (1)

Country Link
KR (1) KR20120138939A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114882934A (en) * 2021-02-05 2022-08-09 长鑫存储技术有限公司 Test circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114882934A (en) * 2021-02-05 2022-08-09 长鑫存储技术有限公司 Test circuit

Similar Documents

Publication Publication Date Title
US7881136B2 (en) Test mode signal generator for semiconductor memory and method of generating test mode signals
US9360520B2 (en) Test mode control circuit of semiconductor apparatus and control method thereof
US9336838B1 (en) Semiconductor memory apparatus and system including the same
US8214171B2 (en) Semiconductor memory device including test mode circuit
US8238179B2 (en) Device and method for generating test mode signal
JP7299423B2 (en) test circuit
US20090006917A1 (en) Test circuit for supporting concurrent test mode in a semiconductor memory
KR20120138939A (en) Testmode control circuit for semiconductor device
KR100718038B1 (en) Circuit for selecting bank in semiconductor memory apparatus
US7334169B2 (en) Generation of test mode signals in memory device with minimized wiring
US9082470B2 (en) Semiconductor memory apparatus and method of operating using the same
US20180259575A1 (en) Test mode control circuit
US8006148B2 (en) Test mode control circuit and method for using the same in semiconductor memory device
KR100803354B1 (en) Apparatus and method for testing internal voltage in semiconductor integrated circuit
US7453757B2 (en) Apparatus and method of controlling bank of semiconductor memory
US8271820B2 (en) Micro-processor
JP5703605B2 (en) Semiconductor integrated circuit
US10816597B2 (en) Single pin test interface for pin limited systems
US7948823B2 (en) Semiconductor memory device and word line driving method thereof
KR102375054B1 (en) Circuit for setting test mode and semiconductor device including the same
US8149639B2 (en) Test apparatus of semiconductor integrated circuit and method using the same
KR100512162B1 (en) Jtag interface circuit for emulation mode of microprocessor
US20140126319A1 (en) Setting information storage circuit and integrated circuit chip including the same
KR20110121392A (en) Semiconductor memory device
KR20100079770A (en) Semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application