KR20120131504A - Semiconductor device and method for forming the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a forming method thereof are provided to secure sufficient electrostatic capacity by implementing an amplification type capacitor in not only a DRAM with a planar gate structure but also in a DRAM with a vertical gate structure. CONSTITUTION: A first single crystal layer(104) is formed on a semiconductor substrate(100). A second single crystal layer(118) is formed on the upper side of the first single crystal layer. A first top electrode(120) is formed in the sidewall of the second single crystal layer. A second top electrode(122) connects adjacent first top electrodes. A third single crystal layer(124) is formed on the upper side of the second single crystal layer. A conductive layer(128) is formed on the upper side of the third single crystal layer.

Description

Semiconductor device and method for forming the same

The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device including an amplifying capacitor and a method of forming the same.

Most modern electronic appliances are equipped with semiconductor devices. The semiconductor device includes electronic elements such as transistors, resistors and capacitors, which are designed to perform partial functions of the electronic products and then integrated on the semiconductor substrate. For example, electronic products such as a computer or a digital camera include semiconductor devices, such as a memory chip for storing information and a processing chip for controlling information, and the memory chip and the processing chip include a semiconductor substrate. Electronic components integrated on the substrate.

On the other hand, semiconductor devices need to be increasingly integrated in order to meet the excellent performance and low price demanded by consumers. As the degree of integration of semiconductor devices increases, design rules decrease, and the pattern of semiconductor devices becomes smaller. As miniaturization and high integration of a semiconductor device progresses, the overall chip area increases in proportion to an increase in memory capacity, but the area of a cell area where a semiconductor device pattern is formed is actually decreasing. Therefore, in order to secure a desired memory capacity, more patterns must be formed in a limited cell area, so a fine pattern having a reduced critical dimension of the pattern must be formed.

Meanwhile, the semiconductor device may operate according to a predetermined purpose by injecting impurities into a predetermined region of the silicon wafer or depositing a new material. The semiconductor device includes many devices such as transistors, capacitors, resistors, etc. to perform a predetermined purpose, and each device is connected through a conductive layer to exchange data or signals.

In order to improve the degree of integration, not only the size of the various components in the semiconductor device but also the length and width of the connecting lines must be reduced. As the wiring used in the semiconductor memory device, for example, a word line for transmitting a control signal and a bit line for transferring data can be exemplified. Reducing the width of the word lines and bit lines, or the size of the cross section, increases the resistance that impedes the transmission of control signals or data. Such an increase in resistance can slow down the transmission of signals and data in the semiconductor device, increase power consumption, and further impair operational stability of the semiconductor memory device.

On the contrary, when the density is increased and the width of the word line and the bit line is maintained in a conventional manner to prevent the increase in resistance, the physical distance between the adjacent word lines or the bit lines is inevitably closer. Compared to a word line to which a control signal having a relatively high potential is transmitted, a bit line transferring data transmitted from a unit cell capacitor may not normally transmit data due to an increase in parasitic capacitance. If the data is not transmitted through the bit line smoothly, the sense amplifier may need to detect and amplify the data, which may indicate that the semiconductor memory cannot output data stored in the unit cell to the outside. it means.

In order to solve the problem caused by the increase in the parasitic capacitance of the bit line, there is a method of increasing the amount of charge corresponding to the data output from the unit cell, but for this purpose, the size of the capacitor in the unit cell of the semiconductor memory device must be increased. However, as the degree of integration of semiconductor memory devices increases, the area occupied by capacitors in semiconductor memory devices also decreases. That is, there is a limit to increasing the size of the capacitor in the unit cell while increasing the degree of integration of the semiconductor memory device.

On the other hand, in the embedded DRAM structure, a bipolar junction capacitor capacitor is proposed so that the amplified capacitor is operated by the charge stored in the base when the data is read from the DRAM cell. In addition to the charge, the charge supplied to the collector was applied together to provide a structure in which the cell data, the amount of charge stored in the storage electrode, was amplified.

However, embedded DRAM uses a floating body as a storage electrode, and a silicon on insulator (SOI) substrate must be used to implement the structure of the floating body. In a typical DRAM, a bulk silicon substrate is used. There is a problem in that it is not easy to implement the floating body as a storage electrode.

In addition, since the cell size has a size of 10F2 to implement the floating body as a storage electrode, the cell size is highly integrated such that the size of the cell has a size of 8F2 to 4F2 in general DRAM, which is not suitable for implementing the floating body. .

The present invention provides a structure in which amplification capacitors are implemented in a general DRAM to amplify cell data stored in a storage electrode.

A semiconductor device according to an embodiment of the present invention includes a first single crystal layer grown on a semiconductor substrate, a second single crystal layer provided on the first single crystal layer, and a sidewall of the second single crystal layer, wherein the first single crystal layer is provided on the first substrate. A first upper electrode partially buried in the single crystal layer, a second upper electrode connecting the first upper electrode adjacent to each other, a third single crystal layer connected to the second single crystal layer, and the third single crystal It characterized in that it comprises a conductive layer connected to the upper layer.

The first single crystal layer and the third single crystal layer may include an N-type epitaxial silicon single crystal layer.

And, the second single crystal layer is characterized in that it comprises a P-type epitaxial silicon single crystal layer.

And, the conductive layer is characterized in that it comprises a collector electrode.

And a bit line formed on the semiconductor substrate, a bit line contact plug provided between the gates, and a bit line connected to an upper portion of the bit line contact plug and extending in a direction perpendicular to the gate. do.

And an interlayer insulating film disposed on the second upper electrode to electrically insulate the conductive layer.

In addition, the thickness of the first upper electrode and the first single crystal layer overlapping is 100 kPa to 500 kPa.

The semiconductor device may further include a bit line embedded in the semiconductor substrate and a vertical gate provided on the semiconductor substrate.

The first single crystal layer may be provided on the vertical gate.

In addition, the semiconductor device is characterized in that it is applied to a general DRAM.

A method of forming a semiconductor device according to an embodiment of the present invention includes the steps of forming a first single crystal layer on a semiconductor substrate, forming a second single crystal layer on the first single crystal layer, and the second single crystal layer Forming a first upper electrode formed on a sidewall and partially buried in the first single crystal layer and a second upper electrode connecting the adjacent first upper electrode to a third single crystal on the second single crystal layer; Forming a layer, and forming a conductive layer on the third single crystal layer.

And forming a gate on the semiconductor substrate before forming the first single crystal layer, forming a bit line contact plug on the semiconductor substrate between the gates, and forming an upper portion of the bit line contact plug. And forming a bit line connected to the gate in a direction perpendicular to the gate.

The forming of the first single crystal layer may include growing by an epitaxial growth method in which a N-type impurity is doped using the semiconductor substrate as a seed after forming the gate. .

The forming of the first single crystal layer may include forming a first interlayer insulating layer on the bit line, forming a storage electrode predetermined region to expose the semiconductor substrate, and forming a lower portion of the predetermined storage electrode region. And growing by an epitaxial growth method with an N-type impurity doped with the exposed semiconductor substrate as a seed.

The method may further include forming a spacer on a sidewall of the predetermined storage electrode predetermined region on the first single crystal layer after forming the predetermined storage electrode predetermined region.

In the forming of the second single crystal layer, the first single crystal layer may be grown by an epitaxial growth method with a P-type impurity doped as a seed.

And after the forming of the second single crystal layer, performing a planarization etching process on the second single crystal layer, the spacer, and the first interlayer insulating layer.

The forming of the first upper electrode may include removing the spacers, etching an upper portion of the first single crystal layer by performing an anisotropic etching process on the removed spacers, and sidewalls of the second single crystal layer. And embedding an upper electrode material in a portion of which the upper portion of the first single crystal layer is etched.

In addition, the thickness of the upper portion of the first single crystal layer is characterized in that the 100 ~ 500Å.

In the forming of the third single crystal layer, the second single crystal layer may be grown by an epitaxial growth method with an N-type impurity doped as a seed.

The method may further include forming a second interlayer insulating film on the second upper electrode after the forming of the third single crystal layer.

And forming a bit line in the semiconductor substrate before forming the first single crystal layer, and forming a vertical gate on the semiconductor substrate.

The forming of the first single crystal layer may include forming a third interlayer dielectric layer on the vertical gate, and etching the third interlayer dielectric layer to expose the vertical gate to form a storage electrode predetermined region. And growing the vertical gate exposed to the bottom of the predetermined region of the storage electrode by an epitaxial growth method with a N-type impurity doped as a seed.

The method may further include forming a spacer on a sidewall of the predetermined storage electrode predetermined region on the first single crystal layer after forming the predetermined storage electrode predetermined region.

In the forming of the second single crystal layer, the first single crystal layer may be grown by an epitaxial growth method with a P-type impurity doped as a seed.

And performing a planarization etching process on the second single crystal layer, the spacer, and the third interlayer insulating layer after the forming of the second single crystal layer.

The forming of the first upper electrode may include removing the spacers, etching an upper portion of the first single crystal layer by performing an anisotropic etching process on the removed spacers, and sidewalls of the second single crystal layer. And embedding an upper electrode material in a portion of which the upper portion of the first single crystal layer is etched.

In addition, the thickness of the upper portion of the first single crystal layer is characterized in that the 100 ~ 500Å.

In the forming of the third single crystal layer, the second single crystal layer may be grown by an epitaxial growth method with an N-type impurity doped as a seed.

The method may further include forming a fourth interlayer insulating film on the second upper electrode after the forming of the third single crystal layer.

The present invention implements an amplifying capacitor in a general DRAM, thereby providing an effect of having a capacitance of the general storage electrode even when formed at a height lower than that of the general storage electrode.

1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.
2A to 2H are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.
3 is a sectional view of a semiconductor device according to still another embodiment of the present invention;
4A to 4E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with still another embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings in accordance with an embodiment of the present invention will be described in detail.

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention. As shown in FIG. 1, a semiconductor device according to an exemplary embodiment of the present invention may include a first single crystal layer 104 grown on a semiconductor substrate 100 and a second layer disposed on the first single crystal layer 104. The upper electrode 120 disposed on the sidewall of the single crystal layer 118, the second single crystal layer 118, and partially embedded in the upper portion of the first single crystal layer 104, and the upper electrode connecting the adjacent upper electrodes 120 to each other. And a third single crystal layer 124 connected to the upper portion of the second single crystal layer 118, and a conductive layer 128 connected to the upper portion of the third single crystal layer 124. Here, the conductive layer 128 may be used as a collector electrode.

In addition, the gate 102 formed on the semiconductor substrate 100 and the bit line contact plug 108 provided between the gate 102 and the upper portion of the bit line contact plug 108 are perpendicular to the gate 102. It further includes a bit line 110 extending in one direction. The conductive layer 128 is preferably electrically insulated from the upper electrode 122 by the interlayer insulating film 126. The first single crystal layer 104 includes an N-type epitaxial silicon single crystal layer, the second single crystal layer 118 includes a P-type epitaxial silicon single crystal layer, and the third single crystal layer 124 It is preferable to include an N-type epitaxial silicon single crystal layer.

The overlapping of the upper electrode 120 and the first single crystal layer 104 is to cause a gate induced drain leakage (GIDL) phenomenon to improve the writing performance of the DRAM device. This is to improve the storage capacity of the charge by allowing holes to be injected. In order to maximize the above-described effects, the thickness of the upper electrode 120 overlapping with the first single crystal layer 104 is preferably 100 μs to 500 μs.

As described above, the semiconductor device according to the embodiment of the present invention provides a storage electrode having an NPN structure to implement an amplifying capacitor in a DRAM to ensure sufficient capacitance even when the height of the storage electrode is low, and high integration is achieved. Therefore, it can be easily formed also in the unit cell which has a small area.

A method of forming a semiconductor device according to an embodiment of the present invention having the above-described configuration is as follows. 2A to 2H are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, a gate 102 is formed on the semiconductor substrate 100. Next, the first single crystal layer 104 is formed using the semiconductor substrate 100 as a seed. In this case, the first single crystal layer 104 is preferably an N-type epitaxial silicon single crystal layer grown by epitaxial growth while doped with N-type impurities. Next, an interlayer insulating layer 106 is formed on the gate 102 and the first single crystal layer 104, and the bit line contact plug 108 penetrates the interlayer insulating layer 106 and is connected to the semiconductor substrate 100. The bit line 110 is connected to the upper portion of the bit line contact plug 108 and is formed on the interlayer insulating layer 106. Here, the bit line 110 extends in a direction perpendicular to the gate 102 and is shown as a dotted line in FIG. 2A for convenience.

As shown in FIG. 2B, the interlayer insulating layer 112 is formed on the bit line 110, and the interlayer insulating layer 112 is etched to expose the first single crystal layer 104 to thereby store the storage electrode predetermined region 114. Form. The first single crystal layer 104 is not necessarily formed after the formation of the gate 102 as shown in FIG. 2A, but after forming the storage electrode predetermined region 114 to expose the semiconductor substrate 100 in FIG. 2B. It can be formed by an epitaxial growth method using the seed (100).

As illustrated in FIG. 2C, spacers 116 are formed on sidewalls of the storage electrode predetermined region 114. The spacer 116 may be formed of a material having an etching selectivity different from that of the first single crystal layer 104.

As shown in FIG. 2D, the second single crystal layer 118 is formed in the storage electrode predetermined region 114. The second single crystal layer 118 may be formed by growing by an epitaxial growth method while being doped with P-type. In this case, the second single crystal layer 118 is formed by seeding the first single crystal layer 104 grown from the semiconductor substrate 100 as a seed. Since the first single crystal layer is doped with N-type impurities, the second single crystal layer ( In order to dope 118 with P-type impurities, it is preferable to reduce the concentration of N-type impurities and increase the concentration of P-type impurities, that is, by counter-doping.

As shown in FIG. 2E, a planarization etching process is performed on the interlayer insulating film 112, the spacer 116, and the second single crystal layer 118 to leave the height of the storage electrode to be finally formed. At this time, the height of the storage electrode to be finally formed may be reduced according to the amplification rate of the amplifying capacitor according to the present invention. That is, when the amplification ratio of the amplifying capacitor is 20, the height of the storage electrode may be lowered to 1/20 of the existing one. In this case, the height of the storage electrode may have a height of 2000 μs or less, which increases the height of the storage electrode due to high integration, thereby fundamentally preventing defects such as falling of the storage electrode.

As shown in FIG. 2F, upper electrodes 120 and 122 are formed in a portion where the spacer 116 is removed and a portion where the interlayer insulating layer 112 is removed after the upper portion of the interlayer insulating layer 112 and the spacer 116 are removed. Here, a dielectric film may be further formed before forming the upper electrodes 120 and 122. In this case, the etching process is performed on the spacer 116 and then the time of the etching process is increased or anisotropic etching process is additionally performed to partially etch the upper portion of the first single crystal layer 104. Therefore, the upper electrode 120 formed at the portion where the spacer 116 is removed is partially embedded in the upper portion of the first single crystal layer 104. This is to cause a gate induced drain leakage (GIDL) phenomenon to improve the writing performance of the DRAM device, and to improve the storage capability of the charge by allowing holes to be injected into the second single crystal layer 118. . In order to maximize the above-described effects, the thickness of the upper electrode 120 overlapping with the first single crystal layer 104 is preferably 100 μs to 500 μs.

As shown in FIG. 2G, a third single crystal layer 124 is formed on the upper electrode 120 and the second single crystal layer 118. Here, the third single crystal layer 124 may be formed by growing by an epitaxial growth method while being doped with N-type. In this case, the third single crystal layer 124 is formed as a seed of the second single crystal layer 118. Since the second single crystal layer is doped with P-type impurities, the third single crystal layer 124 is doped with N-type impurities. In order to reduce the concentration of the P-type impurities and to increase the concentration of the N-type impurities, that is, it is preferable to form the counter doping (couter doping).

As shown in FIG. 2H, an interlayer insulating layer 126 is formed on the third single crystal layer 124 and a planarization etching process is performed on the interlayer insulating layer 126 to expose the third single crystal layer 124. Subsequently, a conductive layer 128 is formed over the third single crystal layer 124 and the interlayer insulating film 126. Here, the conductive layer 128 may be used as a collector electrode. In this case, the upper electrode 122 and the conductive layer 128 are preferably electrically insulated by the interlayer insulating film 126.

As described above, according to the present invention, an NPN-type storage electrode can be formed to implement an amplifying capacitor in DRAM to ensure sufficient capacitance even when the height of the storage electrode is low, and a unit cell having a small area due to high integration. Also can be easily formed.

In the above description, the amplifying capacitor applied to the general planar gate structure has been described. The amplifying capacitor may be applied to the vertical gate structure as well as the planar gate structure. Hereinafter, the amplifying capacitor applied to the vertical gate structure will be described. Explain.

3 is a cross-sectional view of a semiconductor device according to still another embodiment of the present invention. As shown in FIG. 3, a semiconductor device according to another exemplary embodiment may include a bit line 202 embedded in a semiconductor substrate 200, a vertical gate 204 formed on the semiconductor substrate 200, and a bit line 202 embedded in the semiconductor substrate 200. On the sidewalls of the first single crystal layer 212 grown above the vertical gate 204, the second single crystal layer 216 provided on the first single crystal layer 212, and the second single crystal layer 216. And an upper electrode 218 partially embedded in the upper portion of the first single crystal layer 212, an upper electrode 220 connecting the upper electrodes 218 adjacent to each other, and an upper portion connected to the second single crystal layer 216. The three single crystal layer 222 and the conductive layer 226 connected to the upper portion of the third single crystal layer 222. Here, the conductive layer 226 may be used as a collector electrode.

The conductive layer 226 is preferably electrically insulated from the upper electrode 220 by the interlayer insulating film 224. The first single crystal layer 212 includes an N-type epitaxial silicon single crystal layer, the second single crystal layer 216 includes a P-type epitaxial silicon single crystal layer, and the third single crystal layer 222 It is preferable to include an N-type epitaxial silicon single crystal layer.

The overlap between the upper electrode 218 and the first single crystal layer 212 is to cause a gate induced drain leakage (GIDL) phenomenon in order to improve the writing performance of the DRAM device. This is to improve the storage capacity of the charge by allowing holes to be injected. It is preferable that the thickness of the upper electrode 218 overlapping with the first single crystal layer 212 to maximize the above-mentioned effect is 100 kPa to 500 kPa.

As described above, the semiconductor device according to another embodiment of the present invention provides a storage electrode having an NPN structure and implements an amplifying capacitor in a DRAM including a vertical gate to provide sufficient capacitance even when the height of the storage electrode is lowered. It can be secured, and can be easily formed even in a unit cell having a small area by high integration.

A method of forming a semiconductor device according to still another embodiment of the present invention having the above-described configuration is as follows. 4A through 4E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with still another embodiment of the present invention.

As shown in FIG. 4A, a bit line 202 is formed in the semiconductor substrate 200. Next, a vertical gate 204 is formed on the semiconductor substrate 200, and a spacer 206 is formed on the sidewall of the gate 204. The vertical gate 204 is preferably formed by growing the semiconductor substrate 100 with a P-type impurity as a seed.

As shown in FIG. 4B, after forming the interlayer insulating layer 208 on the semiconductor substrate 100 including the gate 204, the semiconductor substrate 100 is etched to expose the gate 204 so as to store the storage electrode. Form 210. Subsequently, a first single crystal layer 212 is formed on the vertical gate 204 of the bottom of the storage electrode predetermined region 210. At this time, the first single crystal layer 212 is grown by using an epitaxial growth method with the vertical gate 204 as a seed, so that the doping of the N-type impurity is increased than that of the P-type impurity. To form an N-type epitaxial silicon single crystal layer.

As shown in FIG. 4C, after the spacer 214 is formed on the sidewall of the storage electrode predetermined region 210 (see FIG. 4B) above the first single crystal layer 212, the storage electrode predetermined region 210 is buried. The second single crystal layer 216 is formed. The second single crystal layer 216 is grown using an epitaxial growth method with the first single crystal layer 212 as a seed, but is grown in a counter-doped state so that the concentration of the P-type impurities is greater than that of the N-type impurities. It is formed of a -type epitaxial silicon single crystal layer.

As shown in FIG. 4D, a planarization etching process is performed on the interlayer insulating film 208, the spacer 214, and the second single crystal layer 216 to leave the height of the storage electrode to be finally formed. At this time, the height of the storage electrode to be finally formed may be reduced according to the amplification rate of the amplifying capacitor according to the present invention. That is, when the amplification ratio of the amplifying capacitor is 20, the height of the storage electrode may be lowered to 1/20 of the existing one. In this case, the height of the storage electrode may have a height of 2000 μs or less, which increases the height of the storage electrode due to high integration, thereby fundamentally preventing defects such as falling of the storage electrode. Subsequently, after the upper portion of the interlayer insulating film 208 and the spacer 214 are removed, the upper electrodes 218 and 220 are formed in a portion where the spacer 214 is removed and a portion where the interlayer insulating film 208 is removed. Here, a dielectric film may be further formed before forming the upper electrodes 218 and 220.

At this time, the etching process is performed on the spacer 214 to increase the time of the etching process or to perform an additional anisotropic etching process so that the upper portion of the first single crystal layer 212 is partially etched. Therefore, the upper electrode 218 formed at the portion where the spacer 214 is removed is partially embedded in the upper portion of the first single crystal layer 212. This is to cause a gate induced drain leakage (GIDL) phenomenon in order to improve the writing performance of the DRAM device, and to improve the storage capability of the charge by allowing holes to be injected into the second single crystal layer 216. . The depth at which the upper electrode 218 overlaps with the first single crystal layer 212 for maximizing the above-described effect is preferably 100 kPa to 500 kPa.

As shown in FIG. 4E, a third single crystal layer 222 is formed on the upper electrode 218 and the second single crystal layer 216. Here, the third single crystal layer 222 may be formed by growing by an epitaxial growth method while being doped with N-type. In this case, the third single crystal layer 222 is formed as a seed of the second single crystal layer 216. Since the second single crystal layer is doped with P-type impurities, the third single crystal layer 222 is doped with N-type impurities. In order to reduce the concentration of the P-type impurities and to increase the concentration of the N-type impurities, that is, it is preferable to form the counter doping (couter doping). Subsequently, an interlayer insulating film 224 is formed on the third single crystal layer 222, and a planarization etching process is performed on the interlayer insulating film 224 so that the third single crystal layer 222 is exposed. And a conductive layer 226 on the interlayer insulating film 224. Here, the conductive layer 226 may be used as a collector electrode, and the upper electrode 220 and the conductive layer 226 may be It is preferable to be electrically insulated by the interlayer insulating film 224.

As described above, the present invention forms an NPN storage electrode so that an amplifying capacitor can be implemented not only in a DRAM including a planar gate structure but also in a DRAM including a vertical gate structure, thereby providing sufficient electrostatic capacity even when the height of the storage electrode is lowered. The capacity can be secured and can be easily formed even in a unit cell having a small area by high integration.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. Of the present invention.

Claims (27)

A first single crystal layer formed on the semiconductor substrate;
A second single crystal layer provided on the first single crystal layer;
A first upper electrode disposed on sidewalls of the second single crystal layer and partially embedded in the first single crystal layer;
A second upper electrode connecting the first upper electrode adjacent to each other;
A third single crystal layer connected over the second single crystal layer; And
And a conductive layer connected to an upper portion of the third single crystal layer. The method according to claim 1,
And the first single crystal layer and the third single crystal layer comprise an N-type epitaxial silicon single crystal layer. The method according to claim 1,
And the second single crystal layer comprises a P-type epitaxial silicon single crystal layer. The method according to claim 1,
The conductive layer comprises a collector electrode. The method according to claim 1,
A gate formed on the semiconductor substrate;
A bit line contact plug provided between the gates; And
And a bit line connected to an upper portion of the bit line contact plug and extending in a direction perpendicular to the gate. The method according to claim 1,
And an interlayer insulating film provided on the second upper electrode to electrically insulate the conductive layer. The method according to claim 1,
The semiconductor device according to claim 1, wherein the thickness of the first upper electrode and the first single crystal layer overlaps with each other. The method according to claim 1,
A bit line embedded in the semiconductor substrate;
And a vertical gate provided on the semiconductor substrate. The method according to claim 8,
And the first single crystal layer is provided on the vertical gate. Forming a first single crystal layer on the semiconductor substrate;
Forming a second single crystal layer on the first single crystal layer;
Forming a first upper electrode formed on sidewalls of the second single crystal layer and partially embedded in the first single crystal layer, and a second upper electrode connecting the first upper electrode adjacent to each other;
Forming a third single crystal layer on the second single crystal layer; And
And forming a conductive layer over the third single crystal layer. The method of claim 10,
Before the step of forming the first single crystal layer
Forming a gate on the semiconductor substrate;
Forming a bit line contact plug on the semiconductor substrate between the gates; And
And forming a bit line connected to an upper portion of the bit line contact plug and connected in a direction perpendicular to the gate. The method of claim 11,
Forming the first single crystal layer is
After forming the gate
And growing by an epitaxial growth method in the state doped with N-type impurities using the semiconductor substrate as a seed. The method of claim 11,
Forming the first single crystal layer is
Forming a first interlayer insulating layer on the bit line;
Forming a storage electrode predetermined region to expose the semiconductor substrate; And
And growing by an epitaxial growth method with an N-type impurity doped as a seed by using the semiconductor substrate exposed to the bottom of the storage electrode predetermined region as a seed. The method according to claim 13,
After forming the storage electrode predetermined region
And forming a spacer on sidewalls of the predetermined region of the storage electrode on the first single crystal layer. The method according to claim 14,
Forming the second single crystal layer is
A method of forming a semiconductor device, characterized in that the first single crystal layer is grown by an epitaxial growth method in a state doped with P-type impurities. The method according to claim 14,
After forming the second single crystal layer
And performing a planarization etching process on the second single crystal layer, the spacer, and the first interlayer insulating layer. The method according to claim 14,
Forming the first upper electrode
Removing the spacers;
Etching an upper portion of the first single crystal layer by performing an anisotropic etching process on the removed spacers; And
And embedding an upper electrode material in the portion where the second single crystal layer sidewall and the first single crystal layer are etched. The method of claim 10,
Forming the third single crystal layer is
A method for forming a semiconductor device, characterized in that the second single crystal layer as a seed is grown by an epitaxial growth method while doped with N-type impurities. The method of claim 10,
After forming the third single crystal layer
And forming a second interlayer insulating film on the second upper electrode. The method of claim 10,
Before the step of forming the first single crystal layer
Forming a bit line in the semiconductor substrate; And
Forming a vertical gate on the semiconductor substrate. The method of claim 20,
Forming the first single crystal layer is
Forming a third interlayer insulating film on the vertical gate;
Etching the third interlayer insulating layer to expose the vertical gate to form a storage electrode predetermined region; And
And growing the vertical gate exposed to the bottom of the predetermined region of the storage electrode by an epitaxial growth method with a N-type impurity doped as a seed. 23. The method of claim 21,
After forming the storage electrode predetermined region
And forming a spacer on sidewalls of the predetermined region of the storage electrode on the first single crystal layer. 23. The method of claim 22,
Forming the second single crystal layer is
A method of forming a semiconductor device, characterized in that the first single crystal layer is grown by an epitaxial growth method in a state doped with P-type impurities. 24. The method of claim 23,
After forming the second single crystal layer
And performing a planarization etching process on the second single crystal layer, the spacer, and the third interlayer insulating layer. 27. The method of claim 24,
Forming the first upper electrode
Removing the spacers;
Etching an upper portion of the first single crystal layer by performing an anisotropic etching process on the removed spacers; And
And embedding an upper electrode material in the portion where the second single crystal layer sidewall and the first single crystal layer are etched. The method of claim 20,
Forming the third single crystal layer is
A method for forming a semiconductor device, characterized in that the second single crystal layer as a seed is grown by an epitaxial growth method while doped with N-type impurities. The method of claim 20,
After forming the third single crystal layer
And forming a fourth interlayer insulating film on the second upper electrode.

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