KR20120130984A - Array substrate for liquid crystal display device including insulating layer formed by using soluble material and method of fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate for a liquid crystal display device including an insulating layer formed by using a soluble material and a method for fabricating the same are provided to form a passivation layer of a soluble material including SiO2 and to simplify a manufacturing process. CONSTITUTION: A passivation layer is formed in the upper part of a source electrode(126), a drain electrode and a data line(130). The passivation layer is made of soluble hybrid materials including silicon oxide(SiO2). A sub pattern(150) is formed in the upper part of the passivation layer in each pixel region. The sub pattern is separated from a pixel electrode(142) and a common electrode(144). The sub pattern is connected to a gate extension part(115). The sub pattern is overlapped with a semiconductor layer(124).

Description

Array substrate for liquid crystal display device including insulating layer formed using soluble material and method for manufacturing same

The present invention relates to an array substrate for a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device including an insulating layer formed by using a soluble material including silicon oxide (SiO ₂ ) and a fabrication thereof. It is about a method.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Recently, liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting diodes Various flat panel displays (FPDs), such as organic light emitting diodes (OLEDs), are being utilized.

Among these flat panel display devices, liquid crystal display devices are widely used because they have advantages of miniaturization, light weight, thinness, and low power driving.

The liquid crystal display device includes an array substrate having gate wirings, data wirings, thin film transistors (TFTs), pixel electrodes, and the like, a color filter substrate having black matrices, a color filter layer, a common electrode, etc., an array substrate and a color. It consists of a liquid crystal layer formed between the filter substrate, which will be described with reference to the drawings.

1 is a cross-sectional view of a conventional array substrate for a liquid crystal display device.

As shown in FIG. 1, a gate wiring (not shown), a gate electrode 14 extending from the gate wiring (not shown), and an end portion of the gate wiring (not shown) are connected to an upper portion of the substrate 10. The common pad 18 is formed to be spaced apart from the gate pad electrode 16 and the gate line (not shown).

A gate insulating layer 22 is formed on the gate wiring, the gate electrode 14, the gate pad electrode 16, and the common wiring 18, and the gate insulating layer 22 is made of an inorganic insulating material. .

The semiconductor layer 24 is formed on the gate insulating layer 22 corresponding to the gate electrode 14, and the source electrode 26 and the drain electrode 28 spaced apart from each other are formed on the semiconductor layer 24.

In addition, a data line 30 connected to the source electrode 26 and intersecting the gate line 12 and an data pad electrode connected to an end of the data line 30 are formed on the gate insulating layer 22. 32) is being formed.

The gate electrode 14, the gate insulating layer 22, the semiconductor layer 24, the source electrode 26 and the drain electrode 28 spaced apart from each other form a thin film transistor Tr. .

A passivation layer 34 is formed on the source electrode 26 and the drain electrode 28, the data line 30, and the data pad 32, and the passivation layer 34 forms the drain electrode 28. A drain contact hole 36 to expose the gate pad, a gate pad contact hole 38 to expose the gate pad electrode 16, and a data pad contact hole 40 to expose the data pad electrode 32. .

The gate pad contact hole 38 is formed through the passivation layer 34 and the gate insulating layer 22, and the passivation layer 34 is made of an inorganic insulating material such as silicon nitride (SiNx). .

A pixel electrode 42 connected to the drain electrode 28 through the drain contact hole 36, and a common electrode 44 spaced apart from the pixel electrode 42 in parallel with the passivation layer 34. A gate pad terminal 46 connected to the gate pad electrode 16 through the gate pad contact hole 38 and data connected to the data pad electrode 32 through the data pad contact hole 40. The pad terminal 48 is formed.

In addition, a part of the pixel electrode 42 overlaps the common wiring 18 with the protective layer 34 interposed therebetween, and the common wiring 18 and the pixel electrode 42 overlapping each other and the protective layer interposed therebetween. 34 configures a storage capacitor StgC.

The array substrate for a liquid crystal display device forms a pattern by repeating an photolithographic process including thin film deposition, photoresist coating, exposure, development, etching and photoresist removal. The exposure etching process may be classified based on a mask used in the process.

For example, an array substrate for a liquid crystal display device may include a first mask process of forming the gate wiring 12, the gate electrode 14, the gate pad electrode 16, and the common wiring 18 on the substrate 10. And a second mask process for forming the semiconductor layer 24, the source electrode 26, the drain electrode 28, the data wiring 30, and the data pad electrode 32, the drain contact hole 36, and the gate pad. A third mask process for forming the contact hole 38 and the data pad contact hole 40 and a fourth mask process for forming the pixel electrode 42 and the common electrode 44 may be performed.

In particular, the protective layer 34 may be formed by depositing an inorganic insulating material layer, coating a photoresist layer on the inorganic insulating material layer, exposing the photoresist layer through a mask, and developing the exposed photoresist layer. It is formed through the six steps of develop, etching the inorganic insulating material layer using the developed photoresist layer, stripping the photoresist layer.

As such, the protective layer 34 made of an inorganic insulating material is formed through a complicated step, and in particular, a chemical vapor deposition (CVD) apparatus used for depositing an inorganic insulating material layer is used to secure a vacuum state. There is a problem that the process time is required, and the maintenance cost is high, and this factor causes an increase in the manufacturing cost of the array substrate for the liquid crystal display device.

In addition, since the deposition of the inorganic insulating material layer using the chemical vapor deposition apparatus is performed at a slow deposition rate, there is a problem that the process time for forming the protective layer 34 is further increased.

In addition, the inorganic insulating material is poor in planarization characteristics, so that the protective layer corresponding to the stepped portions of the semiconductor layer 24, the source electrode 26, the drain electrode 28, the data line 30, and the data pad 32 ( There is a problem that a defect occurs in 34).

In addition, a gate line 12 and a data line 30 are formed below the passivation layer 34, and a pixel electrode 42 and a common electrode 44 are formed on the passivation layer 34. In the array substrate for the display device, the gate wiring 12 and the data wiring 30 may overlap with the pixel electrode 42 and the common electrode 44 with the protective layer 34 interposed therebetween to act as a parasitic capacitance. have.

However, since the dielectric constant of silicon nitride (SiNx) constituting the protective layer 34 is about 7.5, the parasitic capacitance in proportion to the dielectric constant of the dielectric between the two electrodes is also a relatively large value. Therefore, there is a problem in that the time constant RC is increased to delay the transmission of the gate signals and the data signals respectively supplied through the gate wiring 12 and the data wiring 30 and to decrease the charging characteristics.

The delay in the gate signal and the data signal transmission and the deterioration of the charging characteristics act as a factor of degrading the image quality of the liquid crystal display.

The present invention provides an array substrate for a liquid crystal display device, which simplifies a manufacturing process, reduces manufacturing cost and manufacturing time, prevents defects in a protective layer due to a step difference in a lower pattern, prevents signal delay, and improves charging characteristics. The purpose is to provide a manufacturing method.

Another object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same, including an soluble protective layer and suppressing an increase in off current of the thin film transistor to improve electrical characteristics of the thin film transistor.

An array substrate for a liquid crystal display device according to the present invention for achieving the above object, the substrate; A gate wiring and a data wiring formed on the substrate to define a pixel region by crossing each other with a gate insulating film interposed therebetween; A common wiring formed of the same material on the same layer in parallel with the gate wiring; A gate electrode branched from the gate wiring, and a gate extension extending from the gate electrode; A semiconductor layer formed on the gate insulating layer to correspond to the gate electrode, and a source electrode and a drain electrode formed to be spaced apart from each other on the semiconductor layer; A protective layer formed on the source electrode, the drain electrode, and the data line and made of a soluble organic-inorganic hybrid insulating material including silicon oxide (SiO ₂ ); A gate electrode formed on the passivation layer for each of the pixel regions, the pixel electrode connected to the drain electrode, the common electrode alternately with the pixel electrode, and connected to the common wiring, and spaced apart from the pixel electrode and the common electrode; And an auxiliary pattern connected to the semiconductor layer and overlapping the semiconductor layer.

The soluble organic-inorganic hybrid insulating material including the silicon oxide (SiO ₂ ) includes a soluble insulating material, a crosslinking agent, and a photoinitiator based on silicon oxide (SiO ₂ ).

A gate pad electrode connected to an end of the gate line; A data pad electrode connected to an end of the data line; A gate pad terminal connected to the gate pad electrode; The apparatus further includes a data pad terminal connected to the data pad electrode.

The protective layer includes a drain contact hole exposing the drain electrode, a data pad contact hole exposing the data pad electrode, a gate contact hole exposing the gate extension in the protective layer and the gate insulating layer, and the gate. A gate pad contact hole exposing a pad electrode and a common contact hole exposing the common wiring, the pixel electrode contacts the drain electrode through the drain contact hole, and the auxiliary pattern is formed through the gate contact hole Contact with the gate extension, the gate pad terminal contacts the gate pad electrode through the gate pad contact hole, and the data pad terminal contacts the data pad electrode through the data pad contact hole. .

In the method of manufacturing an array substrate for a liquid crystal display device according to the present invention, a gate wiring parallel to the gate wiring is formed on a substrate on which a pixel region is defined, and the gate electrode and the gate electrode branched from the gate wiring in the pixel region. Forming a gate extension extending in the; Forming a gate insulating film over the gate wiring, the common wiring, the gate electrode, and the gate extension; Forming a data line over the gate insulating layer to define the pixel area crossing the gate line, a semiconductor layer corresponding to the gate electrode, and a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; Forming a protective layer made of a soluble organic-inorganic hybrid insulating material including silicon oxide on the source and drain electrodes and the data line; A pixel electrode connected to the drain electrode for each of the pixel regions, a common electrode alternately connected to the pixel electrode, connected to the common wiring, spaced apart from the pixel electrode and the common electrode, and connected to the gate extension on the passivation layer; And forming an auxiliary pattern corresponding to the semiconductor layer.

The forming of the protective layer may include coating a soluble organic-inorganic hybrid insulating material including the silicon oxide to form a soluble insulating material layer on the source electrode, the drain electrode, and the data line; Exposing the soluble insulating material layer through an exposure mask; Developing the exposed soluble insulating material layer; Curing the developed soluble insulating material layer; Etching the gate insulating layer using the heat-treated soluble insulating material layer as an etching mask.

The forming of the protective layer includes: pre-baking the soluble insulating material layer prior to exposing the soluble insulating material layer; And hard-baking the soluble insulating material layer after developing the soluble insulating material layer.

The forming of the gate line and the common line may include forming a gate pad electrode connected to the gate line end, and the forming of the data line may include forming a data pad electrode connected to the data line end. The forming of the protective layer may include forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode, wherein the pixel electrode and the common electrode are formed. And forming the auxiliary pattern further comprises forming a gate pad terminal contacting the gate pad electrode through the gate pad contact hole and a data pad terminal contacting the data pad electrode through the data pad contact hole. Include.

In the array substrate for a liquid crystal display device and the method for manufacturing the same according to the present invention, a protective layer is formed using a soluble hybrid material containing silicon oxide (SiO ₂ ), thereby simplifying the manufacturing process and reducing the manufacturing cost and It reduces the manufacturing time, prevents the defect of the protective layer due to the step of the lower pattern, has the effect of preventing signal delay and improving the charging characteristics.

In addition, a transparent pattern is formed of the same material forming the pixel electrode and connected to the gate wiring through the gate contact hole on the upper portion of the protective layer in response to the thin film transistor, thereby suppressing the off current increase of the thin film transistor, which may occur when the soluble material is applied. It has the effect of preventing the electrical characteristics of the thin film transistor from deteriorating.

1 is a cross-sectional view of a conventional array substrate for a liquid crystal display device.
2 is a plan view of an array substrate for a liquid crystal display according to a first embodiment of the present invention.
3 is a cross-sectional view of a portion cut along the cutting line III-III of FIG.
4A to 4D are plan views illustrating manufacturing steps of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.
Figures 5a to 5g is a cross-sectional view of the manufacturing step for the portion cut along the cutting line III-III of FIG.
6 is a voltage-current characteristic curve of a thin film transistor provided on an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and an auxiliary pattern is not provided, and a liquid crystal having a soluble organic-inorganic hybrid insulating material having a protective layer. Graph showing voltage-current characteristic curve of array substrate for display device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

2 is a plan view of an array substrate for a liquid crystal display device according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of the array substrate for a liquid crystal display device according to an embodiment of the present invention, and FIG. It is sectional drawing about the cut part. For convenience of description, a region in which the thin film transistor Tr, which is a switching element, is formed in each pixel region P is defined as a switching region TrA.

As shown, a low resistance metal material on the transparent insulating substrate 110, for example, aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), molybdenum (MoTi) The gate wiring 112 and the common wiring 118 are formed side by side with one or two or more materials and extend in one direction and are spaced at regular intervals.

In this case, a gate pad electrode 116 is formed to be connected to an end of the gate line 112, and although not shown in the drawing, all ends of the common line 118 are connected by an auxiliary common line (not shown). The common pad electrode (not shown) is formed at an end of the auxiliary common wiring (not shown).

In addition, the switching region TrA extends from the gate line 112 and includes a gate electrode 114, and branches from the gate electrode 114 to provide a gate extension 115.

In addition, an inorganic insulating material may be formed on the gate wiring 112, the gate electrode 114, the gate extension 115, the gate pad electrode 116, the common wiring 118, and the common pad electrode (not shown). A gate insulating film 122 made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is formed.

In addition, a semiconductor layer 124 is formed on the gate insulating layer 122 corresponding to the gate electrode 114 in the switching region TrA, and a source electrode spaced apart from each other on the semiconductor layer 124. 126 and the drain electrode 128 are formed.

In this case, the semiconductor layer 124 includes an active layer 124a made of pure amorphous silicon and an ohmic contact layer 124b formed of impurity amorphous silicon and spaced apart from each other.

In addition, a data line 130 is formed on the gate insulating layer 122 to be connected to the source electrode 126 and cross the gate line 112 to define the pixel region P. The data pad electrode 132 connected to the end of the 130 is formed.

In this case, first and second semiconductor patterns 125a and 125b formed of the same layer and the same material as the semiconductor layer 124 are formed under the data line 130 and the data pad electrode 132. The formation of the first and second semiconductor patterns 125a and 125b under the data line 130 and the data pad electrode 132 is due to a manufacturing process, and the semiconductor layer 124 and the data line 130 are connected to each other. It may be omitted when a manufacturing method of patterning by performing another mask process is performed.

Meanwhile, the gate electrode 114, the gate insulating layer 122, the semiconductor layer 124, and the source electrode 126 and the drain electrode 128 spaced apart from each other are sequentially stacked in the switching region TrA. The transistor Tr is constituted.

In addition, a passivation layer 134 is formed on the source electrode 126, the drain electrode 128, the data line 130, and the data pad electrode 132, and the passivation layer 134 is the drain. A drain contact hole 136 exposing the electrode 128, a gate contact hole 137 exposing the gate extension 115, a gate pad contact hole 138 exposing the gate pad electrode 116, and And a data pad contact hole 140 exposing the data pad electrode 132.

The gate contact hole 137 and the gate pad contact hole 138 are formed through the gate insulating layer 122 provided below the protective layer 134.

In this case, the protective layer 134 is formed using a soluble organic / inorganic hybrid insulating material containing silicon dioxide (SiO ₂ ).

The soluble organic-inorganic hybrid insulating material including the silicon oxide (SiO ₂ ) is a silicon oxide (SiO ₂ ) based soluble insulating material using a solvent such as propylene glycol monomethyl ether acetate (PGMEA). A cross-linker and a photoinitiator may be added to the SiO ₂ base soluble insulating material.

Availability containing such a silicon oxide (SiO ₂₎ organic-inorganic hybrid insulating material roneun is composed of a silicon oxide (SiO ₂₎ the main chain of the base (SiO ₂ base main chain), a monomer (monomer) methyl siloxane (methylsiloxane), vinyl A siloxane (vinylsiloxane), phenylsiloxane (phenylsiloxane) series may be used.

At this time, silicon (Si) is bonded to the radical group consisting of alkyl (alkyl) including methyl (vinyl), vinyl (vinyl), phenyl (organic) in addition to oxygen (O) as an inorganic material, the corresponding insulation The material is called an organic-inorganic hybrid insulating material.

The soluble organic-inorganic hybrid insulating material including the silicon oxide (SiO ₂ ) may have a refractive index in the range of 1.51 to 1.56 and a dielectric constant in the range of 3.8 to 4.3.

The protective layer 134 is, soluble organic-inorganic hybrid layer of insulating material exposed containing soluble organic-inorganic hybrid layer of insulating material is applied (coating), silicon oxide (SiO ₂₎ through a mask containing a silicon oxide (SiO ₂₎ ( exposure), development of a soluble organic-inorganic hybrid insulation layer comprising exposed silicon oxide (SiO ₂ ), curing of a soluble organic-inorganic hybrid insulation layer containing developed silicon oxide, heat-treated silicon oxide ( The gate insulating layer 116 may be formed through five steps of etching using the soluble organic-inorganic hybrid insulating material layer including SiO ₂ ).

More specifically, pre-baking before exposure and hard-baking after development may proceed, and the hard-baking may proceed for a longer time at a higher temperature than pre-baking.

As described above, the protective layer 134 using the soluble organic-inorganic hybrid insulating material including silicon oxide (SiO ₂ ) may have fewer steps than the protective layer (34 in FIG. 1) formed by depositing conventional silicon nitride (SiNx). Since it is formed through, the process can be simplified.

In addition, since the soluble organic-inorganic hybrid insulating material containing silicon oxide (SiO ₂ ) is coated in an atmosphere of normal temperature using a coating device such as a spin coater or a slit coater, There is no need to secure a vacuum, manufacturing time is shortened, and manufacturing costs can be reduced by relatively low maintenance costs.

In addition, defects in the protective layer 134 due to the lower step may be prevented by excellent planarization characteristics of the soluble organic-inorganic hybrid insulating material including silicon oxide (SiO ₂ ).

Meanwhile, a pixel electrode 142 connected to the drain electrode 128 through the drain contact hole 136 on the protective layer 134 made of a soluble organic-inorganic hybrid insulating material including silicon oxide (SiO ₂ ). ) And a common electrode 144 spaced apart from the pixel electrode 142 in parallel and connected through the common wiring 118 and the common contact hole 139.

In this case, an auxiliary pattern 150 formed of the same material as the material forming the pixel electrode 142 is formed in the switching region TrA by contacting the gate extension 115 through the gate contact hole 137. It is characteristic that there is.

The auxiliary pattern 150 is formed to cover the active layer 124a exposed between the thin film transistor Tr and more precisely between the source electrode 126 and the drain electrode 128. In addition, since the same voltage as that of the gate voltage applied to the gate electrode 114 is applied to the auxiliary pattern 150, the same gate voltage is also applied to the active layer 124a to the upper and lower portions thereof to form a channel region. As a result, the phenomenon that the off current I _off characteristic curve of the thin film transistor Tr shifts upward is suppressed.

A gate pad terminal 146 connected to the gate pad electrode 116 through the gate pad contact hole 138 and the data pad electrode through the data pad contact hole 140 on the passivation layer 134. A data pad terminal 148 connected to the 132 is formed.

A portion of the pixel electrode 142 is formed to overlap the common wiring 118 with the protective layer 134 interposed therebetween, such that the common wiring 118 and the pixel electrode 142 overlap each other. The protective layer 134 interposed therebetween forms a storage capacitor StgC.

In addition, in order to prevent light leakage through the edge of each pixel region P, a common electrode (hereinafter, referred to as the outermost common electrode 144a) disposed at the edge of the pixel region P may be connected to the data line 130. It may overlap partially, and this overlap may act as a kind of parasitic capacitance.

At this time, the dielectric constant (range of about 3.8 to 4.3) of the soluble organic-inorganic hybrid insulating material including silicon oxide (SiO ₂ ) is lower than the dielectric constant (about 7.5) of silicon nitride (SiNx). _The array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention having a protective layer 134 made of a soluble organic-inorganic hybrid insulating material including ₂ ) includes the outermost common electrode 144 and the data line 130. And parasitic capacitance generated by the protective layer 134 therebetween, and as a result, delay of various signals and deterioration of charging characteristics of various wirings can be prevented.

In addition, the array substrate for a liquid crystal display according to the exemplary embodiment of the present invention is connected to the protective layer 134 corresponding to the thin film transistor Tr through a gate extension 115 and a gate contact hole 137. The auxiliary material 150 is made of the same material constituting the pixel electrode 142 to suppress an increase in the off current of the thin film transistor Tr, which may be caused by the provision of the protective layer 134 made of a soluble insulating material. It is characterized by having.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings.

4A to 4D are plan views illustrating manufacturing steps of an array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention, and FIGS. 5A to 5G illustrate manufacturing steps of a part cut along the cutting line III-III of FIG. 2. It is a cross section.

As shown in FIGS. 4A and 5A, the deposition of the first metal film on the transparent insulating substrate 110, the application of the photoresist, the development of the exposed and exposed photoresist using an exposure mask, the etching of the first metal film and the photo By performing a first mask process including a strip of resist, the gate wiring 112 and the gate pad electrode 116 extending in one direction on the substrate 110 and the gate wiring 112 are common to be spaced apart from each other. The wiring 118 is formed.

In this case, although not shown in the drawing, an auxiliary common wiring (not shown) connecting one end of the common wiring 118 and a common pad electrode (not shown) connected to an end thereof are formed.

In addition, a gate electrode 114 is formed in the switching region TrA on the substrate 110 in a form branched from the gate wiring 112, and at the same time, extends from the gate electrode 114 into the pixel region P. A gate extension 115 is formed.

In this case, the gate wiring 112 and the gate pad electrode 116, the common wiring 118, the auxiliary common wiring (not shown), the common pad electrode (not shown), the gate electrode 114 and the gate extension part ( 115 is made of a low-resistance metal material, such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), molybdenum (MoTi), or a single material. It can be layered or multilayered.

Next, as shown in FIGS. 4B and 5B, the gate wiring 112 and the gate pad electrode 116, the gate electrode 114 and the gate extension 115, the common wiring 118 and the auxiliary common wiring ( The gate insulating layer 122 is formed by depositing an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) over the common pad electrode (not shown) and the common pad electrode (not shown).

Subsequently, the pure amorphous silicon layer, the impurity amorphous silicon layer and the second metal film are deposited on the gate insulating layer 122, the photoresist is applied, exposed and developed, the etching of the pure and impurity amorphous silicon layer and the second metal film and the photoresist are performed. Through a second mask process including a strip, a data line 130 defining a pixel region P intersecting the gate line 112 on the gate insulating layer 122 and a data pad electrode connected to an end portion thereof. 132 is formed, and at the same time, a semiconductor layer including an active layer 124a of pure amorphous silicon and an ohmic contact layer 124b of impurity amorphous silicon in the switching region TrA and sequentially stacked on the gate insulating layer 122. 124 and the source electrode 126 and the drain electrode 128 spaced apart from each other.

In this case, the exposure mask used in the second mask process includes a transmission area, a semi-transmission area, and a blocking area.

The transflective region of the exposure mask corresponds to the active layer 124a exposed between the source electrode 126 and the drain electrode 128, and the blocking region is the source electrode 126 and the drain electrode 128. ), The exposure mask is positioned so as to correspond to the data line 130 and the data pad 132, and then exposed, and the development of the exposed photoresist, the etching of the second metal film, and the photoresist strip are performed. The data line 130, the data pad electrode 132, and the source and drain electrodes 126 and 128 spaced apart from the semiconductor layer 124 may be formed.

In this manner, a single mask process is performed to simultaneously form the semiconductor layer 124 and the data wiring 130, thereby forming the same material forming the semiconductor layer 124 under the data wiring 130 and the data pad electrode 132. First and second semiconductor patterns 125a and 125b are formed.

The gate electrode 114, the gate insulating layer 122, the semiconductor layer 124, and the source electrode 126 and the drain electrode 128 spaced apart from each other are sequentially stacked in the switching region TrA. Phosphorus thin film transistor (Tr) is formed.

Meanwhile, the data line 130, the data pad electrode 132, the source electrode 126, and the drain electrode 128 may also have a low resistance metal material such as aluminum (Al) and an aluminum alloy ( AlNd), copper (Cu), copper alloy, molybdenum (Mo), molybdenum (MoTi) of any one or two or more of the materials to form a single layer or multilayer structure.

As shown in FIGS. 4C and 5C, coating, exposure and development of soluble organic / inorganic hybrid insulating materials comprising silicon dioxide (SiO ₂ ) The protective layer 134 is formed on the source electrode 126, the drain electrode 128, the data line 130, and the data pad 132 through a third mask process including a developer.

That is, by applying a soluble organic-inorganic hybrid insulating material containing silicon oxide (SiO ₂ ) to form a soluble insulating material film, by placing a mask on top of the soluble insulating material film to expose, and then developing the exposed soluble insulating material film, The protective layer 134 may be formed.

The protective layer 134 includes a drain contact hole 136, a gate contact hole 137, a gate pad contact hole 138, and a data pad contact hole 140. In this step, the drain contact hole is formed. 136 and data pad contact hole 140 expose only drain electrode 128 and data pad electrode 132, respectively.

Thus, the gate contact hole 137 and the gate pad contact hole 138 are formed only in the protective layer 134 to expose the corresponding gate insulating layer 122, and the lower gate extension 115 and the gate pad electrode ( 116 is in a state covered by the gate insulating film 122.

Here, the soluble inorganic free between the coating and exposure of the mixed-insulating materials including silicon oxide (SiO ₂₎ - to proceed further baking (pre-baking) step, and the availability, including the silicon oxide (SiO ₂₎ After development of the organic-inorganic hybrid insulating material, a hard-baking step may be further performed.

Next, as illustrated in FIG. 5D, the protective layer 134 made of a soluble organic-inorganic hybrid insulating material including silicon oxide (SiO ₂ ) is cured.

The heat treatment is a process for stabilizing and curing the protective layer 134 by completely removing the solvent of the soluble organic-inorganic hybrid insulating material including the silicon oxide (SiO ₂ ) constituting the protective layer 134, the oven ( in a heat treatment apparatus such as an oven or furnace, etc., at a temperature ranging from about 200 ° C. to about 350 ° C. under an atmospheric pressure of an inert gas atmosphere.

Next, as shown in FIG. 5E, the gate insulating layer 122 exposed through the gate contact hole 137 and the gate pad contact hole 138 is etched using the heat-treated protective layer 134 as an etching mask. The gate extension 115 and the gate pad electrode 116 are respectively exposed.

For example, the gate insulating layer 122 made of an inorganic insulating material may be removed by dry etching, and through this step, the gate contact hole 137 and the gate pad contact hole 138 may be removed. Formed on the passivation layer 134 and the gate insulating layer 122, and the gate extension 115 and the gate pad electrode 116 are exposed through the gate contact hole 137 and the gate pad contact hole 138, respectively. .

On the other hand, unlike the general photoresist removed after etching, the protective layer 134 used as an etching mask for etching the gate insulating layer 122 has an inherent function of preventing an electrical short between wirings and protecting a lower pattern. It is characterized by not being removed to perform.

Therefore, the process of forming the protective layer 134 using a soluble organic-inorganic hybrid insulating material containing silicon oxide (SiO ₂ ) is made of five steps of coating, exposing, developing, heat treatment, and etching the gate insulating layer 122. The process may be simpler than the conventional process of forming a protective layer (34 in FIG. 1), which includes six steps of depositing an inorganic insulating material, applying a photoresist, developing an exposure, etching an inorganic insulating material, and removing a photoresist. By eliminating the use of chemical vapor deposition apparatuses, manufacturing costs and manufacturing time can be reduced.

Next, as shown in FIGS. 4D and 5F, through the fourth mask process including the deposition of the transparent conductive film, the application of the photoresist, the exposure and development, the etching of the transparent conductive film, and the removal of the photoresist, each pixel region ( The pixel electrode 142 and the common electrode 144 are alternately formed on the passivation layer 134 in the upper portion of the protective layer 134, and the auxiliary pattern 150 is formed at the same time corresponding to the switching region TrA, The gate pad terminal 146 and the data pad terminal 148 are formed in the non-display area.

The pixel electrode 142 is connected to the drain electrode 128 through the drain contact hole 136, and the common electrode 144 is spaced apart from each other in parallel with the pixel electrode 142 and alternately disposed. The auxiliary pattern 150 is connected to the gate extension 115 through the gate contact hole 137.

In addition, the gate pad terminal 146 is connected to the gate pad electrode 116 through the gate pad contact hole 138, and the data pad terminal 148 is connected to the data pad contact hole 140 through the gate pad contact hole 138. It is connected to the data pad electrode 132.

A portion of the pixel electrode 142 overlaps the common wiring 118 with the protective layer 134 interposed therebetween, thereby overlapping the common wiring 118 and the pixel electrode 142 that overlap each other. The interlayer protection layer 134 forms a storage capacitor StgC.

As described above, in the array substrate for a liquid crystal display according to the exemplary embodiment of the present invention, five steps of coating, exposing, developing, heat treatment, and etching the gate insulating layer 122 including a soluble organic-inorganic hybrid insulating material including silicon oxide (SiO ₂ ) are performed. Since the passivation layer 134 is formed through the passivation layer, the passivation layer (34 in FIG. 1) is formed through six steps of deposition of an inorganic insulation material, application of photoresist, exposure, development, etching of the inorganic insulation material, and removal of the photoresist. The process is simplified compared to the conventional forming, and manufacturing cost and manufacturing time are reduced.

In addition, the defect of the protective layer 134 due to the step difference of the lower pattern is prevented by the excellent planarization characteristics of the soluble organic-inorganic hybrid insulating material including silicon oxide (SiO ₂ ).

In addition, the protective layer 134 is formed of a soluble organic-inorganic hybrid insulating material including silicon oxide having a relatively low dielectric constant (about 3.8 to about 4.3) than the inorganic insulating material, thereby minimizing parasitic capacitance to delay a signal. And the charging characteristics of the various wirings can be improved.

In addition, the array substrate for a liquid crystal display device according to the embodiment of the present invention is a thin film transistor (Tr) such as an off current increase by using a soluble organic-inorganic hybrid insulating material including silicon as the protective layer 134. Although the deterioration of electrical characteristics may occur, the auxiliary pattern 150 contacting the gate extension 115 connected to the gate electrode 114 to cover the thin film transistor Tr may be turned off by forming an upper portion of the protective layer 134. It is characterized by being able to suppress an increase in off current.

6 is a voltage-current characteristic curve of a thin film transistor provided on an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and an auxiliary pattern is not provided, and a liquid crystal having a soluble organic-inorganic hybrid insulating material having a protective layer. A graph showing a voltage-current characteristic curve of an array substrate for a display device.

As shown, in the comparative example, the off current is shown to be about 1E-12 to 1E-9A in the range less than 0V, but in the embodiment of the present invention, the off current is in the range less than 0V in the range of 1E-13 to 1E. It can be seen that it is about -10A.

Accordingly, it can be seen that an embodiment of the present invention having an auxiliary pattern covering a thin film transistor and applying a gate voltage is reduced compared to a comparative example in which the auxiliary pattern covering a thin film transistor is not formed.

The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the present invention.

110: substrate 112: gate wiring
114: gate electrode 115: gate extension
116: gate pad electrode 118: common wiring
122: gate insulating film 124: semiconductor layer
124a: active layer 124b: ohmic contact layer
125a: first semiconductor pattern 125b: second semiconductor pattern
130: data wiring 132: data pad electrode
134: protective layer 136: drain contact hole
137: gate contact hole 138: gate pad contact hole
140: data pad contact hole 142: pixel electrode
144: common electrode 146: gate pad terminal
148: data pad terminal StgC: storage capacitor
Tr: thin film transistor

Claims (8)

A substrate;
A gate wiring and a data wiring formed on the substrate to define a pixel region by crossing each other with a gate insulating film interposed therebetween;
A common wiring formed of the same material on the same layer in parallel with the gate wiring;
A gate electrode branched from the gate wiring, and a gate extension extending from the gate electrode;
A semiconductor layer formed on the gate insulating layer to correspond to the gate electrode, and a source electrode and a drain electrode formed to be spaced apart from each other on the semiconductor layer;
A protective layer formed on the source electrode, the drain electrode, and the data line and made of a soluble organic-inorganic hybrid insulating material including silicon oxide (SiO ₂ );
A gate electrode formed on the passivation layer for each of the pixel regions, the pixel electrode connected to the drain electrode, the common electrode alternately with the pixel electrode, and connected to the common wiring, and spaced apart from the pixel electrode and the common electrode; An auxiliary pattern connected to the semiconductor layer and overlapping the semiconductor layer
Array substrate for a liquid crystal display device comprising a.
The method of claim 1,
The soluble organic-inorganic hybrid insulating material includes an array substrate for a liquid crystal display device including a silicon oxide (SiO ₂₎ based on the availability of an insulating material, cross-linking agent and a photoinitiator comprising the silicon oxide (SiO _2).
The method of claim 1,
A gate pad electrode connected to an end of the gate wiring;
A data pad electrode connected to an end of the data line;
A gate pad terminal connected to the gate pad electrode;
A data pad terminal connected to the data pad electrode
Array substrate for a liquid crystal display device further comprising.
The method of claim 3, wherein
The protective layer includes a drain contact hole exposing the drain electrode and a data pad contact hole exposing the data pad electrode.
The protective layer and the gate insulating layer may include a gate contact hole exposing the gate extension, a gate pad contact hole exposing the gate pad electrode, and a common contact hole exposing the common wiring.
The pixel electrode contacts the drain electrode through the drain contact hole, the auxiliary pattern contacts the gate extension through the gate contact hole, and the gate pad terminal contacts the gate pad through the gate pad contact hole. And an electrode in contact with the electrode, wherein the data pad terminal contacts the data pad electrode through the data pad contact hole.
Forming a common wiring parallel to the gate wiring on the substrate on which the pixel region is defined, and forming a gate electrode branched from the gate wiring and a gate extension extending from the gate electrode in the pixel region;
Forming a gate insulating film over the gate wiring, the common wiring, the gate electrode, and the gate extension;
Forming a data line over the gate insulating layer to define the pixel area crossing the gate line, a semiconductor layer corresponding to the gate electrode, and a source electrode and a drain electrode spaced apart from each other on the semiconductor layer;
Forming a protective layer made of a soluble organic-inorganic hybrid insulating material including silicon oxide on the source and drain electrodes and the data line;
A pixel electrode connected to the drain electrode for each of the pixel regions, a common electrode alternately connected to the pixel electrode, connected to the common wiring, spaced apart from the pixel electrode and the common electrode, and connected to the gate extension on the passivation layer; And forming an auxiliary pattern corresponding to the semiconductor layer.
Method of manufacturing an array substrate for a liquid crystal display device comprising a.
The method of claim 5, wherein
Forming the protective layer,
Coating a soluble organic-inorganic hybrid insulating material including the silicon oxide to form a soluble insulating material layer on the source electrode, the drain electrode and the data line;
Exposing the soluble insulating material layer through an exposure mask;
Developing the exposed soluble insulating material layer;
Curing the developed soluble insulating material layer;
Etching the gate insulating layer using the heat-treated soluble insulating material layer as an etching mask
Method of manufacturing an array substrate for a liquid crystal display device comprising a.
The method according to claim 6,
Forming the protective layer,
Pre-baking the soluble insulating material layer prior to exposing the soluble insulating material layer;
Hard-baking the soluble insulating material layer after developing the soluble insulating material layer
Method of manufacturing an array substrate for a liquid crystal display device further comprising.
The method of claim 5, wherein
The forming of the gate line and the common line may include forming a gate pad electrode connected to an end of the gate line.
Forming the data line includes forming a data pad electrode connected to an end of the data line,
The forming of the protective layer may include forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode.
The forming of the pixel electrode, the common electrode and the auxiliary pattern may include a gate pad terminal contacting the gate pad electrode through the gate pad contact hole, and a data pad terminal contacting the data pad electrode through the data pad contact hole. Forming steps
Method of manufacturing an array substrate for a liquid crystal display device further comprising.

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