KR20120129637A - Image display device and driving method of thereof - Google Patents

Abstract

PURPOSE: An image display device and a driving method thereof are provided to store an FRC correcting pattern commonly applied to a two-dimensional mode and a three-dimensional mode in a memory and to apply the FRC correcting pattern in a two-dimensional mode. CONSTITUTION: An image display device stores an FRC(Frame Rate Control) correcting pattern in a memory(S10). In case a current driving mode is a three-dimensional mode, the image display device extends correcting values of the FRC correcting pattern through repetitive reading of the FRC correcting pattern(S20,S30). The image display device adds the extended correcting value to input image data of a three-dimensional image(S40). In case a current driving mode is a two-dimensional mode, the image display device adds correcting values of the FRC correcting pattern to the input image data of a two-dimensional image(S50). [Reference numerals] (AA) Start; (BB) End; (S10) Storing an FRC(Frame Rate Control) correcting pattern in a memory; (S30) Extending correcting values of the FRC correcting pattern; (S40) Adding the extended correcting value to input image data of a three-dimensional image; (S50) Adding correcting values of the FRC correcting pattern to the input image data of a two-dimensional image

Description

Image display device and its driving method {IMAGE DISPLAY DEVICE AND DRIVING METHOD OF THEREOF}

The present invention relates to an image display device capable of selectively implementing a two-dimensional plane image (hereinafter referred to as '2D image') and a three-dimensional stereoscopic image (hereinafter referred to as '3D image').

With the development of various contents and the development of circuit technology, image display devices can selectively implement 2D and 3D images. The image display device uses a stereoscopic technique or an autostereoscopic technique to implement a 3D image.

The binocular parallax method uses a parallax image of the left and right eyes with a large stereoscopic effect, and there are glasses and no glasses, both of which are put to practical use. In the non-eyeglass system, an optical plate such as a parallax barrier for separating the optical axis of left and right parallax images is installed in front of or behind the display screen. The spectacle method displays left and right parallax images having different polarization directions on a display panel, and implements a stereoscopic image using polarized glasses or liquid crystal shutter glasses.

Among them, the polarizing glasses method includes a patterned retarder 2 attached to the display panel 1 as shown in FIG. 1. In the polarizing glasses method, the left eye image data L and the right eye image data R are alternately displayed on the display panel 1 in units of horizontal lines, and the polarization incident on the polarizing glasses 3 through the patterned retarder 2 is performed. Switch the characteristic. Through this, the polarized glasses method can realize a 3D image by spatially dividing the left eye image and the right eye image.

Meanwhile, a frame rate control (FRC) technology is known for 2D-only image display devices. FRC is a method of uniformly distributing a small number of colors, and was developed for the purpose of expressing a larger number of colors than the original colors (that is, increasing the color depth). The FRC is designed to express colors of 8 bits (or 10 bits) by using a display panel driven by 6 bits (or 8 bits), and includes dithering technology. Dithering means spatially distributing weights over a plurality of pixels as shown in FIG. 2 to express an intermediate color. The FRC is a spatial concept that if a pixel is small enough, the two colors (the color of the weighted pixel and the unweighted pixel) appear to be neutral, and the two colors (the color of the weighted pixel) By using a temporal concept that alternating weights of unweighted pixels) appear alternately at high enough speeds, they also appear neutral.

Existing 2D-only image display apparatuses distribute a FRC compensation pattern of a predetermined size (for example, 4 (number of pixels) x 4 (number of pixels)) whose weights are spatially dispersed, as shown in FIG. By compensating the input image data with gray scales smaller than the weight, more colors than the original colors can be expressed.

The FRC technology has been applied to a recent polarized glasses type image display device that selectively implements 3D images. However, in the polarization glasses type image display apparatus, since the FRC compensation pattern applied to the image made for the left / right view is reduced to half the size compared to the 2D driving, it is difficult to apply the existing FRC technology as it is. This is because, as mentioned above, the image display apparatus employing the polarizing glasses method alternately displays the left eye image and the right eye image in units of horizontal lines during 3D driving.

In other words, assuming that the existing FRC compensation pattern is repeatedly designed to have a size of 4 (the number of pixels) x 4 (the number of pixels) as shown in FIG. 3, 4 (the number of pixels) x 4 (the length) in 2D driving. The desired image quality can be realized by applying the FRC compensation pattern of the number of pixels as it is, but in 3D driving, the FRC compensation pattern of 4 (the number of pixels) x 2 (the number of pixels) is applied to the desired image quality. Difficult to implement If the size of the FRC compensation pattern applied to the monocular (left eye or right eye) image is reduced, the gray scale of the intermediate color to be expressed is inevitably deteriorated.

Of course, a case in which the 3D FRC compensation pattern is stored in advance in the memory separately from the 2D FRC compensation pattern may be considered. However, in this case, a very large memory is required, and thus it is difficult to adopt the manufacturing cost.

Accordingly, it is an object of the present invention to provide an image display apparatus and a driving method thereof that enable the application of FRC technology without deterioration of image quality not only during 2D driving but also during 3D driving.

Another object of the present invention is to provide an image display apparatus and a method of driving the same, which allow the FRC technology to be applied with the same level of image quality as 2D driving even during 3D driving without increasing the memory capacity.

In order to achieve the above object, an image display apparatus according to an embodiment of the present invention includes a display element for displaying a 2D image and a 3D image; A patterned retarder bonded to the display element to transmit a left eye image of the 3D image with first polarization and a right eye image of the 3D image with second polarization; Polarizing glasses including a left eye filter transmitting the first polarization and a right eye filter transmitting the second polarization; A memory for storing an FRC compensation pattern commonly applied to the input image data of the 2D image and the 3D image; And adding compensation values of the FRC compensation pattern to input image data of the 2D image, and extending compensation values of the FRC compensation pattern when the input image data of the 3D image is input to expand the compensation values of the 3D image. An FRC processing circuit is added to the input video data.

The FRC processing circuit may include: a first line counter for counting the FRC compensation pattern in units of one line; A second line counter for counting the FRC compensation pattern in units of two lines; A counter selection controller for outputting a selection signal having a different logic value in a 2D mode for implementing the 2D image and a 3D mode for implementing the 3D image according to a mode signal; A multiplexer which selects an output of the first line counter and an output of the second line counter in response to the selection signal and outputs the result of the counting result; An FRC compensation value for adding compensation values of the FRC compensation pattern to the input image data of the 2D image in the 2D mode and adding extended compensation values of the FRC compensation pattern to the input image data of the 3D image in the 3D mode. Application part; And supplying compensation values of an FRC compensation pattern read from the memory in the 2D mode to the FRC compensation value applying unit in response to the coefficient result input from the multiplexer, and reading the FRC compensation pattern read from the memory in the 3D mode. And an FRC compensation value modulator for extending the compensation values of and supplying the FRC compensation value application unit.

In the 3D mode, the FRC compensation value modulator compensates the FRC compensation pattern by repeatedly reading the compensation values of one line from the memory twice in the FRC compensation pattern and repeatedly supplying the same compensation values to the FRC compensation value applying unit. Expand the values.

In addition, according to an embodiment of the present invention, a display device for displaying a 2D image and a 3D image, bonded to the display device to transmit the left eye image of the 3D image with the first polarization, and the right eye image of the 3D image with the second polarization A method of driving an image display apparatus including a patterned retarder for transmitting by a polarization glasses and a left eye filter for transmitting the first polarization and a right eye filter for transmitting the second polarization, the method comprising: (A) the 2D image; Storing an FRC compensation pattern commonly applied to the input image data of the 3D image in a memory; (B) adding compensation values of the FRC compensation pattern to the input image data of the 2D image; And (C) adding the extended compensation values to the input image data of the 3D image by expanding the compensation values of the FRC compensation pattern when the input image data of the 3D image is input.

In the step (C), the compensation values of the FRC compensation pattern are expanded by repeatedly reading out one line of compensation values from the memory twice in the FRC compensation pattern.

The image display device and its driving method according to the present invention store the FRC compensation pattern commonly applied to the 2D mode and the 3D mode in a memory, and then apply the FRC compensation pattern as it is in the 2D mode, and in the 3D mode, the FRC compensation pattern. Repeated reading of the FRC compensation pattern is extended by 2 times in the vertical direction.

Accordingly, the present invention can apply the FRC technology with the same level of image quality as 2D driving even in 3D driving without increasing the memory capacity.

1 is a view showing a polarizing glasses method for implementing a 3D image.
2 shows an example of an FRC compensation pattern.
3 is a view for explaining a problem when applying a conventional FRC compensation technology to a polarizing glasses image display device.
4 and 5 are views showing an image display device according to an embodiment of the present invention.
6 is a view showing a detailed configuration of the FRC processing circuit shown in FIG.
7 illustrates an example of an FRC compensation pattern preset in a memory.
8 shows the coefficient results in 2D mode and the compensation values of the FRC compensation pattern read accordingly.
9 shows the coefficient results in 3D mode and the compensation values of the FRC compensation pattern read accordingly.
10 shows extended compensation values of an FRC compensation pattern in 3D mode.
FIG. 11 illustrates an example in which extended compensation values of an FRC compensation pattern are applied to a left eye image and a right eye image in a 3D mode. FIG.
12 illustrates a method of driving an image display device according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 12.

3 and 4 show an image display apparatus of a polarizing glasses method according to an embodiment of the present invention.

3 and 4, the image display apparatus includes a display element 10, a patterned retarder 20, a control circuit 30, an FRC processing circuit 32, a memory 35, The panel driving circuit 40 and the polarizing glasses 50 are provided.

The display device 10 includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an inorganic electroluminescent device and an organic light emitting diode device. The display device may be implemented as a flat panel display device such as an electroluminescence device (EL) including an organic light emitting diode (OLED) and an electrophoresis display device (EPD). Hereinafter, the display element 10 will be described mainly with respect to the liquid crystal display element.

The display element 10 includes a display panel 11, an upper polarizer 11a, and a lower polarizer 11b.

The display panel 11 includes two glass substrates and a liquid crystal layer formed therebetween. A plurality of data lines DL and a plurality of gate lines GL intersecting the data lines DL are disposed on the lower glass substrate of the display panel 11. Due to the cross structure of the signal lines DL and GL, a pixel array including a plurality of pixels PIX is formed in the display panel 11. The black matrix, the color filter, and the common electrode are formed on the upper glass substrate of the display panel 11.

Upper and lower polarizing films 11a and 11b are attached to each of the upper and lower glass substrates of the display panel 11, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed. The common electrode supplied with the common voltage Vcom is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and is in the in plane switching (IPS) mode and the FFS (Fringe). It is formed on the lower glass substrate together with the pixel electrode in a horizontal electric field driving method such as a field switching mode. A column spacer for maintaining a cell gap of the liquid crystal cell may be formed between the glass substrates.

The display device 10 of the present invention may be implemented in any form such as a transmissive display device, a transflective display device, a reflective display device. In the transmissive display device and the transflective display device, the backlight unit 12 is required. The backlight unit 12 may be implemented as a direct type backlight unit or an edge type backlight unit.

The patterned retarder 20 is bonded to the upper polarizing film 11a of the display panel 11. The first retarder RT1 is formed in the odd lines of the patterned retarder 20, and the second retarder RT2 is formed in the even lines of the patterned retarder 20. The light absorption axis of the first retarder RT1 and the light absorption axis of the second retarder RT2 are different from each other. The first retarder RT1 of the patterned retarder 20 faces the odd-numbered pixel lines of the pixel array, and the second retarder RT2 faces the even-numbered pixel lines of the pixel array. The first retarder RT1 delays the phase of the linearly polarized light (2D image or 3D left eye image) incident through the upper polarizing film 11a by 1/4 wavelength and passes the first polarized light (eg, left circularly polarized light). The second retarder RT2 delays the phase of the linearly polarized light (2D image or 3D right eye image) incident through the upper polarizing film 11a by 1/4 wavelength to pass the second polarized light (eg, right circularly polarized light).

The control circuit 30 controls the operation of the panel driving circuit 40 in the 2D mode or the 3D mode according to the mode signal MODE. The control circuit 30 receives a mode signal MODE through a user interface such as a touch screen, an on screen display (OSD), a keyboard, a mouse, and a remote controller, and accordingly, the 2D mode operation and 3D mode operation can be switched. On the other hand, the control circuit 30 is a 2D / 3D identification code encoded in the data of the input image, for example, 2D / 3D identification that can be coded in the EPG (Electronic Program Guide) or ESG (Electronic Service Guide) of the digital broadcast standard Code can be detected to distinguish between 2D mode and 3D mode.

The control circuit 30 separates the 3D image data input from the video source under the 3D mode into input image data RGB of the left eye image and input image data RGB of the right eye image, and then stores the FRC previously stored in the memory 35. The input image data RGB of the left and right eye images is modulated with reference to the compensation pattern to generate the FRC compensation data RmGmBm of the left eye image and the FRC compensation data RmGmBm of the right eye image. The FRC compensation data RmGmBm of the left eye image and the FRC compensation data RmGmBm of the right eye image are alternately supplied to the panel driving circuit 40 by one horizontal line. The control circuit 30 modulates the input image data RGB of the 2D image input from the video source under the 2D mode into the FRC compensation data RmGmBm with reference to the FRC compensation pattern stored in the memory 35 in advance. The FRC compensation data RmGmBm of the image is supplied to the panel driving circuit 40.

The control circuit 30 includes an FRC processing circuit 32 for data modulation. The FRC processing circuit 32 adds the compensation values of the FRC compensation pattern to the input image data RGB of the 2D image, and expands and expands the compensation values of the FRC compensation pattern when the input image data RGB of the 3D image is input. The compensated compensation values are added to the input image data RGB of the 3D image. The FRC processing circuit 32 will be described later in detail with reference to FIGS. 6 to 11.

The control circuit 30 uses the timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal Data Enable, DE, and the dot clock DCLK to control the panel driving circuit 40. Generate control signals for controlling the operation timing.

The data control signal for controlling the operation timing of the data driver 40A includes a source start pulse (SSP) and a rising point indicating a start point of data in one horizontal period in which data for one horizontal line is displayed. Or a source sampling clock (SSC) for controlling the latch operation of data based on a falling edge, a source output enable signal (SOE) for controlling the output of the data driver 40A, and a display panel ( And a polarity control signal POL for controlling the polarity of the data voltage to be supplied to the liquid crystal cells of 11).

The gate control signal for controlling the operation timing of the gate driver 40B includes a gate start pulse (GSP) indicating a start horizontal line at which a scan starts in one vertical period in which one screen is displayed, and the gate driver 40B. Gate shift clock signal (GSC) for sequentially shifting the gate start pulse (GSP) and the gate output enable signal (Gate Output) for controlling the output of the gate driver 40B. Enable: GOE).

The control circuit 30 multiplies the timing signals Vsync, Hsync, DE, and DCLK in synchronization with the input frame frequency to obtain a frame frequency of N × f (N is a positive integer of 2 or more, f is an input frame frequency) Hz. The operation of the panel driving circuit 40 can be controlled. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) scheme and 50 Hz in the phase-alternating line (PAL) scheme.

The memory 35 includes a nonvolatile memory capable of updating and erasing data, for example, an electronically erasable programmable read only memory (EEPROM) and / or an extended display identification data ROM (EDID ROM) to configure an FRC compensation pattern. Store the values in the form of a lookup table. The compensation values constituting the FRC compensation pattern are for increasing the color depth of the input image data RGB, and may be determined as different values for each gray level and for each position. Since the FRC compensation patterns applied in the 2D mode and the 3D mode are the same, the increase in the capacity of the memory 35 is not accompanied. The memory 35 is electrically connected to the FRC processing circuit 32.

The panel driving circuit 40 may include a data driver 40A for driving the data lines DL of the display panel 11 and a gate driver 40B for driving the gate lines GL of the display panel 11. ).

The data driver 40A may include a plurality of source drive ICs. Each of the source drive ICs of the data driver 40A includes a shift register, a latch, a digital-to-analog converter (DAC), an output buffer, and the like. The data driver 40A latches the FRC compensation data RmGmBm of the 2D or 3D image according to the data control signals SSP, SSC, and SOE. The data driver 40A converts the FRC compensation data RmGmBm of the 2D or 3D image into the analog positive gamma compensation voltage and the negative gamma compensation voltage in response to the polarity control signal POL to invert the polarity of the data voltage. The data driver 40A outputs a data voltage to the data lines DL in synchronization with the scan pulse (or gate pulse) output from the gate driver 40B. The source drive ICs of the data driver 40A may be bonded to the lower glass substrate of the display panel 11 by a tape automated bonding (TAB) process.

The gate driver 40B generates a scan pulse swinging between the gate high voltage and the gate low voltage according to the gate control signals GSP, GSC, and GOE. The scan pulse is supplied to the gate lines GL in a line sequential manner according to the gate control signals GSP, GSC, and GOE. The gate driver 40B includes a gate shift register array. The gate shift register array of the gate driver 40B may be formed in a non-display area outside the display area in which the pixel array is formed in the display panel 11 by using a gate in panel (GIP) method. By the GIP method, gate shift registers can be formed together with the pixel array in the TFT process of the pixel array.

The polarizing glasses 50 include a left eye 50L having a left eye polarization filter and a right eye 50R having a right eye polarization filter. The left eye polarization filter has the same light absorption axis as the first retarder RT1 of the patterned retarder 20, and the right eye polarization filter has the same light absorption axis as the second retarder RT2 of the patterned retarder 20. Have For example, the left eye polarization filter of the polarizing glasses 50 may be selected as a left circular polarization filter, and the right eye polarization filter of the polarizing glasses 50 may be selected as a right circular polarization filter. The user may view 3D image data displayed on the display device 10 in a spatial division manner through the polarizing glasses 50.

6 to 11, the FRC processing circuit 32 will be described. FIG. 6 shows a detailed configuration of the FRC processing circuit shown in FIG. 5, and FIG. 7 shows an example of an FRC compensation pattern preset in a memory. FIG. 8 shows the coefficient result in 2D mode and the compensation values of the FRC compensation pattern read accordingly, and FIG. 9 shows the coefficient result in 3D mode and the compensation values of the FRC compensation pattern read accordingly. 10 shows extended compensation values of the FRC compensation pattern in 3D mode, and FIG. 11 shows an example in which extended compensation values of the FRC compensation pattern are applied to the left eye image and the right eye image in 3D mode.

Referring to FIG. 6, the FRC processing circuit 32 includes a data synchronizer 321, a first line counter 322, a second line counter 323, a counter selection controller 324, a multiplexer 325, and FRC compensation. A value modulator 326 and an FRC compensation value applier 327.

The data synchronizer 321 synchronizes the input image data RGB of the 2D image or the 3D image with the timing signals Vsync, Hsync, DE, and DCLK. The data synchronizer 321 adjusts the timing of the input image data RGB with reference to the timing signals Vsync, Hsync, DE, and DCLK, thereby causing a synchronization mismatch that may occur during the transmission of the input image data RGB. To prevent them.

The first line counter 322 refers to the vertical sync signal Vsync and the horizontal sync signal Hsync (or data enable signal DE) with reference to the FRC compensation pattern stored in the memory 35 in units of one line. Counting outputs the first count value CNT1. As shown in FIG. 7, when the FRC compensation pattern has a size of 4 (the number of pixels) x 4 (the number of pixels), the first count value CNT1 is '0', '1', and '2' as shown in FIG. 8. And '3'. The first count value CNT1 changes every one horizontal period.

The second line counter 323 refers to the vertical sync signal Vsync and the horizontal sync signal Hsync (or data enable signal DE) with reference to the FRC compensation pattern stored in the memory 35 in units of two lines. By counting, the second count value CNT2 is output. As shown in FIG. 7, when the FRC compensation pattern has a size of 4 (the number of pixels) x 4 (the number of pixels), the second count value CNT2 is '0', '1', and '2' as shown in FIG. 9. And '3'. The second count value CNT2 changes every two horizontal periods.

The counter selection controller 324 outputs a selection signal SEL having a different logic value in the 2D mode for the 2D image and the 3D mode for the 3D image according to the mode signal MODE. For example, the counter selection controller 324 may output the selection signal SEL in low logic in the 2D mode and in high logic in the 3D mode.

The multiplexer 325 receives the first count value CNT1 from the first line counter 322 and the first count value from the second line counter 323 in response to the selection signal SEL input from the counter selection controller 324. The two count value CNT2 is selectively output as the counting result CR.

The FRC compensation value modulator 326 receives the first count value CNT1 from the multiplexer 325 as the count result CR in the 2D mode, and receives the first count value CNT1 as a read address. The compensation values of the FRC compensation pattern are read from the memory 35 in units of lines. As shown in FIG. 8, the FRC compensation value modulator 326 compensates for each line of the FRC compensation pattern in one horizontal period according to the first count value CNT1 that increases or decreases from 0 to 3 in one horizontal period. Read P0 to P3 in order. The FRC compensation value modulator 326 receives the line compensation value of P0 in response to the counting result CR of '0', and the line compensation value of P1 in response to the counting result CR of '1'. In response to the counting result CR, the line compensation value of P2 is read, and the line compensation value of P3 is read in response to the counting result CR of '3'. The FRC compensation value modulator 326 outputs the compensation values of the read FRC compensation pattern to the FRC compensation value applying unit 327. The compensation values of the FRC compensation pattern output from the FRC compensation value modulator 326 in the 2D mode are the same as those stored in the memory 35 (shown in FIG. 7).

The FRC compensation value modulator 326 receives the second count value CNT2 from the multiplexer 325 as the count result CR in the 3D mode, and receives the second count value CNT2 as a read address. As a result, the compensation values of the FRC compensation pattern are read from the memory 35 in units of lines, thereby extending the compensation values of the FRC compensation pattern. In order to expand the compensation values of the FRC compensation pattern, the FRC compensation value modulator 326 may have two horizontal directions according to the second count value CNT2 that increases or decreases between '0 to 3' in two horizontal periods as shown in FIG. 9. The period-based compensation values P0 to P3 of the FRC compensation pattern are repeatedly read in sequence. Since the second count value CNT2 changes every two horizontal periods, the FRC compensation value modulator 326 reads out the same compensation value repeatedly for two horizontal periods in which the second count value CNT2 remains the same. The FRC compensation value modulator 326 repeatedly reads the line compensation value of P0 when the counting result CR is '0' for two horizontal periods, and when the counting result CR is '1' for two horizontal periods. The line compensation value of P1 is repeatedly read out, and if the counting result CR is '2' for two horizontal periods, the line compensation value of P3 is repeatedly read out, and the counting result CR is '3' for two horizontal periods. In the case of, the line compensation value of P3 is repeatedly read.

In the 3D mode, the vertical size of the FRC compensation pattern read by the FRC compensation value modulator 326 is twice as large as that stored in the memory 35 as shown in FIG. 10 (as shown in FIG. 7). The extended FRC compensation pattern through repeated reading has a size of 4 (horizontal pixels) x 8 (vertical pixels). In the 3D mode, the FRC compensation value modulator 326 uses the FRC compensation value applying unit as the FRC compensation pattern of the left eye image, using the compensation values P0 to P3 of the odd lines of the extended FRC compensation pattern as shown in FIGS. 10 and 11. The compensation values P0 to P3 of the even lines of the extended FRC compensation pattern are output to the FRC compensation value applying unit 327 as the FRC compensation pattern of the right eye image. Since the FRC compensation pattern of the left eye image and the FRC compensation pattern of the right eye image have the same size of 4 (the number of pixels) x 4 (the number of pixels) as the one stored in the memory 35, it is possible to realize the image quality at the 2D driving level. Become.

The FRC compensation value applying unit 327 generates the FRC compensation data RmGmBm of the 2D image by adding the compensation values of the FRC compensation pattern to the input image data RGB of the 2D image in the 2D mode. The FRC compensation value applying unit 327 generates the FRC compensation data RmGmBm of the 3D image by adding the extended compensation values of the FRC compensation pattern to the input image data RGB of the 3D image in the 3D mode.

12 illustrates a method of driving an image display device according to an embodiment of the present invention.

Referring to FIG. 12, the driving method of the image display apparatus according to the present invention stores the FRC compensation pattern partially applied to the weight as shown in FIG. 7 (S10). This FRC compensation pattern is common to the 2D mode and the 3D mode. Is applied. There is no need for a separate FRC compensation pattern to prevent deterioration in 3D mode. Thus, the capacity of the memory is not increased.

Subsequently, the driving method of the image display apparatus determines whether the current driving mode is the 3D mode based on the mode signal (S20).

When it is determined in S20 that the device is driven in the 3D mode (Yes in S20), the driving method of the image display apparatus sequentially reads the compensation values for each line of the FRC compensation pattern sequentially, thereby extending the compensation values of the FRC compensation pattern. (S30)

Subsequently, the driving method of the image display apparatus increases the color depth of the input image data of the 3D image by adding the extended compensation values of the FRC compensation pattern to the input image data of the 3D image.

On the other hand, when it is driven in the 2D mode as a result of the determination in S20 (No in S20), the driving method of the video display device sequentially reads the compensation values for each line of the FRC compensation pattern in turn, and inputs the compensation values into the 2D video input image data. The color depth of the input image data of the 2D image is increased by adding to (S50).

As described above, the image display device and the driving method thereof according to the present invention store the FRC compensation pattern commonly applied to the 2D mode and the 3D mode in a memory, and then apply the FRC compensation pattern as it is in the 2D mode, In the mode, the FRC compensation pattern is extended twice in the vertical direction through repeated reading of the FRC compensation pattern.

Accordingly, the present invention can apply the FRC technology with the same level of image quality as 2D driving even in 3D driving without increasing the memory capacity.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10 display element 11 display panel
20: patterned retarder 30: control circuit
32: FRC processing circuit 35: memory
40 panel driving circuit 50 polarized glasses
321: data synchronization unit 322: first line counter
323: second line counter 324: counter selection control unit
325: multiplexer 326: FRC compensation value modulator
327: FRC compensation value application unit

Claims (5)

A display device configured to display 2D and 3D images;
A patterned retarder bonded to the display element to transmit a left eye image of the 3D image with first polarization and a right eye image of the 3D image with second polarization;
Polarizing glasses including a left eye filter transmitting the first polarization and a right eye filter transmitting the second polarization;
A memory for storing an FRC compensation pattern commonly applied to the input image data of the 2D image and the 3D image; And
The compensation values of the FRC compensation pattern are added to the input image data of the 2D image, and when the input image data of the 3D image is input, the compensation values of the FRC compensation pattern are expanded to input extended compensation values of the 3D image. And an FRC processing circuit added to the video data. The method of claim 1,
The FRC processing circuit,
A first line counter for counting the FRC compensation pattern in units of one line;
A second line counter for counting the FRC compensation pattern in units of two lines;
A counter selection controller for outputting a selection signal having a different logic value in a 2D mode for implementing the 2D image and a 3D mode for implementing the 3D image according to a mode signal;
A multiplexer which selects an output of the first line counter and an output of the second line counter in response to the selection signal and outputs the result of the counting result;
An FRC compensation value for adding compensation values of the FRC compensation pattern to the input image data of the 2D image in the 2D mode and adding extended compensation values of the FRC compensation pattern to the input image data of the 3D image in the 3D mode. Application part; And
In response to the coefficient result input from the multiplexer, compensation values of the FRC compensation pattern read from the memory in the 2D mode are supplied to the FRC compensation value applying unit, and the FRC compensation pattern read from the memory in the 3D mode is used. And an FRC compensation value modulator which extends the compensation values and supplies the compensation values to the FRC compensation value applying unit. The method of claim 2,
The FRC compensation value modulator in the 3D mode,
An image display device extending the compensation values of the FRC compensation pattern by repeatedly reading the compensation values of one line from the memory twice in the FRC compensation pattern and repeatedly supplying the same compensation values to the FRC compensation value applying unit; . A display device for displaying a 2D image and a 3D image, a patterned retarder bonded to the display device to transmit a left eye image of the 3D image with first polarization, and a right eye image of the 3D image with second polarization; A driving method of an image display apparatus comprising polarizing glasses including a left eye filter transmitting the first polarization and a right eye filter transmitting the second polarization,
(A) storing an FRC compensation pattern commonly applied to the input image data of the 2D image and the 3D image in a memory;
(B) adding compensation values of the FRC compensation pattern to the input image data of the 2D image; And
And (c) expanding the compensation values of the FRC compensation pattern when the input image data of the 3D image is input and adding the extended compensation values to the input image data of the 3D image. Driving method. The method of claim 4, wherein
Step (C) is
And extending the compensation values of the FRC compensation pattern by repeatedly reading the compensation values of one line from the memory twice in the FRC compensation pattern.

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