KR20120126031A - Semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device is provided to reduce power consumption by using relation between tradeoff of power and delay time of an IO signal or a control signal. CONSTITUTION: A plurality of memory arrays of a basic unit include a plurality of writable and readable memory cells. A first bus includes a first buffer circuit(13A) and transmits an address and control signal. A second bus(RWBS) includes a second buffer circuit and transmits write data and read data. A first control circuit(6) successively transmits the address and control signal from one terminal of the first bus from the basic unit of an original terminal to the basic unit of the proximal terminal. A second control circuit(7) successively transmits a data signal from one terminal of the second bus from the basic unit of the original terminal to the basic unit of the proximal terminal.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

TECHNICAL FIELD This invention relates to a semiconductor device. Specifically, It is related with the semiconductor device provided with the memory cell array.

In recent years, semiconductor memory, such as DRAM (Dynamic Random Access Memory), has advanced in performance, high speed, and large capacity, and the introduction of architectures such as DDR (Double Data Rate) / DDR2 / DDR3 also allows data bandwidth to be input and output in memory. Significantly improved.

To improve the data bandwidth of the memory I / O, improve the memory READ (read) and WRITE (write) cycles (tRC: ROW CYCLE TIME), or the number of concurrent operations (parallel number) in the memory. It is necessary to improve the amount of data that can be handled by multiplexing (increasing the number of parallelisms) of the (IO line) or multibanking of the memory array.

As is well known, the power consumption power P is approximated by equation (1).

In Equation 1, n is the number of elements, c is the capacitance (output load capacitance charged and discharged by the element), f is the operating frequency, V is the operating voltage. Here, briefly explaining the derivation of Equation 1, power P is an average of dynamic dissipation consumed when the device charges / discharges the output load capacity, and an operating frequency (actually, a toggle frequency) is defined as f, When the output load capacity is set to CL, the sum of the power when the output Vout of the device rises from Low (0V) to High (VDD) and the power when the output Vout falls from High (VDD) to Low (0V). It is supplied by and approximated as follows (however, tp = 1 / f).

For n elements (n outputs), Equation 2 is obtained by multiplying Equation 2 and setting the capacitance load CL of each output to a common value c.

For example, when the data band width (transmission efficiency) is doubled by improving the operating frequency f, the power is also increased. In addition to the improvement of the data amount in memory cell arrays, there is a demand for lower power consumption.

In addition, Patent Document 1 discloses a memory system that supports multiple memory access latency times. The structure of the system disclosed by patent document 1 is shown in FIG. 1 (cited from FIG. 2A of patent document 1). This is to control access to the memory device in the memory system. The memory controller 202 is divided into a group (latency time group 1) and a distant group (latency time group 2) of the memory device close to each other. The overall access latency is shortened by classifying frequently accessed data and notly data into group 1 and group 2, respectively.

FIG. 2 is a diagram showing a general memory configuration in the case where the configuration of FIG. 1 is replaced with a general DRAM (this is a diagram created by the inventors of the present application).

As shown in Fig. 2, this memory (DRAM core) has a memory cell array 1 (multiple bank configuration) having a plurality of memory cells in an array shape, and decodes a row address to activate a selected word line. A row decoder (X DEC) 2, a column decoder Y DEC 3 that decodes the column address and turns on the Y switch of the selected column (bit line), and a sense amplifier that amplifies the potential of the bit line. / Y switch (4) and the read data amplified by the sense amplifier of the selected column is amplified and output to RWBS (Lead Write Bus) to drive the write data from RWBS (Lead Write Bus). A data amplifier / write amplifier 5 to be performed, an address command timing controller 6 for controlling address, command, and timing, and an internal data bus that is an input to the DRAM core ( Data terminal (not shown) connected to Internal Data Bus (9) Between the RWBS (lead write bus) and the RWBS (lead write bus), the data to perform the write mask control to the memory cell by the data input / output function of the data from the memory cell and the data mask signal from the data mask terminal (not shown). A control circuit (Data I / O, Data Mask) 7, an input (clock, address, command) 8 to the DRAM core, and an internal data bus (I / O) for inputting and outputting data to the DRAM core ( 9) is provided.

FIG. 3 is a diagram for explaining FIG. 2, and FIG. 3 is a diagram illustrating an example of the layout (layout) of FIG. 2 (this is a diagram created by the inventors of the present application). In FIG. 3, the region 10 in the memory cell array 1 represents an active area including memory cells to be accessed. Reference numeral 11 denotes a memory array or a memory macro (circuit block used for a system LSI or the like) constituting a basic unit. The control circuit (address command timing controller) 6 is controlled by an address / command bus (ADDRESS / CMD BUS) connected in common to the basic units 11 of the two memory arrays to access the active area ( 10). The selection of the active region 10 decodes the X address (row address) of the address signal, decodes the column address, and the X decoder (XDEC) 2 for activating the selected word line, and turns on the Y switch of the selection column. A column decoder (YDEC) 3 is used. The data (WRITE data / READ data) is inputted and outputted from the data control circuit 7 and transmitted by the read write bus RWBS commonly connected to the plurality of memory array basic units 11. Although not particularly limited, in FIG. 3, there are 36 data terminals (DQ terminals) connected to an internal data bus 9 for inputting data from the DRAM core, and a plurality of bits of each data terminal DQ are provided. Data (e.g., a plurality of bits serially input corresponding to the burst length (the number of data that can be continuously input and output)) is, for example, parallel data by the data control circuit (Data I / O) 7. The data is converted and parallelly transferred to the read write bus RWBS. The read write bus RWBS extends over the plurality of memory array basic units 11 and is connected in common to the data amplifiers / write amplifiers of each memory array basic unit 11. to be. When the burst length is 4, the RWBS per data terminal has four data lines (IO lines), and 36 x 4 = 144 data lines (IO lines) are provided for the 36 data terminals.

The IO configuration in the memory array may be a hierarchical (local IO line / main IO line) configuration or a non-hierarchical configuration. In the case of a tiered configuration, the main IO line connected to the data amplifier / write amplifier WRITE is connected to a plurality of local IO lines through a switch circuit not shown, and each local IO line is a column decoder. It is selected by (Y DEC) 3 and connected to the bit line of the selected column via the Y switch 4 which is turned on.

During READ, the data read from the memory cell connected to the word line (set to High potential) selected by the X decoder 2 is amplified by the sense amplifier 4 and Y set to the ON state of the selection column. It is transmitted to the local IO line through the switch 4, and also to the data amplifier 5 via the main IO line, and output to the read write bus RWBS. The data control circuit 7 converts the parallel bit data (the number of bits corresponding to the burst length) into serial and outputs serially from the data terminal to the internal data bus 9 in synchronization with the clock. (DDR is transmitted in synchronization with the rising and falling edges of the clock signal).

In WRITE, the bit data input serially from the data terminal connected to the internal data bus 9 is parallelized by the data control circuit 7 to transmit the RWBS, and the write amplifier WRITE AMP. Amplified by (5), it is transmitted to the bit line of the selection column in which the Y switch 4 is turned on through the Main IO line and the selected Local IO line.

Data is controlled by the address command timing controller 6 and read / write (WRITE) in the active region 10 in the selected memory cell array 1.

FIG. 4 shows the case 1 (active region 10-1) selected from the address command timing controller 6 and the data IO 7 side as the active region 10 in FIG. Is a diagram showing the case 2 (active region 10-2) in which the near side is selected.

FIG. 5 is a timing chart showing access operations in cases 1 and 2 of FIG. 4 (FIG. 5 shows control delays (10-1 control delays) corresponding to the active areas 10-1 and 10-2 from command inputs in the command CMD, the clock (memory CLK), the case 1 and the case 2; 10-2 control delay), corresponding to the selection time (10-1 selection time, 10-2 selection time) of the active regions 10-1 and 10-2, and the active regions 10-1 and 10-2. The relationship between the output delay (10-1 output delay, 10-2 output delay) and α, θ, and β is schematically illustrated.

α is tRC (Row Cycle Time),

β is tRRD (Row to Row Delay),

γ is the control delay, data delay (output delay),

θ is READ Latency

to be.

? is an address / command / timing control circuit (address command / timing controller) 6 and a data control circuit 7 for setting addresses / commands and data for controlling the active region 10 of the memory cell array. Time and a delay time for transferring the data signal to the memory array basic unit via the read write bus RWBS. The output delay also corresponds to the time when the data read out from the active area 10 is transferred to the data control circuit 7 via the RWBS.

α is a cycle related to the memory cell array operation of the active region 10.

β is the time at which the next command CMD can be input from one command CMD input.

θ represents the number of clock cycles (latency) from inputting the READ command to outputting data to the data terminal DQ.

For the example of FIG. 5,

10-1 control delay> 10-2 control delay,

10-1 output delay> 10-2 output delay

to be. The control delay and the output delay γ of the active regions 10-1 and 10-2 are at most one clock cycle, and tRC (α) is six cycles, and α >> γ, that is, α is significantly longer than γ. Also, α? Θ, that is, α is a time almost equal to the latency.

Incidentally, increasing the bandwidth of the data and improving the cycle of the memory are synonymous with the improvement of the latency θ.

In the example shown in FIG. 5, the ratio (time ratio: γ / α) of γ to α is small. Therefore, the delay of γ (control delay, output delay) and the power consumed at γ (control delay, output delay) are also smaller than the delay and power at α.

However, when the parallel number of IOs in the memory cell array (for example, the number of data lines to be transmitted in parallel in the read / write bus) increases, for example, to increase the time such as parallel conversion of the bit data serially input from the data terminal. As a result, the ratio of gamma to alpha increases, and the power consumed by gamma increases.

Until now, the development of the architecture has been focused on reducing tRC (α) and β. α = tRC (ROW CYCLE TIME) is an index indicating the cycle in which the memory array is actually operating to access the memory cell. In one tRC, the operating frequency f of the memory input / output is determined by the number of data read / write in parallel (the number of memory cells to be accessed).

Fig. 6 is a view for explaining the related art (a drawing made by the inventor of the present application to explain the problem). In Fig. 6, the number of terminals of the data terminals (data terminals connected to the internal data bus 9) is 36. The burst length BL is four. In response to BL = 4, the read write bus RWBS is 4 bits, and has 36x4 = 144 parallel data lines (IO lines) corresponding to 36 data terminals, and 144 data are written in the active area in the WRITE / READ. YDEC is a column decoder that decodes the column address of the address signal. In Fig. 6, the same reference numerals are attached to the same or equivalent elements as in Figs. It goes without saying that the YDEC may be provided in the memory array basic unit as shown in Figs. 3 and 4.

[Patent Document 1] Japanese Patent Application Publication No. 2008-500668

An analysis of the related art is provided below.

As a specification required for memory, latency θ is also important, but recently, tRC is improved, and power is reduced while improving the number of data accesses (efficiencies) to be read and written to the memory cell, that is, tRC (α) is reduced. In order to increase the number of data accesses, low power is required.

7A and 7B are diagrams schematically showing the WRITE operation and the READ operation in the semiconductor memory shown in FIG. 6. 7 is a figure which the inventor of this application produced in order to demonstrate the problem of the related art. In FIG. 7, burst length = 4, and BL0-BL3 corresponds to burst length = 4, and read / writes four columns (bit lines) BL0, BL1, BL2, BL3 consecutively in one access command. The 4-bit data written to WRITE is shown.

In addition, in FIG.7 (A) and FIG.7 (B), CMD is a WRITE command and a READ command, respectively. In FIGS. 7A and 7B, for the sake of simplicity, the bank active command ACT, the precharge command PRE, and the like are omitted. The CMD is designated by a combination of control signals (chip select, write enable, column address strobe, row address strobe) and the like, and these control signals are input to a command decoder (not shown) and decoded. By inputting the WRITE command or the READ command, the BL0-3 data is written or read for four columns starting from the designated column address with respect to the designated row address.

In Fig. 7A, write data BL0, BL1, BL2, and BL3 of a 4-bit serial are transmitted from one data terminal to a double data rate (two bits in one clock cycle in synchronization with the rising edge and falling edge of the memory CLK). Data) is input. The 4-bit data BL0, BL1, BL2, and BL3 corresponding to the four input columns are serial-parallel converted to 4-bit parallel data, and are transferred in parallel to the four data lines of the read / write bus RWBS. Control delay). Data arriving from the read write bus RWBS to the basic unit 11 of the memory array (bit data without a data mask) is amplified by a write amplifier (not shown) (WRITE AMP 5 in FIG. 2). The bit line (BLT /) of the selected column (four columns) in which the Y switch (Y Switch 4 in FIG. 2) is turned on through the main IO line (MIOT / B) and the local IO line (LIOT / B). It is transferred to the sense amplifier (Sense Amlifier in Fig. 2) of B), and writing to the selected cell (cell connected to the word line set to the high level) in the active area is performed (selection time alpha).

As shown in Case 1 and Case 2 in FIG. 7A, the active region 10-1 (FIG. 6) of the memory array basic unit 11 of the far end is shown from the data control circuit 7 side. The control delay (10-1 control delay) is the control delay 10 of the active region 10-2 (Fig. 6) of the memory array basic unit 11 of the near-end from the data control circuit 7 side. -2 control delay). In Fig. 7A, BL0-BL3, which is placed under the control delays of 10-1 and 10-2, is parallel 4-bit data obtained by serial-parallel conversion of 4-bit data serially input from the data terminal. The BL0-BL3 placed under 1, 10-2 selection time is parallel 4-bit data (write data to four selection columns BL0-BL3 of the memory cell array) transferred to the selection column in the memory array basic unit 11. ]to be.

FIG. 7B is a timing chart illustrating an operation when reading data from a memory cell at burst length 4. As shown in FIG. As shown in Case 1 and Case 2 in Fig. 7B, the control delay (10-1 control delay) and the output delay (10-) from the data control circuit 7 side to the active area 10-1 of the far end. 1 output delay) is longer than the control delay (10-2 control delay) and the output delay (10-2 output delay) for the near-end active region 10-2 from the data control circuit 7 side, respectively. It costs. The data BL0-BL3 read out from the memory cell at the selection time (selection time of the active region 10-1 or 10-2) in Fig. 7B is Y switch (Y Switch 4 in Fig. 2). Is transmitted from the local IO line and the main IO line (not shown) to the read write bus RWBS, thereby requiring an output delay (10-1 output delay, or 10-2 output delay) to the data control circuit 7. Upon arrival, four bits of data BL0-BL3 are output in serial and two cycles at a double data rate. In this example, the cycle from the input of CMD (READ) to the output of the first bit data BL2 is 4 (latency?).

In the WRITE and READ operations in FIGS. 7A and 7B, the characteristics are determined by selecting the far-end memory cell (the memory cell in the active area) from the data control circuit 7 side, and the command ( The period (CMD to CMD period) β between the CMD and the next command CMD is three cycles. In addition, the selection time? Of the active region of the memory cell array is three cycles.

In the example shown in FIG. 5, it was α >> γ, but as shown in FIG. 7, in the high-speed memory, the ratio of gamma to α and θ is large.

That is, the ratio of the delay (data bus line RWBS or the delay of the control signal line) of data transfer in the memory cell array is increased.

In particular, in a high-speed memory that focuses on the cycle? (= TRC) for accessing the memory, the delay? Is relative to the delay? Of the memory operation itself, such as the selection of a word, a bit line, or a memory cell in the memory cell. This will look great.

Therefore, it is necessary to transfer data input from the data terminal to the read write bus RWBS efficiently, to perform WRITE / READ access to the memory cell, and to achieve both low power consumption.

Fig. 8 is a view for explaining the related art (the drawing made by the inventor of the present application to explain the problems of the related art). In Fig. 8, four basic units 11 are provided as memory arrays, and the number of data terminals (IO terminals connected to the internal data bus 9) is 36, and the burst length BL = 8. The read write bus RWBS corresponding to one data terminal is an 8-bit data line (IO line) and includes 8 x 36 = 288 (288-bit parallel) data lines as a whole.

Reference numerals 10-1 and 10-2 denote active regions in the memory array basic unit 11, respectively. In addition, YDEC is a column decoder which decodes a column address. In Fig. 8, the same reference numerals are attached to the same or equivalent elements as in Fig. 6 and the like. It goes without saying that YDEC may be provided in the memory array basic unit 11 as shown in FIGS. 3 and 4. The active region 10-1 is farther from the control circuit (address command timing controller) 6 and the data control circuit (data I / O, data mask) 7 side than the active region 10-1. 2) is a close side.

9 and 10 are timing charts for describing the WRITE operation and the READ operation in the configuration of FIG. 8, respectively. As shown in Fig. 9, in the continuous WRITE in which the WRITE command is input continuously without time, in response to the rising edge and the falling edge of two clock cycles from the first WRITE command CMD, corresponding to eight columns. 8-bit data BL0-BL7 is serially input to the data terminal, and at a control delay of?, 8-bit data BL0-BL7 is parallel data, which is written to the memory array basic unit 11 through the read write bus RWBS. The amplifier is supplied to the WRITE AMP of FIG. 2. At the selection time following the control delay, 8-bit data of BL0-BL7 is written into the memory cell connected to the selected word line and connected to the bit line of the selected eight columns.

In the example of FIG. 9, the selection time α is three clock cycles. Subsequent to 8-bit data serially input corresponding to the previous WRITE command CMD, 8-bit data corresponding to the next WRITE command CMD is input serially from the data terminal. The control delay of the far-end access area 10-1 is longer than the control delay of the near-end access area 10-2. In addition, pipeline 1 on the left side of FIG. 9 indicates that the processing of the control delay and subsequent selection time is performed by the pipeline of one stage.

As shown in Fig. 10, during continuous READ in which the READ command is input continuously without time, 8-bit data from the data terminal after the latency θ from the READ command (CMD) input, the rising edge and the falling edge of the clock. It is output in synchronization with.

Pipeline 1 on the left side of FIG. 10 shows the control delay and the selection time, and pipeline 2 indicates the output delay and the output of the serial bit data. As shown by Case1, the control delay and output delay of the far-end access area 10-1 are all longer than the control delay and output delay of the near-end access area 10-2 shown as Case2.

As described above, in Patent Document 1, the average latency is shortened by paying attention to the delay time of the latency path in order to efficiently read data and write data.

However, just shortening the average latency does not shorten the cycle of memory access itself. In addition, it is insufficient to reduce power.

It is therefore an object of the present invention to provide a semiconductor device having a memory array that enables power reduction and memory access shortening.

In order to solve at least one of the said subjects, this invention has the structure of the following roughly (but is not limited to these).

According to the present invention, a memory array including a plurality of writeable and readable memory cells is formed of a plurality of basic units,

A first bus which is provided to a plurality of said basic units in common, and to which an address signal / control signal is transmitted;

A second bus which is provided in common to a plurality of said basic units and which transfers write data and read data,

The first bus includes at least one first buffer circuit that functions as a pipeline register,

The second bus includes at least one second buffer circuit that functions as a pipeline register,

A first control circuit which sequentially transmits an address / control signal from the one end of the first bus, in the order from the base unit on the far-end side with respect to the one end, and the basic unit on the near-end side with respect to the one end;

A second control circuit which sequentially transmits data signals from one end on the second bus in order from the far end side basic unit to the one end to the near end side basic unit at the time of writing; And

Write data transmitted from the second bus to each of the plurality of basic units is written to each of the plurality of the basic units,

Upon reading, read data from each of the plurality of basic units arrives in the second control circuit in the order of the basic unit on the far-end side from the basic unit on the near-end side via the second bus. In the second control circuit, a semiconductor device for outputting the arrived read data is provided.

According to the present invention, a semiconductor device having a memory array capable of maintaining data efficiency and reducing power consumption can be realized.

1 is a diagram illustrating a configuration of Patent Document 1. FIG.
2 is a diagram showing a configuration of a general memory.
3 illustrates a related art.
4 illustrates a related art.
5 is a timing chart of the related art of FIG.
6 is a view for explaining a structural example 1 of the related art.
7A and 7B are timing charts illustrating the WRITE and READ operations in FIG. 6.
8 is a view for explaining a structural example 2 of the related art.
FIG. 9 is a timing chart illustrating the WRITE operation of the related art of FIG. 8. FIG.
10 is a timing chart for explaining a READ operation of the related art in FIG. 8;
Fig. 11 is a diagram explaining Embodiment 1 of the present invention.
12 is a timing chart for explaining the WRITE operation of the first embodiment of the present invention;
Fig. 13 is a timing chart for explaining a READ operation according to the first embodiment of the present invention.
14 is a timing chart for explaining a pipeline of the WRITE operation according to the first embodiment of the present invention.
Fig. 15 is a timing chart for explaining the pipeline of the READ operation according to the first embodiment of the present invention.
16 is a diagram describing Embodiment 2 of the present invention;
Fig. 17 is a timing chart illustrating the WRITE operation of the second embodiment of the present invention.
Fig. 18 is a timing chart for explaining a READ operation according to the second embodiment of the present invention.
Fig. 19 is a timing chart for explaining the pipeline of the WRITE operation according to the second embodiment of the present invention.
20 is a timing chart illustrating a pipeline of continuous WRITE operations according to the second embodiment of the present invention.
Fig. 21 is a timing chart for explaining the pipeline of the READ operation according to the second embodiment of the present invention.
Fig. 22 is a timing chart for explaining the pipeline of the WRITE to READ operation according to the second embodiment of the present invention.
Fig. 23 is a timing chart for explaining the pipeline of the READ to WRITE operation according to the second embodiment of the present invention.
24 is a diagram describing Embodiment 3 of the present invention;
Fig. 25 is a diagram explaining burst switching in Embodiment 3 of the present invention.
Fig. 26 is a diagram explaining Embodiment 4 of the present invention;
Fig. 27 is a diagram for explaining the burst switching prohibition rule in the fourth embodiment of the present invention.
Fig. 28 is a diagram explaining specifications of CMD to CMD period β in the common IO line (CIO) configuration according to the fourth embodiment of the present invention.
Fig. 29 is a diagram explaining Embodiment 5 of the present invention;
Fig. 30 is a diagram explaining specifications of the CMD to CMD period β in the fifth embodiment of the present invention.
31A and 31B are diagrams showing an example of the configuration of a buffer.
32 is a view for explaining an example of address assignment in Embodiment 6 of the present invention.
FIG. 33 is a view for explaining a first example of address assignment switching in Embodiment 6 of the present invention. FIG.
Fig. 34 is a view for explaining a second example of address assignment switching in Embodiment 6 of the present invention.
35 is a diagram showing a configuration example of a basic unit of a buffer and a memory array in each embodiment;

EMBODIMENT OF THE INVENTION Hereinafter, the preferable form for implementing this invention is demonstrated.

The main features of the present invention have the following constitution (but not limited to the following).

(1) A pipeline register is inserted into an address, an address command bus from a command control circuit, an IO line (lead write bus), etc. from a data control circuit, and the memory cell array is divided.

(2) The validity and the invalidity of the pipeline register are switched in accordance with the operation specification of the memory, so that the basic unit of the memory cell array can be changed.

(3) The interval β (tRRD) between the access latency and the command input is made variable for each basic unit of the divided memory cell array.

(4) A parallel memory cell array is selected for the IO line and the control line so that data input and output can be performed.

(5) The number of selections when selecting a memory cell array in parallel with respect to an IO line and a control line is made variable according to an operation specification. In addition, address assignment is made variable.

According to some preferred embodiments, a memory array including a plurality of write and read memory cells is composed of a plurality of basic units 11, is provided in common for a plurality of the basic units, and includes an address signal / control signal. A first bus (address command bus) to which transfer is performed and a plurality of basic units 11 are provided in common, and a second bus (RWBS) to which write data and read data are transferred. . The first bus includes at least one first buffer circuit 13A that functions as a pipeline register. The second bus includes at least one second buffer circuit 13B that functions as a pipeline register. Further, a first control circuit that sequentially transmits address / control signals from one end of the first bus to a base unit on the far end side with respect to the one end, and then to a base unit on the near end side with respect to the one end. (6) and the data signal from the one end on the second bus RWBS at the time of data writing, in the order from the basic unit on the far-end side with respect to the one end, and the basic unit on the near-end side with respect to the one end. In addition, the second control circuit 7 for sending is provided. The write data transmitted from the second bus RWBS to each of the plurality of basic units is written to each of the plurality of the basic units. Further, when reading data, read data from each of the plurality of basic units arrives in the second control circuit in the order of the basic unit on the far-end side from the basic unit on the near-end side via the second bus. The second control circuit 7 outputs the arrived read data. According to some preferable aspects, at least 1 in the said 1st bus (address command bus) between the said basic unit located in the far-end side and the said basic unit located in the near-end side from the 1st control circuit 6 Two first buffer circuits (13A), on the second bus (RWBS), between the basic unit located on the far-end side and the basic unit located on the near-end side from the second control circuit (7), It is good also as a structure provided with the at least 1 2nd buffer circuit 13B. Alternatively, in the first bus (address command bus), a first buffer circuit 13A is provided between adjacent basic units, and in the second bus RWBS, a second between adjacent basic units is provided. It is good also as a structure provided with the buffer circuit 13B.

According to some preferred embodiments, the memory array comprises first to Nth basic units 11 (where N is a positive integer of 2 or more), and the first bus (address command bus) is ( N-1) pairs of (N-1) first buffer circuits 13A are provided between adjacent basic units, and the second bus RWBS has a burst length M × N (where M is Per data terminal for serially inputting and outputting MxN bit data corresponding to one or more predetermined positive integers), and having parallel M data lines, between (N-1) pairs of adjacent basic units (N-1) second buffer circuits 13B are provided. The first control circuit 6 sequentially stores the address / control signals in the most basic unit among the first to Nth basic units in the order of the address / control signals in the most basic unit. The first bus is sent out every cycle. When writing data, the second control circuit 7 stores M × N bit data serially input from the one data terminal from the data in the most basic unit among the first to Nth basic units. To M data lines of the second bus RWBS sequentially and in parallel, in order of the data in the last basic unit, M by bit (corresponding to the burst length M × N). The M × N bit data is sequentially transmitted and stored in M different N basic units for each M bit, and the number of data lines of the second bus RWBS is M). M-bit data transmitted from the second bus RWBS to each of the first to Nth basic units 11 is written in each of M columns of the first to Nth basic units. In addition, when reading data, M-bit data read from each of the M columns of the first to Nth basic units is transferred to the second bus RWBS in parallel, so that the M bits of the most basic unit are the M bits. From the data, the second control circuit 7 sequentially arrives at the second control circuit in the order of the M bit data of the basic unit of the farthest end, and the second control circuit 7 receives M × N bit data from the data terminal. Output in serial.

According to some preferable aspects, it is good also as a structure which can thin the pipeline register and can optimize to several different burst length. The first bus includes a first buffer circuit 13A between each pair of plural pairs of adjacent basic units, and the second bus includes each pair of plural pairs of adjacent basic units. A second buffer circuit 13B is provided between the first buffer circuit and the second buffer circuit in at least one pair of the plurality of first buffer circuits and the plurality of second buffer circuits. It functions as a function, invalidates the pipeline and register functions of the remaining first buffer circuit and the second buffer circuit, thereby making it possible to cope with a plurality of different burst lengths.

According to one of the preferred forms, in more detail, for example, the memory array consists of first to Nth basic units (where N = 2 ^ K, K is a predetermined positive integer of 2 or more), The first bus includes (N-1) first buffer circuits 13A between adjacent (N-1) pairs of the basic units, and the second bus RWBS has a burst length. Per data terminal for serially inputting and outputting the number K of bit data corresponding to each other, and having parallel M data lines (wherein M is a predetermined positive integer of 2 or more), and adjacent (N-1) pairs (N-1) second buffer circuits 13B are provided between the basic units, and when the burst length is M × N, the (N-1) first and second buffer circuits are pipelined. When the burst length is M × (N / (2 ^ L)) (where L is a predetermined integer of 1 or more and K or less, ^ is a squared operator), adjacent 2 ^ (K-1) ) Basic stages May be integrated into one set, and the first and second buffer circuits between adjacent sets may function as pipeline registers, and the remaining first and second buffer circuits may be invalidated in the pipeline and register functions. .

According to some preferred embodiments, a plurality of third buffer circuits are provided corresponding to each of the plurality of basic units 11 and receive address / control signals transmitted to the first bus and supply the plurality of third buffer circuits to the basic units. 13C is provided.

According to some preferred aspects, a control delay γ consisting of a transfer cycle of address / command to the first bus and a write cycle of write data to the second bus in write access for write and read access. In a first period corresponding to the second period corresponding to the selection time α at which data is written to, or read from, the selected memory cell in the basic unit of the memory cell array. In this regard, the first period is made up of a plurality of cycles corresponding to pipeline control, and has a length equal to or greater than the second period.

According to some preferred forms, in the read access, following the selection time, the output delay γ until the data read from each basic unit is transmitted to the second bus and arrives at the second control circuit. The corresponding third period consists of a plurality of cycles corresponding to the pipeline control and has a length equal to or greater than the second period corresponding to the selection time α.

According to some preferred forms, both the first period and the third period have the same length as the second period.

According to some preferable aspects, the said 1st time period and the 2nd time period corresponding to the some command input continuously, or the said 1st thru | or 3rd time period become a unit of pipeline control between commands.

According to one of several preferred forms, the said basic unit is made into a subbank, the bank 15 containing a plurality of subbanks is provided, and a plurality of accesses are performed to the plurality of subbanks.

According to one of several preferred forms, the second bus includes a write-only bus (WBS) 16 for transferring write data from the second control circuit to the plurality of basic units, and from the plurality of basic units. A read-only bus (RBS) 17 for transferring the read data to the second control circuit 7. The write only bus WBS 16 includes at least one second buffer circuit 13B, and the read only bus RBS 17 includes at least one second buffer circuit 13B.

First, one of the basic principles of the preferred form will be described. In addition, in the following, in order to facilitate the explanation of the basic principle of the present invention, a description will be made in contrast with the above-described related technology, Patent Document 1 and the like.

The number of memory cell arrays that are controlled by control circuits (addresses, commands, timing controllers) or data control circuits (data I / O, data masks) is increased by dividing the memory array into basic units and increasing the capacity of the memory. Moreover, the wiring length of a control signal and the wiring of the read / write bus RWBS for data transfer are also long. For this reason, although the shortening with respect to the period of the selection time tRC ((alpha)) advances, the shortening does not progress with respect to the period of control delay and output delay (gamma), and while shortening period of (alpha) in high performance and large capacity, (gamma) The proportion occupied by the period is growing.

That is, the ratio of the transmission time of the data signal and the control signal in the memory cell array (period γ of delay of the read write bus or the control signal line) becomes large.

In particular, in a high speed memory that emphasizes the speedup (shortening) of the ROW cycle time tRC (α) for accessing the memory, the delay α of the memory operation itself, such as the selection of a word, a bit line, or a memory cell in a memory cell, As to the dominant term, the above-described control delay / output delay γ becomes large.

Therefore, data input from the outside is efficiently transferred by the read write bus RWBS to write to the memory cell, and read data from the memory cell is transferred to the read write bus RWBS for efficient reading. In order to perform the above, both high speed signal transmission and low power consumption are required.

According to a preferred embodiment, attention is paid to the power delay product (= P Td). As mentioned above, the power P,

(Where n is the number of elements, c is the capacitance, f is the operating frequency, and V is the operating power supply voltage), but the delay γ (= delay 1) such as the control delay and output delay (= delay 1) and the selection time (α) When divided into the corresponding delays (= delay 2) and the like, the power delay product P · Td is expressed by the following expression (3).

In equation (3), subscript 1 represents the number of elements n of delay 1 (γ of control delay and output delay), capacitance c, operating frequency f, and operating power supply voltage V, and subscript 2 represents elements of delay 2 (selection time α). A number n, a capacity c, an operating frequency f, and an operating power supply voltage V are shown.

Considering the items that can be traded off for power reduction, the number of data output from the memory and the number of data input to the memory cannot be reduced in view of the data efficiency seen from the system.

In the READ operation, the control delay / output delay γ is an address from the CMD (READ command) input to the memory array basic unit 11, a delay until a command is supplied (control delay), or the memory array basic unit 11. Is a delay (output delay) from the data control circuit which received the parallel data transferred to the read write bus RWBS from the serial data to output from the data terminal. The number of bit data read out from the semiconductor memory does not change because it corresponds to the burst length.

When the output of data is started from the semiconductor memory, and the data bus (for example, the bus 9 of FIG. 9) outside the semiconductor memory is filled with data (i.e., each clock cycle consecutive on the data bus is filled with data, and the data When no clock cycle exists, the data efficiency such as an external data rate (data transfer rate) is determined by the cycle α.

In order to reduce power, the trade-off can be ignored by allowing the system side which accesses the semiconductor memory (for example, READ access) to ignore the period of the control delay and output delay γ which affects the read latency seen in the first access. The relationship becomes available.

That is, the data efficiency is not only focused on the data rate of the number of data with respect to the operating frequency, but also attention is paid to the items of power consumption and attention to the power delay product P · Td. In order to reduce power consumption without compromising data efficiency, the trade-off relationship can be used in the component of the delay time Td due to the control delay / output delay γ and the delay 1 which is an item of the power consumption. With respect to ₁ , the power can be reduced by reducing f ₁ and V ₁ in the power term of n ₁ × c ₁ × f ₁ × V ₁ ² .

Power P and delay time Td are also betrayed items. For this reason, when the power P is halved, it is necessary to devise such that the delay time Td is not more than doubled.

On the other hand, the delay 2 (selection time α) for determining the number of input / output data of the memory cell requires a constant or small configuration of the memory cell array.

6 and 7 show, for example, the configuration of 36 data terminals DQ, burst length BL = 4 (data player = 144), and an example of the timing operation among the above-described related technologies. . 8, 9, and 10, the configuration of the data terminal DQ number 36, the burst length BL = 8 (data player = 288), and the timing operation are shown.

In the example shown in Fig. 9, the delay time? For one cycle for the transmission of the control signal and the data signal / mask signal at the time of WRITE, and the active area 10-1 (CASE1) or 10-2 (CASE2). ], A delay time of two cycles is consumed at the selection time of data writing. By the control circuits 6 and 7 of FIG. 8, 3 cycles are allocated to (alpha). On the other hand, since the burst length is 8 and four cycles are required for data input, β becomes four cycles.

In the example shown in FIG. 10, one cycle is allocated to the control delay γ during READ, and one cycle is also assigned to the output delay γ for reading the read data. In this case, α, β, and θ are all four cycles.

Patent Document 1 (Japanese Patent Application Laid-Open No. 2008-500668), which is the above-described related art, refers to a means for shortening the average latency by paying attention to the delay time of the latency pass in order to efficiently read data and write data. Providing. However, only by means of shortening the average latency, the cycle of the memory itself is not shortened. Further, only means for shortening the average latency is insufficient to reduce the power.

In the related art, when the active area of the far end of the memory array is accessed and when the near end active area is accessed, the difference in current consumption due to the charge / discharge current of the read / write bus RWBS, which is an IO line of data transfer, is different. none.

If the ROW cycle time tRC (selection time α) of the memory cell array is shortened, the number of data that can be read or written to the memory cell array is increased. However, as described above, the delay of the control signal / data signal with respect to? Occupies a greater proportion.

According to the present invention, the pipeline control is introduced into the delay control of γ by using the relationship between the tradeoff between α and γ. That is, the bus (multiple bits) is divided into pipeline registers, and signal transmission in a plurality of divided sections is performed in the pipeline. In the case of a two-stage pipeline, the bus in front of the pipeline and register is divided into a bus in the rear stage, and the first data group is sent to the front bus in the first cycle, and the second data group is sheared in the subsequent second cycle. The first data group is sent to the bus of the next stage which is the output of the pipeline register. With such a configuration, it is possible to reduce the time (timing allowance) per pipeline stage, to reduce the number of data lines for parallel transmission, to reduce the data efficiency and to reduce the power consumption of the memory array. A configuration is provided. In addition, a configuration of a memory array that realizes an increase in the number of data that can be read and written is provided. Specifically, according to the present invention, the transfer of the control signal and the data signal to the memory array (control delay γ) and the transfer of the data signal from the memory array (output delay γ) are configured in a plurality of cycles. In addition, pipeline control is carried out for each cycle. That is, according to the present invention, at least one pipeline register (buffer) is introduced into the bus for transmitting the control signal and the data signal, and the bus at the front end separated by the pipeline register and the output side of the pipeline register. Different data can be co-existed in the same cycle on the bus after the next stage. As a result, the transmission efficiency of control signals and data signals is not reduced, and the time (timing allowance) per pipeline stage can be alleviated.

Further, according to the present invention, a plurality of active regions of the basic unit of the memory array corresponding to each stage of the pipeline are selected for a bus of the pipelined data signal (control signal) to read and write to the memory cell array. It can cope with an increase in the number of data.

In contrast, in the related art, the transmission of the control signal and the data signal (control delay / output delay γ) is not pipelined. In the examples of FIGS. 5, 6, 9, and 10, γ is one cycle. to be. In other words, parallel data is transmitted in parallel on the read write bus RWBS in one clock cycle.

According to the present invention, when the related art of parallel transmission of read and write data on the read write bus RWBS and the number of data that can be read and written are made the same without taking a pipeline configuration, By introducing, the number of paths for transferring the data (the number of data lines of the read write bus RWBS) can be reduced to one-stage of the pipeline. Thus, according to this invention, it becomes possible to aim at low power consumption, without compromising data efficiency.

Further, according to the present invention, by completely separating γ and α, the α which defines the cycle of the memory is shortened and the cycle is shortened. In contrast, in the related art, as shown in Figs. 5, 7, 9 and 10, γ is included in α and is not separated.

More specifically, according to some preferred embodiments, a plurality of bit data (e.g., BL0, BL2) is provided on one data line to be pipeline-controlled in the read write bus RWBS, which is an IO line for data transmission. Is transmitted serially. Data BL0 sent to the read write bus RWBS in the previous cycle arrives at the pipeline register, and is transferred to the data line connected to the output of the pipeline register in the next cycle, and the data at the front end of the pipeline register. BL2, the next data of BL0, is transmitted to the line. Similarly, on the other data line of the read write bus RWBS, a plurality of bit data (for example, BL1, BL3) are synchronized with the transfer of data (for example, BL0, BL2) on the one data line, respectively. Is sent serially.

For example, at the time of WRITE, a data line of the read write bus RWBS is pipelined from the data control circuit to the access region of the memory array basic unit in the near-end side, in order from the data control circuit to the access region of the memory array basic unit in the near-end side. Write data is transmitted.

As an example, data (for example, BL0) to the access area of the memory unit basic unit of the farthest end is sent out on the one data line as soon as possible from the data control circuit, and to the access area of the memory unit basic unit of the latest end. Data (for example, BL2) is finally sent out from the data control circuit onto the one data line. On another data line of the read write bus RWBS, a plurality of bit data (e.g., BL1, BL3) is serially transmitted in synchronization with the transfer of the data (e.g., BL0, BL2) on the data line. At the selection time α, in the memory array basic unit on the far-end side, data BL0 and BL2 sent in parallel from the pipeline register on the read write bus RWBS, and in the most recent memory array basic unit, Data BL1 and BL3 parallelly sent from the data control circuit to the read / write bus RWBS are written to the memory cells in the respective active regions.

On the other hand, at the time of READ, read data from the access area of the latest memory array basic unit is first transmitted on one data line of the read write bus RWBS, and arrives in the data control circuit as soon as possible, The read data from the access area in the basic unit of the memory array is transferred on the same data line, and finally arrives at the data control circuit.

With this arrangement, according to the present invention, the number of data lines of the read write bus RWBS can be reduced. For example, in the configuration of FIG. 6, the number of data lines of the read write bus RWBS is 36x4 = 144 with respect to the configuration of 36 data terminals and burst length BL = 4.

In contrast, according to one aspect of the present invention, for the configuration of 36 data terminals and burst length BL = 4, 36 x 2 = 72 is required as the number of data lines of the read write bus RWBS. That is, according to one aspect of the present invention, the number of data lines is halved. By halving the number of data lines, the power consumed by charging and discharging the data lines is reduced.

Similarly, a pipeline register is provided for the path for transmitting the control signal to the memory array basic unit, and pipeline control is performed.

As described above, Patent Document 1 discloses that the number of data that can be handled is increased by shortening the average latency. That is, by reducing the average latency θ, the time β at which the next command CMD can be input from the command CMD is reduced.

In contrast, according to the present invention, by using the relationship between the latency θ (γ of delay 1) and the trade-off of power, the number of cycles of the selection time α is maintained or reduced, and the number of data that can be handled is increased, We are trying to reduce power. By serially transferring data on the read write bus RWDB that inputs and outputs data to the basic unit of the memory array, the data of the read write bus RWDB can be reduced without reducing the number of data that can be written and read to the memory array. The number of lines (IO lines) can be reduced. On the contrary, when the number of data lines is the same as the number of existing data lines, a configuration in which more data can be written and read is provided. For example, when the present invention is applied to the configuration of Fig. 6 (x36 x BL4 = 144), writing and reading of data of x36 x BL8 = 288 can be realized.

Further, according to the present invention, when the active area of the far-end is accessed or when the near-end active area is accessed, the charge / discharge current generated during the transmission of the control signal and the data signal can be reduced, thereby consuming current. To reduce the This is provided by a pipeline register (buffer) between the memory array basic units on the IO line (data line) for transferring data, so that the data line is divided, and one driver of the data control circuit divides the data. This is because the line is driven. Similarly, for control signals such as an address / command signal, a control line for transmitting the control signal is divided and provided with a pipeline register (buffer) between the memory array basic units.

On the other hand, in the related art such as FIG. 6, one driver of the data control circuit is driving a data line which is commonly installed from the near end to the far end, and the load is increased due to the increase of the memory capacity and the like. By increasing the current driving capability, the charge / discharge current generated at the time of transmission of the data signal is increased. The same problem exists for control signals such as addresses and commands.

Further, according to the present invention, power consumption is reduced by lowering the driving voltage (amplitude) of the control signal and the data signal transmitted to the memory array. Hereinafter, it demonstrates based on some embodiment.

≪ Embodiment 1 >

It is a figure explaining the structure of Embodiment 1 of this invention. In Fig. 11, the same reference numerals are assigned to elements that are the same or equivalent to Figs. Hereinafter, the difference with the related art of FIG. 6 is mainly demonstrated.

It is divided into a plurality of arrays (basic units 11) suitable for a pipeline configuration synchronized with a clock, and control signals such as addresses, commands, and timing signals, and data signals on the read write bus RWBS, which are IO lines for data transmission. Is divided based on the period of the clock signal CLK, and pipeline control is performed for the transmission of the control signal and the data signal. As shown in Fig. 11, the bidirectional buffer (address / command buffer) 13C connected to the address / command bus and the output (address, command, timing signal) of the address / command buffer 13C are connected. The address command sub-controller 12 which controls the basic unit 11 of the memory array is provided in correspondence with the basic unit 11 of the memory array. In addition, a buffer 13A inserted into an address / command bus (ADDRESS / CMD BUS) that transfers control signals such as an address / command and functions as a pipeline register and a read / write bus RWBS is inserted into a pipeline / A buffer 13B serving as a register is provided. The address command sub-controller 12 receives the address / command held in the address / command buffer 13C and outputs it to the memory array basic unit 11. The output of the buffer 13C whose input is connected to the address command bus (ADDRESS / CMD BUS) is connected to the input of the address command sub controller 12 to latch the address / command. The X address (row address) and the control signal output from the address command sub controller 12 are input to the control of the ROW system and the X decoders CTRL and XDEC.

The control circuit (address command timing controller) 6 receives an internal clock, an address, and an address, a command, and an internal clock signal from the command generator 8, similarly to Figs. The address command timing signal is output to (ADDRESS / CMD BUS). In addition, in the example of FIG. 11, although each buffer 13 is a bidirectional buffer (refer FIG. 31 (A)), for example, when it is set as unidirectional buffer structure, such as buffer 13C, FIG. It is good also as a structure as shown in B).

As shown in FIG. 31A, the buffers 13A and 13B are each in the bidirectional data buffer 13A when the WRITE Enable + address space selection logic is active (active) (WRITE Enable is active). Also, when the address space selection logic is active), the information of the WRITE data of the RWBS 130 is passed to the RWBS 134, and when the WRITE Enable + address space selection logic is inactive (i.e., WRITE Enable is enabled). The three-state buffer circuit 131 which is in an inactive state and / or when the address space selection logic is inactive, and becomes an off state (Hi-Z), and the READ Enable + address space selection logic is active (active) When READ Enable is active and the address space selection logic is active, the READ data of the RWBS 134 is passed to the RWBS 130 side, and when the READ Enable + address space selection logic is inactive. (Ie, READ Enable is inactive and / or And a three-state buffer circuit 132 which is in an off state (Hi-Z) when the response space selection logic is in an inactive state. The output of the buffer circuit 131 is connected to the latch circuit 133. The latch circuit 133 is provided with two inverters, one inverter inputs the output of the other inverter, and the output is connected to the input of the other inverter. WRITE Enable is activated at WRITE, and the address space selection logic becomes active when the address signal corresponds to the memory array basic unit connected to the RWBS 134 side. The WRITE Enable or address space selection logic is activated, for example, in synchronization with the memory CLK that defines the cycle. READ Enable is activated at the time of READ, and the address space selection logic is activated when the address signal corresponds to the memory array basic unit connected to the RWBS 134 side. READ Enable or address space selection logic enables in synchronization with the memory CLK that defines the cycle.

In the fourth embodiment of Fig. 26, the READ Enable + address space selection logic and the WRITE Enable + address space selection logic are fixed to the buffers 13A and 13B with respect to the set of buffers 13A and 13B. The function of pipeline control (pipeline register) may be made invalid.

As shown in FIG. 31B, the buffer 13B outputs the address / command of the ADDRESS / CMD BUS 137 when the signal of the Enable + address space selection logic is active (active), and enables + address. The three-state buffer circuit 135 is provided to be in an off state (Hi-Z) when the space selection logic is in an inactive state. The output of the buffer circuit 135 is connected to the latch circuit 136. The latch circuit 136 is provided with two inverters, one inverter inputs the output of the other inverter, and the output is connected to the input of the other inverter. Enable is activated at the time of access, and when the buffer circuit 135 corresponds to the basic unit of memory array to be accessed, the ENABLE + address space selection logic input to the buffer circuit 135 becomes active.

In Fig. 11, the number of data terminals (terminals connected to the internal data bus 9) is 36, the burst length BL = 4, and the read write bus RWBS has 36 x 2 = 72 bidirectional data buses. . The read write bus RWBS extending from the lower memory array basic terminal 11 in the drawing extends through the buffer 13B to the upper memory array basic terminal 11 in FIG. 11. Of the four column data BL0 to BL3 corresponding to the burst length = 4, the 2-bit data of BL0 and BL1 is formed on the two data lines of the read write bus RWBS from the data control circuit 7 before the BL2 and BL3. It is output in parallel and transferred to the active region 10-1 after being latched by the buffer 13B. At the timing at which 2-bit data of BL0 and BL1 are latched in the buffer 13B, 2-bit data of BL2 and BL3 are output from the data control circuit 7 on the two data lines to which BL0 and BL1 are first transmitted. , To the active region 10-2. In addition, the BL2 / 3 data transferred later on two bits of the read write bus RWBS is not latched by the buffer 13B, and the active region 10- of the memory array basic terminal 11 on the upper side of FIG. It is not delivered to 1).

35 is a diagram showing an example of the configuration of the buffers 13A, 13B, and 13C and the memory array basic unit. The memory array basic unit 11 has the same configuration as that in FIG. 4 and includes a column decoder 3. The address signal on the address command bus is input from the buffer 13C to the row decoder XDEC, and the Y address is input to the column decoder YDEC. The control signal (command signal) of the address command bus is input from the buffer 13C to the control circuit CTRL. The read write bus RWBS is connected to the data amplifier / light amplifier 5, and is sense amplifier of a column selected through a Y switch turned on by a column select signal from YDEC through a main IO line and a local IO line. Is connected to. In FIG. 35, for the memory array basic unit 11 at the latest stage, the lower buffers 13A, 13B in the drawing are the control circuit 7 and the data control circuit 6, and the memory array at the farthest end. As for the basic unit 11, the upper buffers 13A and 13B in the figure become the termination circuit of the bus.

FIG. 12 is a diagram illustrating a timing operation of the write operation of FIG. 11. FIG. 13 is a view for explaining the read operation of FIG. 11. In Fig. 11, 4-bit data of BL0-BL3 is serially input at the double data rate to each terminal of the 36 data terminals DQ in correspondence with the burst length = 4.

The address signal, control signal, and timing signal for controlling the active regions 10-1 and 10-2 and the data BL0 / 1 and BL2 / 3 for writing to the active regions 10-1 and 10-2 are: It is transmitted from the control circuit 6 and the data control circuit 7 within two cycles (during the period of?). At this time, the data of BL0 / BL1 is allocated to the active region 10-1 so as to write the data of BL2 / 3 to the active region 10-2.

The row addresses for controlling the active regions 10-1 and 10-2 of the memory array basic unit 11 may be common to the active regions 10-1 and 10-2, or may be different from each other.

In the related art (Figs. 7 and 9), the period? That can be used for the transmission of the control signal and the data signal was one cycle, but as shown in Fig. 12, in the present embodiment, the transmission of the control signal and the data signal is performed. The period γ that can be used is set to 2 cycles. The delay γ of the control signal and data signal transmitted to the active region 10-1 (10-1 control delay) is two cycles, and the delay γ of the control signal and data signal transmitted to the active region 10-2 ( 10-2 control delay) is shorter than 10-1 control delay.

The sub-controller 12 receives the timing signal generated by the control circuit 6, and generates or corrects the timing signal to generate the period α of the ROW cycle time tRC, and also stores information in the buffer 13C or the like. By doing so, the write operation to the memory cells in the basic unit 11 of the memory array in the period α is guaranteed.

As shown in Fig. 12, in the present embodiment, in the period α (= 2 cycles) of the ROW cycle time tRC, the data of BL0 and BL1 is activated among the serially inputted write data BL0-BL3 having a burst length = 4. Parallel writing is performed in the area 10-1, and data in BL2 and BL3 are written in parallel in the active area 10-2.

At the time of READ, as shown in FIG. 13, the control delay and the output delay γ of the active region 10-1 are two cycles, and the control delay and the output delay of the active region 10-2 are the active region ( It is shorter than the control delay and output delay in 10-1). At the selection time α (2 cycles), 2-bit data of BL0 / 1 is read from the active region 10-1, and 2-bit data of BL2 / 3 from the active region 10-2 is read. In the output delay γ, two-bit data of BL2 / 3 from the active region 10-2 arrives at the data control circuit 7 in one cycle. The 2-bit data of BL0 / 1 from the active region 10-1 is delayed from the 2-bit data of BL2 / 3 through the buffer 13C and arrives at the data control circuit 7 over two cycles. The data control circuit 7 converts parallel 4-bit data of BL2, BL3, BL0, and BL1 into serial 4 bits, and is output at two cycles (double data rate) from the data terminal. In total, serial 4-bit read data is output from the 36 data terminals. The cycle from the input of CMD (READ) to the output of the first bit data BL2 is 5 (latency?).

In both WRITE and READ, the control delay / output delay is determined by the characteristics of the memory cell of the far end. The continuous command input interval (CMD to CMD period β) is two cycles, and the active area selection time α is two cycles.

FIG. 14 is a timing chart illustrating another example of write operations in the first embodiment of FIG. 11. Corresponding to burst length = 4, the serial input of 4-bit data in columns BL0 to BL3 requires two cycles. When the BL0 and the BL1 are provided, the transmission of the control signal and the data signal to the access area 10-1 is started.

The previously provided BL0 / BL1 data is transferred from the data control circuit 7 onto the read write bus RWBS through the buffer 13B toward the active region 10-1 in two cycles (two-stage pipeline). (10-1 control delay). If the BL2 / BL3 data inputted serially following the BL0 / BL1 data is provided, transmission of the control signal and the data signal to the access area 10-2 is started. BL2 / BL3 data is transmitted from the data control circuit 7 onto the read / write bus RWBS toward the active region 10-2 (10-2 control delay).

In the control delay γ, control signals and data signals are transmitted in a two-stage pipeline configuration (pipline1 / pipeline2).

An output from the buffers 13A and 13B for inputting the control signal and the data signal to the active region 10-1 transferred on the address command bus and the read / write bus RWBS, respectively, and the control circuits 6 and 7. The output of the control signal and the data signal from the address command command bus, the bus, and the active area 10-2 on the read / write bus RWBS overlaps in timing. Control signals such as addresses / commands are input to the buffer 13C, and the active regions 10-1 and 10-2 of the memory array are selected by the control XDEC circuit.

By the two-stage pipeline (Pipline1 / Pipeline2), BL0 / 1 data is transmitted to the active region 10-1. Further, after the BL2 / 3 data reaches the active region 10-2 by the first stage Pipeline2 corresponding to Pipeline2, the third stage pipeline Pipeline3 actually enables the memory cell array to be active. Data is written into the areas 10-1 and 10-2 (ROW cycle time tRC: alpha).

FIG. 15 is a timing chart showing another read operation example of the first embodiment of FIG. When the CMD (READ command) is input, the control signals (commands) and address signals from the control circuit 6 enter the active regions 10-1 and 10-2 on the address / command bus buffer 13A. Is transmitted by two-stage pipelines (pipline1 / pipeline2) of control delay γ.

In Fig. 15, the control signal (command) / address signal from the control circuit 6 is the respective signals 10-1 control delay and 10-2 control to the active regions 10-1 and 10-2. Delay), but can be transmitted as a common signal. The common signal is more efficient in terms of power consumption.

When the control signal (command) / address signal from the control circuit 6 is made common in the active regions 10-1 and 10-2, the control circuit 6 displays the address / command bus on the first cycle. The control signal (command) / address signal outputted to is transmitted to the active region 10-1 in the second cycle through the buffer 13A. In this second cycle, the control circuit 6 holds the same control signal (command) / address signal as in the first cycle, outputs it on the address / command bus, and transfers it to the active region 10-2. Since the same signal is maintained in the second cycle (High / Low in the case of High / Low in the first cycle), there is no switching of charge and discharge, so the efficiency is good from the viewpoint of power consumption.

Thereafter, the third stage pipeline3 reads data from the memory cell array in the period of the ROW cycle time α.

When the BL0-3 data described in the write operation of FIG. 14 is read, from the active region 10-1, the BL0 / 1 data passes through the two-stage pipeline (pipline4) through the buffer 13C of the read write bus RWBS. / 5) is read into the data control circuit 7, and from the active region 10-2, BL2 / 3 data is controlled by the first stage pipeline4 through the read / write bus RWBS. It is read into the circuit 7.

BL2 / 3 which first arrives from the read write bus RWBS to the data control circuit 7 is serially output in the order of BL2 and BL3 first, and then BL0 / 1 is serially output in the order of BL0 and BL1. The number of cycles from the CMD input until the first data BL2 is output is 5 (= latency?).

The order of the outputs of BL0-BL3 may be rearranged in the step of outputting to the data terminal. Alternatively, the order may be defined as a specification without rearrangement.

14 and 15, the internal operation is omitted for the second and third of the consecutive commands CMD (not shown).

12 and 13, in the case of continuous command input, the ROW cycle time (α: selection time) by the control delay (γ) of the control signal and the data signal and the pipeline operation of the ROW cycle time (α). The cycle of appearance is shortened. That is, in the example shown in Fig. 12, the ROW cycle time (α: selection time) for the command CMD input one time ago, and the control delay (γ) of the control signal and data signal for the current CMD are temporal. Overlapping (coexisting at the same time), the pipeline is working. In the example shown in FIG. 13, the ROW cycle time (α: selection time) for the CMD previously inputted and the control delay of the control signal and the data signal for this CMD in time overlap (coexist at the same time). Pipeline operation, the output delay (γ) for the previously input CMD and the ROW cycle time (α: selection time) for the current CMD overlap in time (coexisting at the same time), have.

The pipelined control of the address / command bus for transmitting control signals such as addresses and commands, and the read / write bus RWBS, which is an IO line for data signal transmission, results in a ROW cycle time for the control delay γ of the control signal and the data signal. (α: selection time), the period of γ is made into a plurality of cycles corresponding to the pipeline control (related art: 1 cycle, this embodiment: 2 cycles), and the cycle number of α is shortened to the cycle number of γ. By matching (3 technologies, 2 cycles of the present embodiment: 2 cycles), a pipeline operation in which a time corresponding to a previous command and a γ of a subsequent command is performed between time-inputted commands successively is performed. All.

In the above, the signal lines of the control signals and data signals of the control circuits 6 and 7 in the memory cell array are pipelined into buffers (pipeline registers), and these signal lines are converted into the control circuit 6 and the data control circuit 7. By sub-controller 12 for dividing and controlling the memory array close to the distant memory array, the delay (control delay / output delay γ) of the control signal and data signal and the ROW cycle tRC (α) are separated. By shortening α, a configuration of a memory cell array that avoids a decrease in the data rate of input / output data of external data is realized.

Next, a description will be made of the read / write bus RWBS in the memory cell array configuration of the present embodiment with respect to the reduction using the tradeoff relationship with respect to power consumption.

It is shown in Table 1 compared with the related art about (alpha), (gamma), (theta). In the related art of Figs. 7A and 7B, control delay γ: 1 cycle, selection time α: 3 cycles, latency θ: 4 cycles, and command interval β: 3 cycles.

In Embodiment 1, control delay and output delay: 2 cycles (= 2γ), selection time: 2 cycles (= (2/3) alpha), latency = 4 cycles (= (5/4) θ), command interval = 2 cycles (= (2/3) β)

The power (power) of the control delay γ in the related art of FIGS. 7A and 7B is set to P = n x c x f ₁ x V ² . In the first embodiment, the control delay γ is two cycles, which is twice the related art, but is divided into two data lines (pipeline registers) of the read / write bus RWBS in units of one cycle by pipeline control. Therefore, since the length of 1/2 of the related art, and hence the capacitance C, is driving 1/2) of the capacity c of the data line of the related art, the drive frequency is f1 which is the same as that of the related art. In the first embodiment, in the read / write bus RWBS, the number of data lines for parallel transfer of bit data is 1/2 of the related art n, and the data lines are divided into two by a pipeline register, and the capacity of the data lines is c /. 2, but because it is a two-stage pipeline, the total capacity is (c / 2) × 2. As a result, the power P1 = (n / 2) x (c / 2) x 2 x f ₁ x V ² = P / 2 of the control delay γ of the first embodiment. That is, 1/2 of the related art. The delay of the selection time is shortened to (2/3), and the power is 3/2 times when the power and the delay product are constant.

In the WRITE operation, the ratio of the power of the first embodiment to the related art is roughly supplied below from the ratio of the sum of the power of the control delay and the selection time in each of the first embodiment and the related art.

Embodiment 1 / related technology = (1/2 + 3/2) / (1 + 1) = 100%

In the READ operation, from the ratio of the sum of the powers of the control delay, the selection time, and the output delay in each of the first embodiment and the related art,

Embodiment 1 / related technology = (1/2 + 3/2 + 1/2) / (1 + 1 + 1) = 83.3%

In the modification of the first embodiment, alpha and beta are coincident for comparison in order to make a constant comparison of the number of data that can be input and output when the semiconductor memory is viewed from the system. When the power delay product is the same and the delay Td1 can be set to 3? (3 cycles), the power can be reduced to 1/3 ideally. The operation of the control circuits 6 and 7 with respect to the control delay γ and the power consumption of data input / output on the read / write bus RWBS are 1/3 times the ratio with the related art. In this modified example, since the ROW cycle time is set to alpha and coincided in the operation of the memory array, the power consumption remains as much as one time of the related art. When the consumption current at the delay of the control signal and the data signal (control delay γ) becomes a magnitude that cannot be overlooked with respect to the consumption current at the ROW cycle time α and is almost equal, the power delay product is derived from the constant. In the WRITE operation, the ratio of the whole power consumption

Variation / Related Technology = (1/3 + 1) / (1 + 1) = 66%

In the READ operation,

Modifications / Related Techniques = (1/3 + 1 + 1/3) / (1 + 1 + 1) = 55.5%

The actual circuit design is complicated, and there are some parts in which power consumption is not determined by the simple calculation as described above. However, even if the current consumption in γ is halved, the total current consumption is 75%.

With the configuration of the memory cell array according to the present embodiment, power consumption can be reduced. When the current consumption at γ cannot be ignored with respect to the current consumption at α, and when (current consumption at γ)> (current consumption at α) proceeds, the effect of the present invention is further increased.

Next, in the first embodiment, the data line (IO line) of the read write bus RWBS in the memory cell array configuration will be described. By assigning BL0 / 1 and BL2 / 3 to the active regions 10-1 and 10-2, respectively, 144 data of the data terminal x36 and burst 4 (BL0-3) are divided into 72 data lines IO for 72 data. Input / output is enabled. In contrast, in the related art of Fig. 6, data is inputted and outputted from the control circuit 7 by data lines (IO lines) for 144 data.

In the first embodiment, this is a configuration of a memory cell array in which the data line (IO line) of the read / write bus RWBS is pipeline controlled, and serial transmission is performed by time division.

Since data is inputted and outputted from the 144 data lines (IO lines) to the memory cell array by 72 data lines (IO lines), it is desirable to utilize the reduced 72 data lines (IO lines) as wiring resources. It becomes possible. For example, it is possible to provide a power supply wiring in an area of a wiring resource for a data line (IO line).

In contrast, in the related art, according to the first embodiment, input and output of 576 data is possible for the configuration of up to 288 IO lines.

≪ Embodiment 2 >

It is common for a semiconductor memory to switch a plurality of operating specifications within the same chip. Next, as Embodiment 2, the burst length 8 of x 36 is demonstrated, and the switching specification in Embodiment 1 is demonstrated.

FIG. 16 schematically shows the configuration of the second embodiment in the case of burst length = 8. In Embodiment 1 of the burst length = 4, the basic unit 11 of the memory array is divided into two, but as shown in FIG. 16, in Embodiment 2, the basic unit 11 of the memory array is divided into four. In the configuration, the columns BL0 / 1, BL2 / 3, BL4 / 5, and BL6 / 7 are allocated to the active regions 10-1, 10-2, 10-3, and 10-4, respectively. For the burst length = 8 and the number of data terminals = 36, the number of data lines of the read write bus RWBS is 72. The address / command bus from the control circuit 6 and the read / write bus RWBS connected to the data control circuit 7 each include three buffers (pipeline registers) 13A and 13B, respectively. A four-stage pipeline is constructed corresponding to the basic unit 11 of the memory array from the near end to the far end.

17 is a view for explaining the timing operation of the WRITE operation of FIG. 16. 18 is a view for explaining the READ operation of FIG. In Fig. 16, 8-bit data corresponding to eight columns BL0-BL7 to be written in accordance with burst length = 8 is serially input to each terminal of the 36 data terminals DQ at a double data rate (4 cycles). do. The control delay γ is assigned four cycles corresponding to the four-stage pipeline.

The address signal for controlling the active region 10-1, the command signal (address, control signal-timing signal), and the data BL0 / 1 to be written to the active region 10-1 are the next two of the CMD input. In the first clock cycle, the control circuit 6 and the data control circuit 7 output the address / command buffer and the read write bus RWBS of the section corresponding to the basic unit of the first memory array. From the first, second and third stage buffers 13A and B to the address / command buffer of the basic unit of the second, third and fourth memory arrays and the read write bus (RWBS) of the fifth clock. Are sent sequentially. The 10-1 control delay is four cycles from the second clock cycle to the fifth clock cycle.

The address signal, control signal and timing signal for controlling the active region 10-2 and the data BL2 / 3 for writing to the active region 10-2 are controlled by the control circuit 6 and data at the third clock. The control circuit 7 outputs the address command buffer of the section corresponding to the first memory array basic unit and the read / write bus RWBS, and the buffers of the first and second stages in the fourth and fifth clocks ( 13A, B) are sequentially transferred to the address / command buffer and read / write bus RWBS in the sections of the second and third memory array basic units. The 10-2 control delay is three cycles from the third clock cycle to the fifth clock cycle.

The address signal, the control signal, and the timing signal for controlling the active area 10-3, and the data BL4 / 5 to be written to the active area 10-3, are controlled by the control circuit 6 and data at the fourth clock. From the control circuit 7 to the address command buffer and the read write bus RWBS of the section corresponding to the first memory array basic unit, and from the first stage buffers 13A and B at the fourth clock, It is transferred to the address / command buffer and read / write bus RWBS of the section of the second memory array basic unit. The 10-3 control delay is two cycles from the fourth clock cycle to the fifth clock cycle.

The address signal, control signal, and timing signal for controlling the active region 10-4 and the data BL6 / 7 for writing to the active region 10-4 are controlled by the control circuit 6 and data at the fifth clock. The control circuit 7 outputs the address / command buffer and the read write bus RWBS in the section corresponding to the first memory array basic unit. The 10-4 control delay is one cycle of the fifth clock only.

Four cycles of the sixth to ninth clock cycles are the selection time α, and parallel two bits are provided in the active regions 10-1, 10-2, 10-3, and 10-4 of the basic units of the four memory arrays. Writing of BL0 / BL1, parallel 2-bit BL2 / BL3, parallel 2-bit BL4 / BL5, and parallel 2-bit BL6 / BL7 is performed. The CMD to CMD period β is four cycles, and in the fifth clock cycle, the first two bits BL0 and BL1 of 8-bit serial data BL0-BL7 corresponding to the next CMD are input serially. The row addresses for controlling the active regions 10-1 and 10-2 of the memory array basic unit 11 may be common to the active regions 10-1 and 10-2, or may be different from each other. .

In the related art (see FIGS. 7 and 9), γ that can be used for the transmission of the control signal and the data signal was one cycle, but as shown in FIG. 17, in the present embodiment, the transmission of the control signal and the data signal is performed. The period γ that can be used is 4 cycles. Delays (10-1, 10-2, 10-3, 10-4 control delays) of control signals and data signals transmitted to the active areas 10-1, 10-2, 10-3, 10-4, 4, 3, 2, 1 cycle.

In this embodiment, the sub-controller 12 receives the timing signal generated by the control circuit 6, and the sub-controller 12 generates a period α of the ROW cycle time tRC by newly generating or correcting the timing signal. By generating and retaining the information in the buffer 13C or the like, the write operation to the memory cells in the basic unit 11 of the memory array in the period α is guaranteed.

In the present embodiment, at the time of READ, as shown in Fig. 18, the address signal and the command signal (address, control signal and timing signal) to the active region 10-1 are controlled by the control circuit (the first clock). 6 is output to the address command bus, and is transmitted to the active region 10-1 over four cycles through the three-stage buffer 13A. The address signal and the command signal to the active region 10-2 are output from the control circuit 6 to the address command bus at the second clock, and the two stage buffer 13A is opened from the control circuit 6. Through this, three cycles are transmitted to the active region 10-2. The address signal and the command signal to the active region 10-3 are output from the control circuit 6 to the address command bus at the third clock, and from the control circuit 6 through the three-stage buffer 13A, It is transmitted to the active area 10-3 in two cycles. The address signal and the command signal to the active region 10-4 are output from the control circuit 6 to the address command bus at the fourth clock and are transmitted to the active region 10-4.

In four cycles from the fifth to the eighth clock cycles, BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7 are read out from the active regions 10-1 to 10-4.

In the ninth clock cycle, the read data BL6, BL7 from the active region 10-4 arrive at the data control circuit 7 in parallel, and in the tenth clock cycle, the data BL6, 7 are in the order of the data BL6, 7. Bit serial output. The data BL4 and BL5 read out from the active region 10-3 arrive at the data control circuit 7 in parallel in the tenth clock cycle through the buffer 13B. 2-bit serial output in order. The data BL2 and BL3 read out from the active region 10-2 arrive at the data control circuit 7 in parallel in the 11th clock cycle through the two-stage buffer 13B, and the data BL2 in the 12th clock cycle. Followed by a 2 bit serial. The data BL0 and BL1 read out from the active region 10-1 arrive at the data control circuit 7 in parallel in the 12th clock cycle through the three-stage buffer 13B and the data in the 13th clock cycle. Output is 2 bit serial in order of BL0, 1. In total, serial 8-bit read data is output from 36 data terminals. The number of cycles from the input of CMD (READ) to the output of the first bit data BL6 is 9 (latency? = 9).

Neither WRITE nor READ operation, the control delay / output delay is determined by the characteristics of the memory cell of the far end. The selection time α of the active region is four cycles.

FIG. 19 is a diagram illustrating a write operation of FIG. 17 in a pipeline. Control delay of 2-bit parallel transmission on the read / write bus RWBS to the active area 10-1 of BL0 and BL1 serially input, among BL0-BL7 inputted in 8-bit serial corresponding to burst length = 8 ( 10-1 control delay) is a 2-bit parallel on the read-write bus RWBS to the active area 10-2 of BL4 and BL3, which are serially input, and the 4-stage pipeline (Pipeline1-Pipeline4) of clock cycles 2-5. The control delay of the transmission (10-2 control delay) is the three-stage pipeline (Pipeline2-Pipeline4) in clock cycles 3-5, the lead write bus (RWBS) to the active area 10-3 of BL4, BL5, which is serially input. The control delay of the 2-bit parallel transmission on the phase (10-3 control delay) leads to a two-stage pipeline (Pipeline3-Pipeline4) with clock cycles 4-5, read writes to the active area 10-4 of the serially inputted BL6 and BL7. The control delay (10-4 control delays) for 2-bit parallel transfers to the bus (RWBS) is the first stage of clock cycle 5 Phosphorus (Pipeline4).

Writing to the active regions 10-1-10-4 (ROW cycle α) is performed by the fifth stage Pipeline 5, and α is 4 cycles.

20 is a diagram illustrating a continuous WRITE operation of FIG. 17 in a pipeline. The CMD to CMD period β is 4 cycles. The next clock cycle 6 of the clock cycle 5 to the end of the control delay γ of the previous CMD (WRITE command) to the four cycles of the clock cycle 9 are the control delays γ of the next CMD (WRITE command) and control of the next CMD (WRITE command). The delay γ overlaps in time with the selection time of 10-1 to 10-4 of the preceding CMD.

FIG. 21 is a diagram illustrating a continuous READ operation of FIG. 18 in a pipeline. The control delay (10-1 control delay) in which the address to the active area 10-1 and the command are transferred to the address / command bus is performed by the four-stage pipeline (Pipeline1-4) and the clock cycles 2-5. The control delay (10-2 control delay) at which the address to the active area 10-2 and the command transfer to the address / command bus are performed (Pipeline2-Pipeline4) and the three stages of the clock cycle 3-5 are active. The control delay (10-3 control delay) in which the address to the area 10-3 and the command are transferred to the address / command bus is performed by the two-stage pipeline (Pipeline3-Pipeline4) and the active area of the clock cycle 4-5. The control delay (10-4 control delay) at which the address to (10-4) and the command to the address / command bus are transferred is the first stage pipeline (Pipeline4) of clock cycle 5. In clock cycles 6-9, 2-bit data is read from the active regions 10-1 to 10-4, respectively.

The 2-bit data BL6 and BL7 read out from the active region 10-4 are supplied to the data control circuit 7 via the read write bus RWBS in clock cycle 10, and in order of BL6 and BL7 in clock cycle 11 It is output as serial. The 2-bit data BL4 and BL5 read out from the active region 10-3 are output to the read write bus RWBS in clock cycle 10, and are supplied to the data control circuit 7 through the buffer 13B of one stage, In clock cycle 12, it is output serially in the order of BL4, BL5. The 2-bit data BL2 and BL3 read out from the active region 10-2 are output to the read write bus RWBS in clock cycle 10, and the data control circuit 7 in clock cycle 11 through the two-stage buffer 13B. Is supplied to and serially outputted in the order of BL2 and BL3 in clock cycle 13. The 2-bit data BL0 and BL1 read out from the active region 10-1 are output to the read write bus RWBS at clock cycle 10, and the data control circuit 7 at clock cycle 11 through the three-stage buffer 13B. Is supplied to and serially output in the order of BL0, BL1 in clock cycle 14.

22 is a timing chart illustrating an operation example of WRITE to READ. The period between CMDs is 4 cycles. In clock cycle 2-5, the next CMD (READ) is input to the control delay of the WRITE command, clock cycle 5, and clock cycle 6-9 overlaps the control delay of READ and the selection time of WRITE in time. Clock cycles 10-13 are the selection times for READ. Clock cycles 10-13 are the output times of the READ. In clock cycles 15-18, the 8-bit serial bits BL6, BL7, BL4, BL5, BL2, BL3, BL0, BL1 are output.

23 is a timing diagram illustrating an operation example of READ to WRITE. The period between CMDs is 4 cycles. In clock cycle 2-5, the next CMD (WRITE) is input to the control delay of the READ command, clock cycle 5, 8-bit serial data is input in four cycles of clock cycles 5-8, and clock cycle 6-9 is set to READ. The control delay and the WRITE selection time overlap each other. Clock cycles 10-13 are the selection times for READ, clock cycles 10-13 are the output times for WRITE, and output delays for READ. In clock cycles 11-14, the 8-bit serial bits BL6, BL7, BL4, BL5, BL2, BL3, BL0, BL1 are output.

In the case of the second embodiment, with the setting of the burst length = 8, the control delay γ = 4 cycles, the selection time alpha = 4 cycles, the command interval = 4 cycles, and the latency at READ = 9.

Also in the second embodiment, as in the first embodiment, a low power consumption means can be obtained by extending the time of the control delay and the output delay γ. In addition, since the number of data becomes 72 IO lines with respect to 288 IO lines, wiring resources can be utilized, and in the case of allowing a large number of data to be handled as in the first embodiment, the reading and writing times are four times in this configuration. It can handle up to 1152 data.

≪ Embodiment 3 >

24 is a diagram for explaining burst length switching. The number of data terminals is 36, the burst length is 8, and 8-bit data serially input / output from one data terminal is written in 8 columns BL0-7 of the active area and read out of 8 columns BL0-7, and 36 Corresponding to 36 data terminals, 36 x 8 pieces = 288 data are read / write. The operation in this case is the same as that of the second embodiment.

When the burst length is set from 8 to 4 (BL0-3), the pipeline control by the buffers 13A1 and 13B1 between the active regions 10-1 and 10-2, and the active regions 10-3 and By making the pipeline control by the buffers 13A3 and 13B3 between 10-4) invalid (pipeline deactivated) (pipeline idle), the same operation as in the first embodiment is performed. When the pipeline pipeline control of the buffer is invalid, that is, the pipeline register function is invalid, the buffers 13A1 and 13B1 and 13A3 and 13B3 output the input through the latch operation. For example, in the case where the buffers 13A1 and 13B1 and the buffers 13A3 and 13B3 comprise a switch and a flip-flop and include a latch (D-type latch) for controlling the through state and the hold state by a clock signal or the like, With the switch on, the input is always output through. In the case where the buffer functions as a pipeline register, for example, the switch is turned on and off to acquire and hold the input in units of cycles.

In the case of the number of data terminals = 36 and the burst length = 2 (BL0, BL1), the pipelined control by the buffers 13A1, 13B1 and 13A3, 13B3 is invalidated and the active region 10- It is set as the structure which invalidates pipeline control by the buffers 13A2 and 13B2 between 2 and 10-3.

In Embodiment 3, the specification which makes the latency (theta) and CMD to CMD period (beta) variable at the root of an access bus becomes possible. When the active area is set to x36 x 2 bits = 72 IOs, the memory array (buffers 13A1-A3 and 13B1-B3 are activated) with a burst length of 8 (BL0-7) and a burst length of 2 (BL0). -1) (only buffers 13A2 and 13B2 are active, buffers 13A1, A3, 13B1 and B3 are inactive), and the active regions 10-1, 10-2, 10-3 and 10- to access. 4) is sufficient depending on the selection address. Β in the CMD to CMD period is made variable in the active regions 10-1, 10-2, 10-3, and 10-4 to be accessed.

25 is a timing chart for explaining the switching of the burst length of the READ operation in the third embodiment.

In Embodiment 3, burst length = 8 is switched to burst length = 2. In this case,? In the CMD to CMD period is varied in the active regions 10-1, 10-2, 10-3, and 10-4 to access. Referring to FIG. 25A, in the case of reading BL0 and BL1 from the access area 10-1, four cycles of 10-1 control delay, 10-1 selection time = 2 cycles, and 10-1 output delay = It becomes four cycles and latency (theta) = 10. CMD to CMD period β = 10. Referring to FIG. 25B, in the case of reading BL2 and BL3 from the access area 10-2, three cycles of 10-2 control delays, 10-2 selection time = 2 cycles, and 10-3 output delays = 3 cycles. Latency θ = 8. CMD to CMD period β = 8. Referring to FIG. 25C, when BL4 and BL5 are read from the access area 10-3, two cycles of 10-2 control delays, 10-2 selection time = 2 cycles, and 10-2 output delays = It becomes two cycles. Latency θ = 6. CMD to CMD period β = 6. Referring to FIG. 25D, when BL6 and BL7 are read from the access area 10-4, one cycle of 10-4 control delay, 10-4 selection time = 2 cycles, and 10-4 output delays = It becomes two cycles. Latency θ = 4. CMD to CMD period β = 4. In the active regions 10-1, 10-2, 10-3, and 10-4, the CMD to CMD period β and the latency θ vary.

≪ Fourth Embodiment >

Since the sub-controller 12 is provided in the memory array basic unit 11, the active regions can be configured as subbanks, respectively. It is a figure explaining Embodiment 4 of this invention. In Fig. 26, four sub-banks 15 are provided per bank 14, and the three-stage buffer 13A1, which functions as a pipeline register in the address command bus and the read / write bus RWBS, is shown in FIG. 13B1), buffers 13A2 and 13B2, and buffers 13A3 and 13B3. In the case of burst length = 8, 8 bits of data BL0-BL7 corresponding to 8 columns BL0-7 are serially input and output to one data terminal, and the read write bus is 36 to 36 data terminals. 2 data lines are provided. Of BL0-BL7 corresponding to burst length = 8, BL0 / 1 transfers the read / write bus through three buffers 13B, and write / read in the access area 10-1, and BL2 / 3 The read / write bus is transmitted through the two buffers 13B, and the write / read is performed in the access area 10-2, and the BL4 / 5 transmits the read / write bus through the one buffer 13B. Writing / reading is performed in the access area 10-3, BL6 / 7 transmits a read / write bus, and writing / reading is performed in the access area 10-4.

When the array for burst length = 8 is switched to burst length = 2, the CMD to CMD periods in the active regions 10-1, 10-2, 10-3, and 10-4 are β-1 and β-2. , beta-3, beta-4 can be specified. In addition, the bank 14 is divided into sub-banks 15 to be controlled. The plurality of active regions 10-1 to 10-4 in the bank 14 can be accessed by controlling the sub-banks. In this case, the timing at which a signal collision (crash) occurs in some cases occurs in the transfer path of the address / command bus (control signal line) and the transfer path of the read / write bus RWBS. The timing at which a signal collision (crash) occurs is defined as a prohibition input for command input. When performing access to the plurality of active regions 10-1 to 10-4 in the bank 14, it is a premise that a command input serving as a prohibited input is not performed.

FIG. 27 is a diagram illustrating an example of a command inhibit input, and illustrates a command (CMD) inhibit rule of subbank to subbank between different subbanks. It is possible to simultaneously access the access regions of different subbanks in a memory array of a plurality of bank configurations. In FIG. 27A, the command interval (READ command interval) of the same subbank is β-1, and in FIG. 27B (D), the command interval of the same subbank is β-2, Although β-3 and β-4 (both burst length = 2), since output delays overlap between different subbanks, command input between the corresponding subbanks is prohibited.

Fig. 28 shows a timing chart of READ and WRITE operations by a common IO line (Common IO: CIO). In Fig. 28A, in the case of READ to WRITE (the WRITE command is input in succession to the READ command), the occupancy of the IO line (lead write bus) by READ occurs, so that the extension of γ remains unchanged. to CMD period β is shown. As will be described later, when the read write bus RWBS is separated IO (Separate IO: SIO) in which each of the common IOs is IOs, β = α.

As shown in Fig. 28B, in READ to READ (continuous force of READ command), β = α = 2 cycles, and as shown in Fig. 28C, the WRITE to WRITE (WRITE command) Continuous input), β = α = 2 cycles. WRITE to READ (WRITE command followed by READ command), REF to * (WRITE / READ / REF) (Refresh command followed by WRITE / READ / REF command), * to REF (WRITE / READ / REF command followed by refresh) Command input) is also β = α.

≪ Embodiment 5 >

29 is a diagram showing the configuration of Embodiment 5 of the present invention. The read write bus RWBS is set to separate IO (SIO), and data lines are separated from WRITE and READ. That is, a WRITE dedicated bus (WBS) 16 and a READ dedicated bus (RBS) 17 are provided, and a buffer 13 is provided between the active regions, respectively. In the WRITE dedicated bus (WBS) 16, write data from the data control circuit 7 to the active area of the memory array is transferred to the pipeline control. The read only bus (RBS) 17 transfers the read data from the active area 10 to the data control circuit 7 by pipeline control.

In the case of the burst length = 8, one bit data terminal is serially input and output with 8-bit data BL0-BL7 corresponding to eight columns BL0-7. For the 36 data terminals, the number of data lines of the WRITE dedicated bus 16 is 36 x 2 = 72, and the number of data lines of the READ dedicated bus (RBS) 17 is 36 x 2 = 72.

Of BL0-BL7 corresponding to burst length = 8, BL0 / 1 transfers the WRITE-dedicated bus (WBS) 16 from the data control circuit 7 via three buffers 13B, and access area 10 -1), BL2 / 3 transfers the WRITE dedicated bus (WBS) 16 from the data control circuit 7 via the two buffers 13B and writes to the access area 10-2. The BL4 / 5 is transferred from the data control circuit 7 to the WRITE dedicated bus (WBS) 16 via one buffer 13B, and written into the access area 10-3, and BL6 / 7. The WRITE dedicated bus (WBS) 16 is transferred from the data control circuit 7 (not transferred before the buffer 13B), and is written to the access area 10-4.

The data BL6 / 7 read out from the access area 10-4 arrives within one cycle from the READ-dedicated bus (RBS) 17 to the data control circuit 7. The data BL4 / 5 read out from the access area 10-3 is transferred to the READ-dedicated bus (RBS) 17 via one buffer 13B and arrives at the data control circuit 7 within two cycles. The data BL2 / 3 read out from the access area 10-2 is transferred to the data control circuit 7 within three cycles by transferring the READ dedicated bus (RBS) 17 through the two buffers 13B. The data BL0 / 1 read out from the access area 10-1 is transferred to the data control circuit 7 within 4 cycles by transferring the READ dedicated bus (RBS) 17 through the three buffers 13B.

30 is a timing chart illustrating the operation of the fifth embodiment of FIG. 29. FIG. 30A is a timing chart of READ to WRITE (where the WRITE command is input subsequent to the READ command), and β is equal to α. 30B and 30C are the same as in FIGS. 29B and 29C, and in READ to READ (the READ command is continuously input), β = α = 2 cycles, In WRITE to WRITE (the WRITE command is input continuously), β = α = 2 cycles. Β = α is also applied to WRITE to READ (the READ command is input in succession to the WRITE command), REF to * (WRITE / READ / REF), and to to REF.

≪ Embodiment 6 >

Next, Embodiment 6 of the present invention will be described. 32 is an example of address allocation. An example of selecting the basic unit 11 of the memory array from X11 and X12 of the X address is shown. The burst length = 8, and eight read / write buses RWBS are provided for one data terminal, and active regions 10-1 corresponding to 288 IO lines are selected for 36 data terminals. Memory array base unit (11 ₁ ) at (X11, X12) = (0, 0), memory array base unit (11 ₂ ), (X11, X12) = (0 at (X11, X12) = (1, 0) , The memory array basic unit 11 ₃ is selected in (1), and the memory array basic unit 1 1 ₄ is selected in (X11, X12) = (1, 1), and the row (word line) in the memory array basic unit 11 is selected. Is selected with 11 bits of X0-X10.

33 shows an example in which the active region is selected in parallel with respect to the control line (address command bus) and the IO line (lead write bus) in the sixth embodiment. X11 and X12 in Fig. 32 become don't (donot) care, and the active area is selected by two bits of X11 and X12 of the X address on the column decoder (COL DECODER) side. Among the data of column BL0-7 corresponding to burst length = 8 input / output corresponding to one data terminal, BL0 / 1, (X11, X12) = (1, 0) at (X11, X12) = (0, 0). ) BL2 / 3, (X11, X12) = (0, 1) at BL4 / 5, (X11, X12) = (1, 1) at BL6 / 7, and each memory array base unit at X0-X10. Rows in are selected. The row decoder ROW DECODER and the column decoder COLUMN DECODER and the row decoder ROW DECODER collectively represent four XDECs on the left side of the figure. A predecoder 18 for switching between rows and columns is provided. In addition, in FIG. 33, the predecoder 18 switches in the setting and test mode at the time of product manufacture. When the column decoder COL DECODER selects an active area from X11 and X12 of the X address, the row decoder ROW DECODER does not decode X11 and X12.

34 is a diagram illustrating a modification of the present embodiment. X11 of the X address is decoded by the row decoder (ROW DECODER) (X12 is don'tcare in the row decoder), and X12 is decoded by the column decoder. X12 of the X address is decoded by the column decoder COL DECODER (in the column decoder, X11 is don'tcare), and the column BL0-7 corresponding to the burst length = 8 input / output corresponding to one data terminal is decoded. Among the data, when X12 = 0, BL0 / 1 and BL2 / 3 are selected, and when X12 = 1, BL4 / 5 and BL6 / 7 are selected. The read write bus RWBS has four data lines (IO lines) for one data terminal, and 144 data lines (IO lines) for 36 data lines. In the row decoder ROW DECODER, when X11 = 0, the memory array basic units 11 ₁ and 11 ₃ are selected, when X11 = 1, the memory array basic units 11 ₂ and 11 ₄ are selected. Select rows in memory array basic units at addresses X0 through X10. At (X11, X12) = (0, 0), BL0-BL3 of the memory array basic unit 11 ₁ , and at (X11, X12) = (1, 0), BL0- of the memory array basic unit (11 ₂ ). BL3, (X11, X12) = (0, 1) in the, in the memory array of the basic unit _{(11 3) BL4-BL7,} (X11, X12) = (1, 1), the memory array base unit (11 ₂₎ BL4-BL7 is selected. At X0-X10, a row in each memory array base unit is selected. In order to select an active region, a predecoder 18 for switching addresses in rows and columns is provided. The switching may be an operating specification of the semiconductor memory (fixed at the time of shipment of the product) or may be a switching in the test mode.

As described above, various derivatives are generated by using Embodiments 1 and 2 as main points.

Pipelining the access latency to the memory cells provides an array configuration that can extend the latency but efficiently utilize the resources of the IO lines in the memory array while reducing cycles. This makes it possible to reduce power consumption by utilizing the trade-off relationship with respect to θ and γ while improving or maintaining α and β, and also to utilize IO line resources in accordance with the division of the active area of the memory array. It became.

In the related art, although the access time due to the perspective of the access bus has been discussed, according to the present invention, in order to reduce power and improve ROW cycles, attention is paid to the IO line in the memory cell array, A memory cell array configuration is provided in which the basic units of the subdivision are divided and a pipeline register and a sub-controller for controlling them are provided to enable operation using a tradeoff relationship between power and delay.

In particular, by dividing and activating a plurality of active areas, data transfer distances by the IO line, such as when accessing a distant memory cell from the control circuits 6 and 7, or when accessing a near memory cell, are different in perspective. By distinguishing the patterns, it becomes possible to control data transfer.

Background Art [0002] The speed of memory cell arrays has been speeded up by shortening the length of the WORD line and the length of the BIT line and subdividing the basic units of the memory cells. As a result, the speed has increased due to the shortening of the ROW cycle α, but the signal of the control circuit and the IO line delay controlling the memory cell array cannot be ignored. By paying attention to the control line and the IO line, the array structure which advances the segmentation of the control line and the IO line makes use of the relationship between the delay time of the control signal, the delay time of the IO line signal, and the trade-off of power. While maintaining or reducing, it was possible to realize a memory cell array configuration capable of reducing power consumption and enabling effective utilization of IO line resources.

In addition, each indication of said patent document shall be included in this book as a reference. Modifications and adjustments of the embodiments are possible within the framework of the entire disclosure (including the scope of the claims) of the present invention and based on the basic technical idea. In addition, various combinations or selections of the various disclosure elements are possible within the framework of the claims of the present invention. That is, the present invention, of course, includes various modifications and modifications that can be made by those skilled in the art according to the entire disclosure and technical spirit including the claims.

1: Memory Cell Array
2: ROW decoder (XDEC)
3: COL decoder (YDEC, COL DECORDER)
4: sense amplifier, Y switch
5: data amplifier / light amplifier
6: Control circuit (address, command, timing controller)
7: Control circuit (Data I / O)
8: Input to DRAM core (Internal CK Address, CMD: Internal Clock, Address, Command)
9: Data input to the DRAM core (Internal Data Bus)
10, 10-1, 10-2, 10-3, 10-4: active area
11: Memory array basic unit (memory macro)
12: Sub controller
13, 13A, 13B, 13C: Buffer
14: Bank
15: Subbank
16: WRITE dedicated bus
17: READ Dedicated Bus
18: pre decoder

Claims (18)

A memory array including a plurality of writeable and readable memory cells is formed of a plurality of basic units,
A first bus which is provided to a plurality of said basic units in common, and to which an address signal / control signal is transmitted;
A second bus which is provided in common to a plurality of the basic units, and to which write data and read data are transferred;
And,
The first bus includes at least one first buffer circuit that functions as a pipeline register,
The second bus includes at least one second buffer circuit that functions as a pipeline register,
A first control circuit which sequentially transmits an address / control signal from the one end of the first bus, in the order from the base unit on the far-end side with respect to the one end, and the basic unit on the near-end side with respect to the one end;
A second control circuit which sequentially transmits data signals from one end on the second bus in order from the far end side basic unit to the one end to the near end side basic unit at the time of writing;
And,
Write data transmitted from the second bus to each of the plurality of basic units is written to each of the plurality of the basic units,
Upon reading, read data from each of the plurality of basic units arrives in the second control circuit in the order of the basic unit on the far-end side from the basic unit on the near-end side via the second bus. The second control circuit outputs the read data that has arrived. The method of claim 1,
The memory array is comprised of first to Nth basic units (where N is a predetermined positive integer of 2 or more),
The first bus includes (N-1) first buffer circuits between (N-1) pairs of adjacent basic units,
The second bus includes parallel M data lines per one data terminal for serially inputting and outputting M × N bit data corresponding to burst length M × N (where M is a predetermined positive integer of 1 or more). (N-1) second buffer circuits provided between adjacent (N-1) pairs of basic units,
The first control circuit sequentially orders the address / control signals from the first base unit to the most basic unit of the first to Nth basic units in the order of the address / control signals from the base unit to the most recent stage. I send it out to a bus every cycle,
At the time of writing, the second control circuit stores the MxN bit data serially inputted from the one data terminal from the data in the most basic terminal unit among the first to Nth basic units. In order of data in a basic unit, M bits are sequentially transmitted in parallel to the M data lines of the second bus in cycles,
M-bit data transmitted from the second bus to each of the first to Nth basic units is written in each M columns of the first to Nth basic units,
At the time of reading, M-bit data read out from each of M columns of the first to Nth basic units is transferred to the second bus so that the most-distant end from M-bit data read from the most recent basic unit. And sequentially arriving in the second control circuit, in the order of the M bit data read from the basic unit of the semiconductor device, wherein the second control circuit outputs M × N bits of data serially from the data terminal. The method of claim 1,
The first bus includes the first buffer circuit between each pair of plural pairs of adjacent basic units,
The second bus includes the second buffer circuit between each pair of adjacent pairs of the basic units,
At least one pair of the plurality of first buffer circuits and the plurality of second buffer circuits, the first buffer circuit and the second buffer circuit function as a pipeline register, and the remaining first buffer circuit and the second buffer A semiconductor device in which a pipeline register function of a buffer circuit is invalidated and made compatible with a plurality of different burst lengths. The method of claim 3,
The memory array is composed of first to Nth basic units (where N = 2 ^ K, K is an integer greater than or equal to 2, ^ is a squared operator),
The first bus includes (N-1) first buffer circuits between adjacent (N-1) pairs of the basic units,
The second bus has M data lines (where M is a predetermined positive integer of 2 or more) per data terminal for serially inputting and outputting the number K of bit data corresponding to the burst length, and (N -(1) having (N-1) second buffer circuits between the pair of adjacent basic units,
When the burst length is M × N, the (N-1) first and second buffer circuits function as pipeline registers,
If the burst length is M × (N / (2 ^ L)) (where L is a predetermined integer equal to or greater than 1 and less than or equal to K, ^ is a squared operation), the adjacent 2 ^ (K-1) basic units are 1 The first buffer circuit and the second buffer circuit between the adjacent sets serve as pipeline registers, and the remaining first and second buffer circuits are set to invalidate pipeline register functions. Semiconductor device. 5. The method according to any one of claims 1 to 4,
And a plurality of third buffer circuits provided corresponding to each of the plurality of basic units and receiving the address / control signal transmitted to the first bus and supplying the first unit to the basic unit. The method according to any one of claims 1 to 5,
A first period corresponding to a control delay consisting of a transfer cycle of address / command to the first bus for write and read access, and a transfer cycle of write data from the write access to the second bus,
In the basic unit of the memory array, with respect to a second period corresponding to a selection time at which writing of data to a selected memory cell or reading from a selected memory cell is performed,
And the first period has a plurality of cycles corresponding to pipeline control, and has a length equal to or greater than the second period. The method according to claim 6,
In the read access, a third period corresponding to an output delay until the data read from the respective basic units is transmitted to the second bus and arrives at the second control circuit following the selection time is determined by the selection time. And a semiconductor device having a length equal to or greater than the second period. The method of claim 7, wherein
And the first period and the third period both have the same length as the second period. 9. The method of claim 8,
The semiconductor device wherein the first and second periods or the first to third periods corresponding to a plurality of commands sequentially inserted in succession are units of pipeline control between commands. 5. The method according to any one of claims 1 to 4,
And a bank including the plurality of subbanks, wherein the plurality of accesses are made to the plurality of subbanks. The method of claim 1,
The second bus,
A write-only bus that transfers write data from the second control circuit to the plurality of basic units;
A read-only bus for transferring read data from the plurality of basic units to the second control circuit
And,
The write-only bus includes at least one second buffer circuit,
And the read-only bus includes at least one second buffer circuit. The method of claim 1,
The memory array is composed of first to Nth basic units (where N = 2 ^ K, K is a predetermined positive integer of 2 or more, ^ is a squared operator),
The row of the basic unit is selected from the first bit group on the lower side of the X address,
One of the first to Nth basic units is selected from a second bit group including K bits higher than the first bit group. The method of claim 1,
The memory array is composed of first to Nth basic units (where N = 2 ^ K, K is an integer of 2 or more),
The row of the basic unit is selected from the first bit group on the lower side of the X address,
And deciding a second bit group including K bits higher than the first bit group by a column decoder to select an access region of the first to Nth basic units. The method of claim 1,
The memory array is composed of first to Nth basic units (where N = 2 ^ K, K is an integer of 2 or more),
The row of the basic unit is selected from the first bit group on the lower side of the X address,
The row decoder and the column decoder decode some bits and other bits of the K bits higher than the first bit group, respectively, to select access regions of the first to Nth basic units. 15. The method according to any one of claims 1 to 14,
The basic unit includes a semiconductor including a first amplifier for receiving and amplifying write data written to a memory cell transferred to the second bus, and a second amplifier for amplifying read data from the memory cell and outputting the read data to the second bus. Device. 6. The method according to claim 1 or 5,
Each buffer circuit of the first and second buffer circuits,
A first third state buffer which receives the write data from the second bus and controls transfer and non-delivery to a rear end side of the second bus by a write permission control signal and address space selection logic;
Receives read data from the rear end side of the first bus to which the output of the first third state buffer is connected, and transfers to the front end side of the first bus by a read permission control signal and address space selection logic, and delivers non-transfer. A second state buffer for controlling the second state;
Latch circuit for latching the output of the first three state buffer
A semiconductor device having a. The method according to claim 5 or 16,
The third buffer circuit includes a three-state buffer that receives the address / control signal from the first bus and controls transfer and non-delivery to the rear end side of the first bus by permission control signals and address space selection logic. ,
Latch circuit for latching the output of the three-state buffer
A semiconductor device having a. The method according to claim 5 or 17,
And a sub-controller that receives an address / control signal from the third buffer circuit and controls the basic unit between the third buffer circuit and the basic unit.

Images