KR20120125172A - Semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device is provided to prevent defects generated in the interface by forming an oxide aluminum film on an amorphous oxide semiconductor layer so that oxygen in the amorphous oxide semiconductor layer is not emitted and heat-treating it. CONSTITUTION: An amorphous oxide is formed on a semiconductor layer. A gate insulating layer(406) is formed on an amorphous oxide semiconductor layer(404). Oxygen is injected into the amorphous oxide semiconductor layer so that the amorphous oxide semiconductor layer comprises an area which contains the oxygen exceeding chemical composition ratio. A gate electrode(410) is formed on the gate insulating layer. An insulating layer which includes an aluminum oxide is formed in the gate electrode.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

A manufacturing method of a semiconductor device and a semiconductor device.

In addition, in this specification, a semiconductor device refers to the general apparatus which can function by using a semiconductor characteristic, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

A technique for constructing a transistor (also referred to as a thin film transistor (TFT)) using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (display device). Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductor materials have attracted attention as other materials.

For example, a transistor using an amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) having an electron carrier concentration of less than 10 ¹⁸ / cm 3 is disclosed as an active layer of the transistor (see Patent Document 1). ).

Japanese Laid-Open Patent Publication No. 2006-165528

However, in a semiconductor device having an oxide semiconductor, the electrical conductivity changes when hydrogen, moisture, or the like forming an electron donor occurs in the thin film forming step of the oxide semiconductor. Moreover, even when the oxide semiconductor thin film formed has oxygen deficiency, there exists a possibility that an electrical conductivity may change. This phenomenon becomes a factor of fluctuation of electrical characteristics in the transistor using the oxide semiconductor.

In view of these problems, it is an object of the present invention to provide a stable semiconductor device to a semiconductor device using an oxide semiconductor and to provide a highly reliable semiconductor device.

A semiconductor device according to the present invention includes an amorphous oxide semiconductor layer having a region containing oxygen in excess of a stoichiometric composition ratio (i.e., oxygen in excess of stoichiometry), and an aluminum oxide film formed on the amorphous oxide semiconductor layer. It is composed. The amorphous oxide semiconductor layer is subjected to oxygen injection treatment to a crystalline or amorphous oxide semiconductor layer subjected to dehydration or dehydrogenation treatment, and thereafter, heat treatment is performed to maintain an amorphous state in the state where an aluminum oxide film is formed. It is formed by. The temperature of the said heat processing is 450 degrees C or less. More specifically, it can be set as the following structures, for example.

One embodiment of the present invention provides an amorphous oxide semiconductor layer having a region containing oxygen exceeding a stoichiometric composition ratio, a source electrode and a drain electrode electrically connected to the amorphous oxide semiconductor layer, and a gate overlapping the amorphous oxide semiconductor layer. A semiconductor device having an electrode, an amorphous oxide semiconductor layer, a gate insulating layer formed between the gate electrode, and an aluminum oxide film formed on the amorphous oxide semiconductor layer.

Another embodiment of the present invention is an amorphous oxide semiconductor layer having a region containing oxygen exceeding a stoichiometric composition ratio, a source electrode and a drain electrode electrically connected to the amorphous oxide semiconductor layer, a source electrode and a drain electrode And a gate insulating layer formed over the amorphous oxide semiconductor layer, a gate electrode formed over the gate insulating layer and overlapping with the amorphous oxide semiconductor layer, and an aluminum oxide film formed over and in contact with the gate electrode.

In another embodiment of the present invention, a gate electrode, a gate insulating layer formed on the gate electrode, and a region formed on the gate insulating layer overlapping with the gate electrode and containing oxygen exceeding the stoichiometric composition ratio are provided. A semiconductor device having an amorphous oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the amorphous oxide semiconductor layer, and an aluminum oxide film formed on the amorphous oxide semiconductor layer in contact with at least a portion of the amorphous oxide semiconductor layer.

In any of the above semiconductor devices, the gate insulating layer preferably has a region containing oxygen exceeding the stoichiometric composition ratio.

In any of the above semiconductor devices, it is preferable to have an oxide insulating film between the aluminum oxide film and the amorphous oxide semiconductor layer, and the oxide insulating film has a region containing oxygen exceeding the stoichiometric composition ratio.

In addition, in this specification etc., the term "above" does not limit that the positional relationship of a component is "right above." For example, the expression "gate electrode on the gate insulating layer" does not exclude the inclusion of another component between the gate insulating layer and the gate electrode. The same applies to the term "below".

In addition, in this specification etc., the terms "electrode" and "wiring" do not functionally limit these components. For example, "electrode" may be used as part of "wiring" and vice versa. The term "electrode" or "wiring" also includes the case where a plurality of "electrodes" and "wiring" are formed integrally.

By injecting oxygen, the amorphous oxide semiconductor layer contains an excess of oxygen, and heat treatment is performed in a state where an aluminum oxide film is formed on the amorphous oxide semiconductor layer so that oxygen in the amorphous oxide semiconductor layer is not released. It can be prevented that a defect is produced | generated at the interface with the layer which contact | connects up and down, or that a defect increases. That is, since excess oxygen contained in the amorphous oxide semiconductor layer acts to fill the oxygen vacancies defect, a highly reliable semiconductor device having stable electrical characteristics can be provided.

1A to 1C are plan views and cross-sectional views illustrating one embodiment of a semiconductor device.
2A to 2C are plan views and cross-sectional views illustrating one embodiment of a semiconductor device.
3A to 3D are cross-sectional views illustrating one embodiment of a method of manufacturing a semiconductor device.
4A to 4D are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device.
5A to 5C are plan views and cross-sectional views illustrating one embodiment of a semiconductor device.
6A to 6C are plan views and cross-sectional views illustrating one embodiment of a semiconductor device.
7A to 7D are cross-sectional views illustrating one embodiment of a method of manufacturing a semiconductor device.
8A to 8D are cross-sectional views illustrating one embodiment of a method of manufacturing a semiconductor device.
9A to 9C illustrate one embodiment of a semiconductor device.
10 is a view for explaining an embodiment of a semiconductor device;
11 is a view for explaining one embodiment of a semiconductor device.
12 illustrates one embodiment of a semiconductor device.
13A and 13B illustrate one embodiment of a semiconductor device.
14A-14F illustrate electronic devices.
15A1, 15A2, 15B1, and 15B2 show the measurement results of SIMS of samples prepared in Example 1. FIG.
Fig. 16A1, Fig. 16A2, Fig. 16B1, and Fig. 16B2 show the measurement results of SIMS of a sample produced in Example 1;
17A to 17D show measurement results of TDS of a sample prepared in Example 1. FIG.
18A to 18D show measurement results of TDS of a sample prepared in Example 1. FIG.
19A to 19C are diagrams showing a TEM image of a sample produced in Example 2. FIGS.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention disclosed in this specification is described in detail using drawing. However, the invention disclosed in this specification is not limited to the following description, and it can be easily understood by those skilled in the art that the form and details can be variously changed. In addition, invention disclosed in this specification is not limited to the description content of embodiment shown below.

In addition, in this specification etc., the ordinal numbers used as 1st and 2nd are used for convenience, and do not represent a process order or a lamination order. In addition, in this specification etc., it does not show the original name as a matter for specifying invention.

(Embodiment 1)

In this embodiment, one embodiment of the semiconductor device and the manufacturing method of the semiconductor device will be described with reference to FIGS. 1A to 3D.

1A to 1C show a plan view and a cross-sectional view of a top gate transistor 510 as an example of a semiconductor device. 1A is a plan view of the transistor 510, and FIGS. 1B and 1C are cross-sectional views taken along the A-B cross section and the C-D cross section in FIG. 1A, respectively. In addition, in FIG. 1A, some components (for example, the gate insulating layer 406, etc.) of the transistor 510 are omitted in order to avoid the trouble.

The transistor 510 shown in FIGS. 1A to 1C has a base insulating layer 402, an amorphous oxide semiconductor layer 404, a source electrode 405a, and a drain electrode 405b on a substrate 400 having an insulating surface. ), A gate insulating layer 406, a gate electrode 410, and an insulating layer 412.

In the transistor 510 illustrated in FIGS. 1A to 1C, the amorphous oxide semiconductor layer 404 has a region (hereinafter also referred to as an excess oxygen region) containing oxygen exceeding the stoichiometric composition ratio. In general, oxygen, which is one of the main components constituting the amorphous oxide semiconductor layer 404, dynamically repeats bonding and dissociation with a metal element, which is one of the other main component materials in the film. Since the metal element dissociated with oxygen has unbound water, it is considered that a certain number of oxygen deficiencies in which oxygen is dissociated exist in the amorphous oxide semiconductor layer. However, in the transistor of one embodiment of the present invention, the excess oxygen contained in the amorphous oxide semiconductor layer 404 can immediately fill in defects (oxygen defects) due to oxygen vacancies in the amorphous oxide semiconductor layer 404. have. Therefore, a highly reliable semiconductor device having stable electrical characteristics can be provided.

The amorphous oxide semiconductor layer 404 has an amorphous structure throughout the film.

In the transistor 510, a layer including an aluminum oxide film is formed as the insulating layer 412. Since the aluminum oxide has a barrier function that it is difficult to permeate hydrogen, moisture, oxygen, and other impurities, impurities such as moisture can be prevented from invading from the outside after completion of the device. In addition, the insulating layer 412 should just have an aluminum oxide film at least, and it is good also as a laminated structure of the film containing an aluminum oxide film and another inorganic insulating material. In addition, when the insulating layer 412 has a laminated structure with a film containing another inorganic insulating material, the film containing the other inorganic insulating material is located on the side of the amorphous oxide semiconductor layer 404, and furthermore, It is more preferable that it is an oxide insulating film which has. For example, the insulating layer 412 can be a laminated structure of an silicon oxide film having an excess oxygen region and an aluminum oxide film from the amorphous oxide semiconductor layer 404 side.

It is preferable that the gate insulating layer 406 has an excess oxygen region. If the gate insulating layer 406 has an excess oxygen region, it is possible to prevent the movement of oxygen from the amorphous oxide semiconductor layer 404 to the gate insulating layer 406, and further, from the gate insulating layer 406, to the amorphous oxide. This is because oxygen can be supplied to the semiconductor layer 404. Similarly, the underlying insulating layer 402 preferably has an excess oxygen region.

In addition, an insulating layer may be further formed on the transistor 510. Moreover, in order to electrically connect the source electrode 405a, the drain electrode 405b, and wiring, an opening may be formed in the gate insulating layer 406 or the like. In addition, the amorphous oxide semiconductor layer 404 does not have to be processed into an island shape.

2A to 2C show another configuration example of the transistor according to the present embodiment. 2A is a plan view of the transistor 520, and FIGS. 2B and 2C are cross-sectional views taken along the E-F cross section and the G-H cross section in FIG. 2A. In addition, in FIG. 2A, some components (for example, the gate insulating layer 406, etc.) of the transistor 520 are omitted in order to avoid complications.

The transistor 520 shown in FIGS. 2A to 2C is, like the transistor 510 shown in FIGS. 1A to 1C, on the substrate 400 having an insulating surface, the underlying insulating layer 402 and the amorphous oxide semiconductor layer. 404, a source electrode 405a, a drain electrode 405b, a gate insulating layer 406, a gate electrode 410, and an insulating layer 412.

The difference between the transistor 520 shown in FIGS. 2A-2C and the transistor 510 shown in FIGS. 1A-1C is that the source electrode 405a, the drain electrode 405b, and the amorphous oxide semiconductor layer 404 are different from each other. Lamination order. That is, the transistor 520 includes the source electrode 405a and the drain electrode 405b in contact with the underlying insulating layer 402, and the amorphous oxide semiconductor layer 404 formed on the source electrode 405a and the drain electrode 405b. Have The other structure is the same as that of the transistor 510, and the description regarding the transistor 510 can be referred to for details.

Hereinafter, an example of the manufacturing process of the transistor 510 is shown using FIGS. 3A-3D. The transistor 520 can be manufactured by the same process as the transistor 510 except for the stacking order of the source electrode 405a and the drain electrode 405b and the amorphous oxide semiconductor layer 404.

First, a base insulating layer 402 is formed on a substrate 400 having an insulating surface. Although there is no big restriction | limiting in the board | substrate which can be used for the board | substrate 400 which has an insulating surface, it is necessary to have heat resistance at least enough to endure later heat processing. For example, glass substrates, such as barium borosilicate glass and alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can be used. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like may be used, and a semiconductor element formed on these substrates may be used as the substrate 400. .

As the substrate 400, a flexible substrate may be used. In the case of using a flexible substrate, a transistor containing an oxide semiconductor film may be produced directly on the flexible substrate, or a transistor containing an oxide semiconductor film may be prepared on another fabrication substrate, and then peeled and transferred to the flexible substrate. Moreover, what is necessary is just to form a peeling layer between a fabrication board | substrate and the transistor containing an oxide semiconductor film, in order to peel and transfer from a fabrication board | substrate to a flexible board | substrate.

The base insulating layer 402 contains silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, gallium oxide, or a mixed material thereof. It can have a single layer or a laminated structure selected from the film. However, when the base insulating layer 402 is formed as a laminated structure containing an oxide insulating film, it is preferable that the oxide insulating film is in contact with the amorphous oxide semiconductor layer 404 formed later. In this embodiment, the silicon oxide film is formed by the plasma CVD method, the sputtering method, or the like as the base insulating layer 402.

In addition, if the underlying insulating layer 402 has an excess oxygen region, it is preferable because excess oxygen contained in the underlying insulating layer 402 can compensate for the oxygen deficiency of the amorphous oxide semiconductor layer 404. When the underlying insulating layer 402 has a laminated structure, it is preferable to have an excess oxygen region in at least the layer in contact with the amorphous oxide semiconductor layer 404. In order to form an excess oxygen region in the underlying insulating layer 402, the underlying insulating layer 402 may be formed, for example, in an oxygen atmosphere. Alternatively, oxygen (at least one of oxygen radicals, oxygen atoms, and oxygen ions) may be injected into the base insulating layer 402 after film formation to form an oxygen excess region. As the method of injecting oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

Subsequently, an amorphous oxide semiconductor layer 404a having a film thickness of 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less is formed on the underlying insulating layer 402 (see FIG. 3A).

As the oxide semiconductor material, a metal oxide material containing two or more selected from In, Ga, Zn, and Sn may be used. For example, an In-Sn-Ga-Zn-O-based material which is a quaternary metal oxide, an In-Ga-Zn-O-based material which is a ternary metal oxide, an In-Sn-Zn-O-based material, In-Al-Zn-O-based material, Sn-Ga-Zn-O-based material, Al-Ga-Zn-O-based material, Sn-Al-Zn-O-based material, Hf-In-Zn- In-Zn-O-based material, Sn-Zn-O-based material, Al-Zn-O-based material, Zn-Mg-O-based material, Sn-Mg, O-based material or binary metal oxide -O-based material, In-Mg-O-based material, In-Ga-O-based material, In-O-based material, Sn-O-based material, Zn-O-based material, etc. may be used. . The oxide semiconductor may contain an element other than In, Ga, Sn, and Zn, for example, SiO ₂ .

Here, for example, an In—Ga—Zn—O based oxide semiconductor means an oxide semiconductor having indium (In), gallium (Ga), and zinc (Zn), and the composition ratio does not matter.

As the amorphous oxide semiconductor layer 404a, a thin film represented by the formula InMO ₃ (ZnO) _m (m> 0) can be used. Here, M represents one or a plurality of metal elements selected from Zn, Ga, Al, Mn and Co. For example, Ga, Ga and Al, Ga and Mn, or Ga and Co as M, for example.

In the case of using an In—Sn—Zn—O-based material as the oxide semiconductor, the composition ratio of the target to be used is an atomic ratio, and In: Sn: Zn = 1: 2: 2, In: Sn: Zn = 2 It is good to set it as 1: 1, In: Sn: Zn = 1: 1: 1.

In the case of using an In—Zn—O based material as the oxide semiconductor, the composition ratio of the target to be used is, in atomic ratio, In: Zn = 50: 1 to 1: 2 (in terms of molar ratio), In ₂ O ₃ : ZnO = 25: 1 to 1: 4), preferably In: Zn = 20: 1 to 1: 1 (In ₂ O ₃ : ZnO = 10: 1 to 1: 2 in terms of molar ratio), more preferably In: Zn = 15: 1 to 1.5: 1 (In ₂ O ₃ : ZnO = 15: 2 to 3: 4 in terms of molar ratio). For example, the target used for forming an In—Zn—O based oxide semiconductor is Z ≧ 1.5 × + Y when the atomic ratio is In: Zn: O = X: Y: Z.

It is preferable to form the amorphous oxide semiconductor layer 404a by sputtering. In addition, when forming the amorphous oxide semiconductor layer 404a by the sputtering method, it is preferable to reduce the hydrogen concentration contained in the amorphous oxide semiconductor layer 404a as much as possible. In order to reduce the hydrogen concentration, as an atmosphere gas supplied into the processing chamber of the sputtering apparatus, high purity rare gas (typically argon), oxygen, and rare gas in which impurities such as hydrogen, water, a compound having a hydroxyl group, or a hydride are removed And mixed gas of oxygen are suitably used. In addition, it is preferable to use the cryopump which has high water exhaust capability or the sputtering ion pump which has high exhaust capability of hydrogen for exhaust of the said process chamber.

In addition, it is preferable that the underlying insulating layer 402 and the amorphous oxide semiconductor layer 404a be formed continuously without being released into the atmosphere. For example, after the impurities containing hydrogen adhered to the surface of the substrate 400 are removed by heat treatment or plasma treatment, the underlying insulating layer 402 is formed without being released into the atmosphere, and is subsequently amorphous without being released into the atmosphere. The oxide semiconductor layer 404a may be formed. In this way, impurities containing hydrogen adhering to the surface of the base insulating layer 402 are reduced, and the interface between the substrate 400 and the base insulating layer 402, and the base insulating layer 402 and amorphous It is possible to suppress the attachment of atmospheric components to the interface of the oxide semiconductor layer 404a. As a result, the transistor 510 having good electrical characteristics and high reliability can be manufactured.

In addition, before forming the amorphous oxide semiconductor layer 404a by sputtering, reverse sputtering that introduces argon gas to generate plasma is also performed on the surface of the underlying insulating layer 402 (also called particles and dust). It is preferable to remove). Reverse sputtering is a method of modifying a surface by applying a voltage using an RF power supply to a substrate side in an argon atmosphere without applying a voltage to the target side, thereby forming a plasma in the vicinity of the substrate. In addition, nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere.

Next, heat treatment (first heat treatment) for removing (dehydrating or dehydrogenating) hydrogen (containing water or hydroxyl groups) is performed on the amorphous oxide semiconductor layer 404a. The temperature of the heat treatment is a temperature at which the amorphous oxide semiconductor layer 404a is not crystallized, and is typically 250 ° C or more and 450 ° C or less, preferably 300 ° C or less.

By this heat treatment, hydrogen, which is an n-type impurity, can be removed from the oxide semiconductor, and high purity can be obtained so that impurities are not contained as much as possible. For example, the hydrogen concentration contained in the amorphous oxide semiconductor layer 404a after the dehydration or dehydrogenation treatment can be 5 × 10 ¹⁹ / cm 3 or less, or 5 × 10 ¹⁸ / cm 3 or less.

In addition, if the heat treatment for dehydration or dehydrogenation is performed before processing the amorphous oxide semiconductor layer 404a into an island shape, the oxygen contained in the underlying insulating layer 402 can be prevented from being released by the heat treatment. desirable.

Moreover, in heat processing, it is preferable that nitrogen, or rare gases, such as helium, neon, argon, do not contain water, hydrogen, etc. Alternatively, the purity of nitrogen introduced into the heat treatment apparatus, or rare gases such as helium, neon, and argon is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (ie, impurity concentration is 1 ppm or less, preferably 0.1 ppm). It is preferable to set it as below).

Next, the amorphous oxide semiconductor layer 404a is processed into an island-shaped amorphous oxide semiconductor layer 404 by a photolithography process. Moreover, you may form the resist mask for forming the island shape amorphous oxide semiconductor layer 404 by the inkjet method. When the resist mask is formed by the inkjet method, since no photomask is used, the manufacturing cost of the semiconductor device can be reduced.

Subsequently, a conductive film serving as a source electrode and a drain electrode (including a wiring formed in the same layer as this) is formed over the amorphous oxide semiconductor layer 404 and processed to form the source electrode 405a and the drain electrode 405b. (See FIG. 3B).

As a conductive film used for the source electrode 405a and the drain electrode 405b, a material capable of withstanding a later heat treatment step is used. For example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, W, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above element as a component. Etc. can be used. A high melting point metal film such as Ti, Mo, W, or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is laminated on one or both of the lower and upper sides of the metal film such as Al and Cu. It is good also as a structure. Moreover, you may form with electroconductive metal oxide as a conductive film used for a source electrode and a drain electrode. Examples of conductive metal oxides include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (abbreviated as In ₂ O ₃ -SnO ₂ , ITO), and indium zinc oxide (In ₂ O ₃ -ZnO) or those in which silicon oxide is contained in these metal oxide materials can be used.

In addition, during etching of the conductive film, it is desirable to optimize the etching conditions so that the amorphous oxide semiconductor layer 404 is etched and not broken. However, it is difficult to obtain a condition that only the conductive film is etched and that the amorphous oxide semiconductor layer 404 is not etched at all. Part of the amorphous oxide semiconductor layer 404 is etched at the time of etching the conductive film to form grooves (concave portions). It may become an amorphous oxide semiconductor layer to have.

Subsequently, a gate insulating layer 406 is formed to cover the source electrode 405a and the drain electrode 405b and to contact a part of the amorphous oxide semiconductor layer 404.

The gate insulating layer 406 is preferably formed using a plasma CVD method or a sputtering method, and includes a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or It can be formed as a silicon nitride oxide film. Alternatively, as the material of the gate insulating layer 406, hafnium oxide, yttrium oxide, lanthanum oxide, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), and hafnium aluminate (HfAl _x O _y (x> 0) , y> 0)), hafnium silicate added with nitrogen, and hafnium aluminate added with nitrogen may be used. By using these high-k materials, the gate leakage current can be reduced. The gate insulating layer 406 may have a single layer structure or a laminated structure.

In addition, when the gate insulating layer 406 has an excess oxygen region, the oxygen deficiency of the amorphous oxide semiconductor layer 404 can be compensated for by the excess oxygen contained in the gate insulating layer 406.

Subsequently, oxygen 421 is injected into the amorphous oxide semiconductor layer 404 from the gate insulating layer 406 to form an oxygen excess region (see FIG. 3C). By the injection processing of oxygen 421, oxygen in the amorphous oxide semiconductor layer 404 which is simultaneously reduced by heat treatment for the purpose of dehydration or dehydrogenation can be supplied. Thereby, the amorphous oxide semiconductor layer 404 can be highly purified and electrically i-type (intrinsic). In addition, the oxygen deficiency can be compensated for by forming the excess oxygen region in the amorphous oxide semiconductor layer 404. As a result, the charge trapping center in the amorphous oxide semiconductor layer 404 can be reduced.

As a method of injecting oxygen 421, a method capable of injecting oxygen 421 into the amorphous oxide semiconductor layer 404 or into an interface is used. For example, an ion implantation method or an ion doping method can be used. The ion implantation method is a method of converting a source gas into a plasma, extracting and separating the ionic species contained in the plasma, accelerating ionic species having a predetermined mass, and implanting the ion gas as an ion beam into the workpiece. In addition, the ion doping method is a method in which a source gas is converted into a plasma, ionic species are extracted from plasma by the action of a predetermined electric field, the extracted ionic species are accelerated without mass separation, and implanted into the target object as an ion beam. to be. By injecting oxygen 421 using an ion implantation method involving mass separation, it is possible to prevent impurities such as metal elements from being added to the amorphous oxide semiconductor layer 404 together with the oxygen 421. In addition, since the ion doping method can increase the area to which the ion beam is irradiated compared with the ion implantation method, the take time can be shortened by implanting the oxygen 421 using the ion doping method.

Alternatively, a plasma immersion ion implantation method may be used as the implantation method of oxygen 421. The plasma immersion ion implantation method can efficiently inject oxygen 421 even when the amorphous oxide semiconductor layer 404 is irregular in shape.

In addition, in this embodiment, the example which injects oxygen 421 into the amorphous oxide semiconductor layer 404 through the gate insulating layer 406 is shown. Injecting the oxygen 421 into the amorphous oxide semiconductor layer 404 over the film laminated on the amorphous oxide semiconductor layer 404 makes it easier to control the injection depth (injection region) of the oxygen, thus making the amorphous oxide semiconductor There is an advantage that the oxygen 421 can be injected efficiently into the layer 404. However, the embodiment of the present invention is not limited thereto, and the surface of the amorphous oxide semiconductor layer 404 is exposed (that is, before forming the conductive films to be the source electrode 405a and the drain electrode 405b), or It is also possible to carry out after the formation of the insulating layer 412.

The injection depth of the oxygen 421 may be controlled by appropriately setting the injection conditions such as the acceleration voltage and the dose, and the film thickness of the gate insulating layer 406 to pass. By the oxygen injection process, the content of oxygen in the amorphous oxide semiconductor layer 404 is made to exceed the stoichiometric composition ratio. For example, it is preferable to set the peak of the oxygen concentration in the amorphous oxide semiconductor layer 404 introduced by the oxygen injection treatment to be 1 × 10 ¹⁸ / cm 3 or more and 5 × 10 ²¹ / cm 3 or less. The injected oxygen 421 contains oxygen radicals, oxygen atoms, and / or oxygen ions. In addition, the oxygen excess region should just exist in a part (including an interface) of the amorphous oxide semiconductor layer 404.

In the oxide semiconductor, oxygen is one of the main components. For this reason, it is difficult to accurately estimate the oxygen concentration in the oxide semiconductor film using a method such as Secondary Ion Mass Spectrometry (SIMS). That is, it can be said that it is difficult to determine whether oxygen was intentionally added to the amorphous oxide semiconductor layer.

However, oxygen has a ratio of their presence in the isotope is present, and the natural world, such as ¹⁷ O and ¹⁸ O is known that the each of 0.037% of the oxygen atoms, 0.204%. In other words, since the concentration of these isotopes in the amorphous oxide semiconductor layer is such that it can be estimated by a method such as SIMS, it is more accurate to estimate the oxygen concentration in the amorphous oxide semiconductor layer by measuring these concentrations. There is a possibility. Therefore, by measuring these concentrations, it may be determined whether oxygen is intentionally added to the amorphous oxide semiconductor layer.

In addition, part of the oxygen 421 added to (included) the amorphous oxide semiconductor layer 404 may have an unbonded number of oxygen in the oxide semiconductor. This is because by having unbound water, hydrogen can be immobilized (non-movable ionization) by bonding with hydrogen remaining in the film.

Subsequently, a conductive film serving as a gate electrode (including a wiring formed in the same layer as this) is formed over the gate insulating layer 406, and is processed to form a gate electrode 410. The gate electrode 410 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material containing these as a main component by plasma CVD or sputtering. As the gate electrode 410, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. The gate electrode 410 may have a single layer structure or a laminated structure.

Next, an insulating layer 412 covering the gate electrode 410 is formed (see FIG. 3D). As the insulating layer 412, a layer containing an aluminum oxide film can be used. That is, the insulating layer 412 includes aluminum oxide. The aluminum oxide film has a barrier function of being difficult to permeate moisture, oxygen, and other impurities. Therefore, by forming the aluminum oxide film on the amorphous oxide semiconductor layer 404, the aluminum oxide film functions as a passivation film, and after completion of the device, impurities such as moisture can be prevented from invading the amorphous oxide semiconductor layer 404 from the outside. have. In addition, the release of oxygen from the amorphous oxide semiconductor layer 404 can be prevented.

In addition, the insulating layer 412 may be a laminated structure of an oxide insulating film (for example, a silicon oxide film, a silicon oxynitride film, etc.) having an excess oxygen region, and an aluminum oxide film.

The insulating layer 412 can be formed using a method which does not mix impurities, such as water and hydrogen, in the insulating layer 412, such as a sputtering method, making it the film thickness at least 1 nm or more. If hydrogen is contained in the insulating layer 412, the hydrogen may invade the amorphous oxide semiconductor layer 404 or the extraction of oxygen in the amorphous oxide semiconductor layer 404 by hydrogen may occur. Therefore, it is important not to use hydrogen in the film formation method so that the insulating layer 412 is a film containing no hydrogen as much as possible. As the sputtering gas used for forming the insulating layer 412, it is preferable to use a high purity gas from which impurities such as hydrogen, water, a compound having a hydroxyl group, or a hydride are removed.

After the formation of the insulating layer 412, heat treatment (second heat treatment) is performed. The temperature of the heat treatment is a temperature at which the amorphous oxide semiconductor layer 404 is not crystallized, preferably 250 ° C or more and 450 ° C or less. The heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppm or less), or a rare gas (argon, helium, etc.). It is preferable that water, hydrogen, etc. are not contained in atmospheres, such as oxygen, super dry air, or a rare gas. In addition, the purity of nitrogen, oxygen, or rare gas introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). desirable.

The timing of the heat treatment (second heat treatment) after the oxygen injection treatment is not limited to the configuration of the present embodiment, but the heat treatment must be performed at least after the formation of the insulating layer 412. The aluminum oxide film used as the insulating layer 412 has a high blocking effect (blocking effect) that does not transmit the film to both impurities such as hydrogen, moisture, and oxygen, and heat-processes the insulating layer 412 after film formation. This is because release of oxygen from the amorphous oxide semiconductor layer 404 can be prevented.

In addition, oxygen is brought into contact with the amorphous oxide semiconductor layer 404 by the second heat treatment, and the oxygen oxide insulating layer is formed from an insulating film containing oxygen (for example, the gate insulating layer 406 or the underlying insulating layer 402). 404 may be supplied.

The transistor 510 is formed by the above process (see FIG. 3D). The transistor 510 intentionally excludes impurities such as hydrogen, water, hydroxyl groups, or hydrides (also referred to as hydrogen compounds) from the amorphous oxide semiconductor layer by heat treatment for the purpose of dehydration or dehydrogenation, and thereafter oxygen. By the injection treatment, oxygen which is simultaneously reduced by heat treatment for the purpose of dehydration or dehydrogenation can be supplied to the amorphous oxide semiconductor layer. As a result, the amorphous oxide semiconductor layer can be made highly purified and electrically i-type (intrinsic).

In addition, by producing the excess oxygen region by the oxygen injection treatment, formation of oxygen vacancies in the amorphous oxide semiconductor layer or at the interface is suppressed, and the donor level in the energy gap resulting from the oxygen vacancies is reduced or substantially. I can eliminate it. Therefore, the transistor 510 is suppressed from fluctuation in electrical characteristics and is electrically stable. In addition, since the amorphous oxide semiconductor layer has an amorphous structure throughout, the uniformity of the film quality is higher than that of the oxide semiconductor layer in which only a part of the film is crystallized.

According to the present embodiment, a semiconductor device containing an amorphous oxide semiconductor having stable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

As mentioned above, the structure, method, etc. which are shown in this embodiment can be used in appropriate combination with the structure, method, etc. which are shown in another embodiment.

(Embodiment 2)

In this embodiment, a manufacturing method of the transistor 510 different from the first embodiment will be described with reference to FIGS. 4A to 4D. In addition, the part and process which have the same part or the same function as Embodiment 1 can be performed similarly to Embodiment 1, and the repeated description is abbreviate | omitted. In addition, detailed description of the same location is abbreviate | omitted.

First, an underlayer insulating layer 402 is formed on a substrate 400 having an insulating surface, and then an oxide semiconductor layer 401a is formed in contact with the underlayer insulating layer 402 (see FIG. 4A).

In the present embodiment, the oxide semiconductor layer 401a can be formed using the same material as the material shown in the first embodiment. In addition, the oxide semiconductor layer 401a may have an amorphous structure or may have a crystal region.

When forming the oxide semiconductor layer 401a by the sputtering method, it is preferable to reduce the hydrogen concentration contained in the oxide semiconductor layer 401a as much as possible. In order to reduce the hydrogen concentration, as an atmosphere gas supplied into the processing chamber of the sputtering apparatus, a high-purity rare gas (typically argon), oxygen, and a rare gas in which impurities such as hydrogen, water, a compound having a hydroxyl group, or a hydride are removed A mixed gas of oxygen is appropriately used.

In addition, forming the oxide semiconductor layer 401a while keeping the substrate 400 at a high temperature is also effective for reducing the impurity concentration that may be contained in the oxide semiconductor layer 401a. As temperature which heats the board | substrate 400, it is good to set it as 150 degreeC or more and 450 degrees C or less, Preferably, it is good to set board | substrate temperature to 200 degreeC or more and 350 degrees C or less. However, an oxide semiconductor layer having a crystal region is formed by heating the substrate at a high temperature during film formation.

In this embodiment, the oxide semiconductor layer 401a having a crystal region is formed at least in part by heating the substrate during film formation.

Next, the oxide semiconductor layer 401a formed into a film is subjected to heat treatment (first heat treatment) for the purpose of dehydration or dehydrogenation. In the present embodiment, the temperature of the first heat treatment is 250 ° C or more and 700 ° C or less, preferably 450 ° C or more and 600 ° C or less, or less than the strain point of the substrate. If the temperature of the first heat treatment is a high temperature (for example, a temperature higher than 400 ° C), it is preferable because desorption of impurities from the oxide semiconductor layer 401a is promoted. In addition, when the temperature of the first heat treatment is high, the oxide semiconductor layer 401a may be partially crystallized or the crystal region may be enlarged.

Subsequently, oxygen 421 is injected into the oxide semiconductor layer 401a. Injection of oxygen 421 can be performed as in the first embodiment. By the oxygen injection treatment, the crystal structure contained in the oxide semiconductor layer 401a is destroyed and amorphous, thereby forming an amorphous oxide semiconductor layer 404a having an excess oxygen region (see Fig. 4B).

By the injection processing of the oxygen 421, oxygen in the amorphous oxide semiconductor layer 404a which is simultaneously reduced by the heat treatment for the purpose of dehydration or dehydrogenation can be supplied. Thereby, the amorphous oxide semiconductor layer 404a can be made highly purified and electrically i-type (intrinsic). In addition, by forming the excess oxygen region in the amorphous oxide semiconductor layer 404a, the oxygen deficiency in the film can be compensated for. As a result, the charge trapping center in the amorphous oxide semiconductor layer 404a can be reduced.

In addition, in this embodiment, the example which injects oxygen 421 in the state which the surface of the oxide semiconductor layer 401a was exposed is shown. However, the embodiment of the present invention is not limited thereto, and oxygen may be injected into the amorphous oxide semiconductor layer 404 through the gate insulating layer 406 or the insulating layer 412.

Next, the amorphous oxide semiconductor layer 404a is processed into an island-shaped amorphous oxide semiconductor layer 404 by a photolithography process. On the amorphous oxide semiconductor layer 404, a conductive film serving as a source electrode and a drain electrode (including a wiring formed in the same layer as this) is formed and processed to form a source electrode 405a and a drain electrode 405b. do.

Subsequently, a gate insulating layer 406 is formed to cover the source electrode 405a and the drain electrode 405b and to contact a part of the amorphous oxide semiconductor layer 404 (see FIG. 4C).

Subsequently, a conductive film serving as a gate electrode (including a wiring formed in the same layer as this) is formed over the gate insulating layer 406, and is processed to form a gate electrode 410. Thereafter, an insulating layer 412 covering the gate electrode 410 is formed (see FIG. 4D).

After the formation of the insulating layer 412, heat treatment (second heat treatment) is performed. The temperature of the heat treatment is a temperature at which the amorphous oxide semiconductor layer 404 is not crystallized, preferably 250 ° C or more and 450 ° C or less.

Through the above steps, the transistor 510 is formed (see FIG. 4D). The transistor 510 is electrically stable because variations in electrical characteristics are suppressed.

According to the present embodiment, a semiconductor device containing an amorphous oxide semiconductor having stable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

As mentioned above, the structure, method, etc. which are shown in this embodiment can be used in appropriate combination with the structure, method, etc. which are shown in another embodiment.

(Embodiment 3)

In this embodiment, another embodiment of the semiconductor device and the manufacturing method of the semiconductor device will be described with reference to FIGS. 5A to 7D. In addition, the part and process which are the same part as the said embodiment, or the same function can be performed similarly to the said embodiment, and repeated description is abbreviate | omitted. In addition, detailed description of the same location is abbreviate | omitted.

5A to 5C show a cross-sectional view and a plan view of a bottom gate transistor 530 as an example of a semiconductor device. FIG. 5A is a plan view, and FIGS. 5B and 5C are cross-sectional views taken along the line I-J and the cross-section K-L in FIG. 5A. In addition, in FIG. 5A, some components (for example, the insulating layer 412, etc.) of the transistor 530 are omitted in order to avoid the trouble.

The transistor 530 illustrated in FIGS. 5A to 5C includes a gate electrode 410, a gate insulating layer 406, an amorphous oxide semiconductor layer 404, and a source electrode 405a on a substrate 400 having an insulating surface. And a drain electrode 405b and an insulating layer 412.

In the transistor 530 illustrated in FIGS. 5A to 5C, the amorphous oxide semiconductor layer 404 is subjected to an oxygen implantation process and has an oxygen excess region. By performing the oxygen injection process, the amorphous oxide semiconductor layer 404 can contain a sufficient amount of oxygen, so that the transistor 530 with high reliability is realized.

In the transistor 530 shown in Figs. 5A to 5C, the gate insulating layer 406, which is an insulating layer in contact with the amorphous oxide semiconductor layer 404, preferably has an excess oxygen region. If the gate insulating layer 406 has an excess oxygen region, it is possible to prevent the movement of oxygen from the amorphous oxide semiconductor layer 404 to the gate insulating layer 406, and further, from the gate insulating layer 406, to the amorphous oxide. This is because oxygen can be supplied to the semiconductor layer 404.

Similarly, the insulating layer 412 preferably has a laminate structure of an oxide insulating film, such as a silicon oxide film or a silicon oxynitride film, which is in contact with the amorphous oxide semiconductor layer 404 and has an excess oxygen region, and an aluminum oxide film. Do. Since the oxide insulating film has an excess oxygen region, it is possible to compensate for the oxygen deficiency of the amorphous oxide semiconductor layer 404 by the excess oxygen contained in the oxide insulating film.

6A to 6C show another configuration example of the transistor according to the present embodiment. 6A is a plan view of the transistor 540, and FIGS. 6B and 6C are cross-sectional views taken along the M-N cross section and the O-P cross section in FIG. 6A. In addition, in FIG. 6A, some components (for example, the insulating layer 412 and the like) of the transistor 540 are omitted in order to avoid the trouble.

The transistor 540 shown in Figs. 6A to 6C is, like the transistor 530 shown in Figs. 5A to 5C, the gate electrode 410 and the gate insulating layer 406 on the substrate 400 having an insulating surface. ), An amorphous oxide semiconductor layer 404, a source electrode 405a, a drain electrode 405b, and an insulating layer 412.

The difference between the transistor 540 shown in FIGS. 6A to 6C and the transistor 530 shown in FIGS. 5A to 5C differs between the source electrode 405a and the drain electrode 405b and the amorphous oxide semiconductor layer 404. Lamination order. That is, the transistor 540 is formed on the source electrode 405a and the drain electrode 405b in contact with the gate insulating layer 406, and on the source electrode 405a and the drain electrode 405b, and the gate insulating layer 406 is provided. At least partially in contact with the amorphous oxide semiconductor layer 404. Other configurations are the same as those of the transistor 530, and for details, the description of the transistor 530 can be referred to.

7A to 7D show an example of the manufacturing method of the transistor 530. The transistor 540 can be manufactured by the same process as the transistor 530 except for the stacking order of the source electrode 405a and the drain electrode 405b and the amorphous oxide semiconductor layer 404.

First, after forming a conductive film on the substrate 400 having an insulating surface, the gate electrode 410 is formed by a photolithography process.

Moreover, you may form the insulating layer used as a base film between the board | substrate 400 and the gate electrode 410. The underlying film has a function of preventing diffusion of impurity elements from the substrate 400, and has a laminated structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film. It can form by.

Subsequently, a gate insulating layer 406 is formed over the gate electrode 410, and an amorphous oxide semiconductor layer 404a having a film thickness of 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less is formed on the gate insulating layer 406. (See FIG. 7A). The film formation of the amorphous oxide semiconductor layer 404a can be performed in the same manner as shown in FIG. 3A.

In addition, the gate insulating layer 406 and the amorphous oxide semiconductor layer 404a are preferably formed continuously without being released into the atmosphere. For example, after the impurities containing hydrogen adhered to the surface of the substrate 400 and the surface of the gate electrode 410 are removed by heat treatment or plasma treatment, the gate insulating layer 406 is formed without being released into the atmosphere. Thus, the amorphous oxide semiconductor layer 404a may be formed without releasing to the atmosphere. By doing in this way, the impurity containing hydrogen adhered on the surface of the gate insulating layer 406 is reduced, and also the interface of the board | substrate 400 or the gate electrode 410 and the gate insulating layer 406, and gate insulation The adhesion of the atmospheric component to the interface between the layer 406 and the amorphous oxide semiconductor layer 404a can be suppressed. As a result, the transistor 530 with good electrical characteristics and high reliability can be manufactured. Similarly, in the case of forming the insulating layer serving as the underlayer, the insulating layer, the gate insulating layer 406 and the amorphous oxide semiconductor layer 404a are preferably formed continuously without being released into the atmosphere.

Next, heat treatment (first heat treatment) for removing (dehydrating or dehydrogenating) hydrogen (containing water or hydroxyl groups) is performed on the amorphous oxide semiconductor layer 404a. The temperature of the heat treatment is a temperature at which the amorphous oxide semiconductor layer 404a is not crystallized, and is typically 250 ° C or more and 450 ° C or less, preferably 300 ° C or less.

Subsequently, oxygen 421 is injected into the amorphous oxide semiconductor layer 404a (see FIG. 7B). Injection of oxygen 421 can be performed as in the first embodiment. In addition, in this embodiment, since the oxygen 421 is injected in a state where the surface of the amorphous oxide semiconductor layer 404a is exposed, the atmosphere in which the oxygen 421 is converted into a plasma instead of the above injection method. The plasma treatment which exposes the amorphous oxide semiconductor layer 404a may be applied. Or you may use it in combination.

By the injection processing of the oxygen 421, oxygen in the amorphous oxide semiconductor layer 404a which is simultaneously reduced by the heat treatment for the purpose of dehydration or dehydrogenation can be supplied. Thereby, the amorphous oxide semiconductor layer 404a can be made highly purified and electrically i-type (intrinsic). In addition, by forming an excess oxygen region in the amorphous oxide semiconductor layer 404a, the oxygen deficiency can be compensated for. As a result, the charge trapping center in the amorphous oxide semiconductor layer 404a can be reduced.

In addition, in this embodiment, the example which injects oxygen 421 in the state which the surface of the amorphous oxide semiconductor layer 404a was exposed is shown. However, the embodiment of the present invention is not limited thereto, and oxygen can be injected into the amorphous oxide semiconductor layer 404 through the insulating layer 412.

Next, the amorphous oxide semiconductor layer 404a is processed into an island-shaped amorphous oxide semiconductor layer 404 by a photolithography process. Thereafter, a conductive film serving as a source electrode and a drain electrode (including a wiring formed in the same layer as this) is formed over the amorphous oxide semiconductor layer 404 and processed to form the source electrode 405a and the drain electrode 405b. ) (See FIG. 7C).

Next, an insulating layer 412 covering the source electrode 405a and the drain electrode 405b is formed (see FIG. 7D).

After the formation of the insulating layer 412, heat treatment (second heat treatment) is performed. The temperature of the heat treatment is a temperature at which the amorphous oxide semiconductor layer 404 is not crystallized, preferably 250 ° C or more and 450 ° C or less.

The transistor 530 is formed by the above process (refer FIG. 7D). The transistor 530 is electrically stable because variations in electrical characteristics are suppressed.

According to the present embodiment, a semiconductor device containing an amorphous oxide semiconductor having stable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

As mentioned above, the structure, method, etc. which are shown in this embodiment can be used in appropriate combination with the structure, method, etc. which are shown in another embodiment.

(Fourth Embodiment)

In this embodiment, a manufacturing method of the transistor 530 different from the third embodiment will be described with reference to FIGS. 8A to 8D. In addition, the part and process which are the same part as the said embodiment, or the same function can be performed similarly to the said embodiment, and repeated description is abbreviate | omitted. In addition, detailed description of the same location is abbreviate | omitted.

First, after forming a conductive film on the substrate 400 having an insulating surface, the gate electrode 410 is formed by a photolithography process. Subsequently, a gate insulating layer 406 is formed on the gate electrode 410, and an oxide semiconductor layer 401a having a film thickness of 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less is formed on the gate insulating layer 406. (See FIG. 8A). The film formation of the oxide semiconductor layer 401a can be performed in the same manner as shown in FIG. 4A. The oxide semiconductor layer 401a may have an amorphous structure or may have a crystal region.

In this embodiment, the oxide semiconductor layer 401a having a crystal region is formed at least in part by heating the substrate during film formation.

Next, the oxide semiconductor layer 401a formed into a film is subjected to heat treatment (first heat treatment) for the purpose of dehydration or dehydrogenation. In the present embodiment, the temperature of the first heat treatment is 250 ° C or more and 700 ° C or less, preferably 450 ° C or more and 600 ° C or less, or less than the strain point of the substrate. If the temperature of the first heat treatment is a high temperature (for example, a temperature higher than 400 ° C), it is preferable because desorption of impurities from the oxide semiconductor layer 401a is promoted. In addition, when the temperature of the first heat treatment is high, the oxide semiconductor layer 401a may be partially crystallized or the crystal region may be enlarged.

Next, the oxide semiconductor layer 401a is processed into an island-shaped oxide semiconductor layer 401 by a photolithography process. Thereafter, a conductive film serving as a source electrode and a drain electrode (including a wiring formed in the same layer as this) is formed over the oxide semiconductor layer 401, and processed to form the source electrode 405a and the drain electrode 405b. To form.

Next, an insulating layer 412 is formed to cover the source electrode 405a and the drain electrode 405b and to contact a part of the oxide semiconductor layer 401 (see FIG. 8B).

Next, oxygen 421 is injected into the oxide semiconductor layer 401 through the insulating layer 412 (see FIG. 8C). By the oxygen implantation process, the crystal structure contained in the oxide semiconductor layer 401 is destroyed and amorphous, and an amorphous oxide semiconductor layer 404 having an excess oxygen region is formed.

By the injection processing of oxygen 421, oxygen in the amorphous oxide semiconductor layer 404 which is simultaneously reduced by heat treatment for the purpose of dehydration or dehydrogenation can be supplied. Thereby, the amorphous oxide semiconductor layer 404 can be highly purified and electrically i-type (intrinsic). In addition, by forming the excess oxygen region in the amorphous oxide semiconductor layer 404, the oxygen deficiency in the film can be compensated. As a result, the charge trapping center in the amorphous oxide semiconductor layer 404 can be reduced.

After the oxygen 421 is injected, heat treatment (second heat treatment) is performed. The temperature of the heat treatment is a temperature at which the amorphous oxide semiconductor layer 404 is not crystallized, preferably 250 ° C or more and 450 ° C or less.

The transistor 530 is formed by the above process (refer FIG. 8D). The transistor 530 is electrically stable because variations in electrical characteristics are suppressed.

According to the present embodiment, a semiconductor device containing an amorphous oxide semiconductor having stable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

As mentioned above, the structure, method, etc. which are shown in this embodiment can be used in appropriate combination with the structure, method, etc. which are shown in another embodiment.

(Embodiment 5)

A semiconductor device (also called a display device) having a display function can be fabricated using the transistors exemplified in the first to fourth embodiments. In addition, part or all of the driving circuit including the transistor may be integrally formed on the same substrate as the pixel portion to form a system on panel.

In FIG. 9A, a seal member 4005 is formed to surround the pixel portion 4002 formed on the first substrate 4001, and is sealed by the second substrate 4006. In FIG. 9A, a scan line driver circuit 4004 and a signal line drive formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate in a region different from the region surrounded by the seal member 4005 on the first substrate 4001. The circuit 4003 is mounted. In addition, various signals and potentials supplied to the pixel portion 4002 through the signal line driver circuit 4003 and the scan line driver circuit 4004 are supplied from the FPC (Flexible printed circuit) 4018a and 4018b.

9B and 9C, a seal member 4005 is formed so as to surround the pixel portion 4002 formed on the first substrate 4001 and the scanning line driver circuit 4004. A second substrate 4006 is formed over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with the display element by the first substrate 4001, the seal member 4005, and the second substrate 4006. 9B and 9C, a signal line driver circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate in a region different from the region surrounded by the seal member 4005 on the first substrate 4001. Is mounted. 9B and 9C, various signals and potentials supplied to the pixel portion 4002 through the signal line driver circuit 4003 and the scan line driver circuit 4004 are supplied from the FPC 4018.

In addition, although the signal line drive circuit 4003 is formed separately and is mounted in the 1st board | substrate 4001 in FIG. 9B and 9C, it is not limited to this structure. The scan line driver circuit may be separately formed and mounted, or only a part of the signal line driver circuit or a part of the scan line driver circuit may be separately formed and mounted.

In addition, the connection method of the separately formed drive circuit is not specifically limited, A COG (Chip On Glass) method, a wire bonding method, the Tape Automated Bonding (TAB) method, etc. can be used. 9A is an example in which the signal line driver circuit 4003 and the scan line driver circuit 4004 are mounted by the COG method. FIG. 9B is an example in which the signal line driver circuit 4003 is mounted by the COG method. Is an example of mounting the signal line driver circuit 4003 by the TAB method.

The display device also includes a panel in which the display element is sealed, and a module in a state in which an IC including a controller is mounted on the panel.

In other words, the display device in this specification refers to an image display device, a display device, or a light source (including an illumination device). In addition to the panel in which the display element is encapsulated, a connector, for example, a module equipped with FPC or TAB tape or TCP, a module having a printed wiring board formed at the end of the TAB tape or TCP, or a display element by a COG method All modules in which ICs (integrated circuits) are mounted directly are also included in the display device.

The pixel portion and the scan line driver circuit formed on the first substrate have a plurality of transistors, and the transistors exemplified in the first to fourth embodiments can be applied.

As a display element formed in a display apparatus, a liquid crystal element (also called liquid crystal display element) and a light emitting element (also called light emitting display element) can be used. The light emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, and the like. In addition, a display medium whose contrast is changed by an electrical action, such as an electronic ink display device (electronic paper), can also be applied.

One embodiment of the semiconductor device will be described with reference to FIGS. 10 to 12. 10-12 correspond to sectional drawing in Q-R of FIG. 9B.

As shown in FIGS. 10 to 12, the semiconductor device has a connecting terminal electrode 4015 and a terminal electrode 4016, and the connecting terminal electrode 4015 and the terminal electrode 4016 are terminals included in the FPC 4018. And anisotropic conductive film 4019 are electrically connected to each other.

The connection terminal electrode 4015 is formed of the same conductive film as the first electrode 4030, and the terminal electrode 4016 is formed of the same conductive film as the source and drain electrodes of the transistors 4010 and 4011.

The pixel portion 4002 and the scanning line driver circuit 4004 formed on the first substrate 4001 have a plurality of transistors. In FIGS. 10 to 12, the transistor 4010 included in the pixel portion 4002 and The transistor 4011 included in the scan line driver circuit 4004 is illustrated. 10 to 12, an insulating layer 4020 and an insulating layer 4024 are formed over the transistors 4010 and 4011, and an insulating layer 4021 is formed in FIGS. 11 and 12. In addition, the insulating layer 4023 in FIGS. 10-12 is an insulating layer which functions as an underlayer.

As the transistors 4010 and 4011, the transistors described in Embodiments 1 through 4 can be used.

The transistor 4010 and the transistor 4011 are transistors which are highly purified and have an amorphous oxide semiconductor layer including an excess oxygen region. Therefore, the transistor 4010 and the transistor 4011 are electrically stable because electrical characteristic variations are suppressed.

Therefore, a highly reliable semiconductor device can be provided as the semiconductor device of this embodiment shown in FIGS. 10 to 12.

In addition, in this embodiment, the conductive layer 4037 is formed in the position which overlaps with the channel formation area of the amorphous oxide semiconductor layer of the transistor 4011 for drive circuits on an insulating layer. As a result, the amount of change in the threshold voltage of the transistor 4011 can be further reduced. The conductive layer 4037 may have the same or different potential as the gate electrode 4039 of the transistor 4011, and may function as a second gate electrode. In addition, the potential of the conductive layer 4037 may be GND, 0V, or a floating state.

The conductive layer 4037 also has a function of shielding the external electric field, that is, preventing the external electric field from acting on the inside (circuit portion including the thin film transistor) (especially an electrostatic shielding function against static electricity). By the shielding function of the conductive layer 4037, it is possible to prevent the electrical characteristics of the transistor 4011 from changing due to an external electric field such as static electricity.

The transistor 4010 formed in the pixel portion 4002 is electrically connected to the display element to form a display panel. The display element is not particularly limited as long as it can display, and various display elements can be used.

The example of the liquid crystal display device using a liquid crystal element as a display element in FIG. 10 is shown. In FIG. 10, the liquid crystal element 4013 includes a first electrode 4030, a second electrode 4031, and a liquid crystal layer 4008. An insulating layer 4032 and an insulating layer 4033 functioning as an alignment film are formed so as to sandwich the liquid crystal layer 4008 therebetween. The second electrode 4031 is formed on the second substrate 4006 side, and the first electrode 4030 and the second electrode 4031 are laminated with the liquid crystal layer 4008 interposed therebetween.

4035 is a columnar spacer obtained by selectively etching the insulating layer, and is formed to control the film thickness (cell gap) of the liquid crystal layer 4008. In addition, spherical spacers may be used.

As a display element, when using a liquid crystal element, a thermotropic liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. These liquid crystals may be low molecular weight compounds or high molecular weight compounds. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. according to conditions.

Moreover, you may use the liquid crystal which shows the blue phase which does not use an oriented film. The blue phase is one of the liquid crystal phases, and when the cholesteric liquid crystal is heated, the blue phase is a phase which is expressed immediately before transition from the cholesteric phase to the isotropic phase. Since a blue phase is expressed only in a narrow temperature range, in order to improve a temperature range, it uses for the liquid crystal layer using the liquid crystal composition which mixed several weight% or more of chiral agents. Since the liquid crystal composition containing the liquid crystal and blue chiral agent which show a blue phase is short in response speed, and since it is optically isotropic, an orientation process is unnecessary and a viewing angle dependency is small. In addition, since the alignment film is not required and the rubbing process is unnecessary, electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, the productivity of the liquid crystal display device can be improved.

The resistivity of the liquid crystal material is 1 × 10 ⁹ Ω · cm or more, preferably 1 × 10 ¹¹ Ω · cm or more, and more preferably 1 × 10 ¹² Ω · cm or more. The value of the intrinsic resistance in this specification is a value measured at 20 占 폚.

The size of the storage capacitor formed in the liquid crystal display device is set so that the charge can be held for a predetermined period in consideration of the leak current of the transistor disposed in the pixel portion 4002. The size of the holding capacitor may be set in consideration of the off current of the transistor and the like. By using a transistor having an amorphous oxide semiconductor layer having a high purity and an excess oxygen region, if a storage capacitor having a size of 1/3 or less, preferably 1/5 or less of the liquid crystal capacitance in each pixel is formed, Suffice.

The transistor having a high purity and amorphous oxide semiconductor layer which suppresses the formation of oxygen vacancies used in the present embodiment can have a low current value (off current value) in an off state. Therefore, the holding time of an electrical signal such as an image signal can be lengthened, and the recording interval can also be set long. Therefore, since the frequency of the refresh operation can be reduced, the power consumption can be suppressed.

In addition, the transistor having the amorphous oxide semiconductor layer which is highly purified and suppresses the formation of oxygen vacancies used in the present embodiment can be driven at a high speed since a relatively high field effect mobility can be obtained. For example, by using such a transistor in a liquid crystal display device, a switching transistor of a pixel portion and a driver transistor used for a driving circuit portion can be formed on the same substrate. Also in the pixel portion, by using such a transistor, a high quality image can be provided.

Liquid crystal display devices include twisted nematic (TN) mode, in-plane-switching (IPS) mode, freted field switching (FSF) mode, symmetrically aligned micro-cell (ASM) mode, optically compensated birefringence (OCB) mode, and FLC. (Ferroelectric Liquid Crystal) mode, AFLC (Anti Ferroelectric Liquid Crystal) mode, and the like can be used.

Moreover, it is good also as a transmission type liquid crystal display device which employ | adopted a normally black liquid crystal display device, for example, a vertical alignment (VA) mode. Some examples of the vertical alignment mode include, but are not limited to, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an ASV mode, and the like. The present invention can also be applied to VA type liquid crystal display devices. VA type liquid crystal display device is a kind of system which controls the arrangement | sequence of the liquid crystal molecule of a liquid crystal display panel. The VA type liquid crystal display device is a system in which liquid crystal molecules are directed perpendicular to the panel surface when no voltage is applied. In addition, a method called multi-domainization or multi-domain design, which is designed to divide a pixel (pixel) into several regions (sub pixels) and to knock down molecules in different directions, can be used.

In the display device, an optical member (optical substrate) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, an antireflection member, or the like is suitably formed. For example, circularly polarized light by a polarizing substrate and a retardation substrate may be used. Moreover, you may use a backlight, a side light, etc. as a light source.

As the display method in the pixel portion, a progressive method, an interlace method, or the like can be used. In addition, as a color element controlled by a pixel at the time of color display, it is not limited to three colors of RGB (R is red, G is green, B is blue). For example, RGBW (W represents white) or RGB, yellow, cyan, magenta, etc., have added one or more colors. In addition, the size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to the display device of the color display, and can also be applied to the display device of the monoclonal display.

In addition, as a display element included in the display device, a light emitting element using an electroluminescence can be applied. The light emitting element using the electroluminescence is distinguished by whether the light emitting material is an organic compound or an inorganic compound. In general, the former is called an organic EL element, and the latter is called an inorganic EL element.

By applying a voltage to the light emitting element, the organic EL element is injected with electrons and holes from the pair of electrodes into the layer containing the light emitting organic compound, respectively, and a current flows. And by recombination of these carriers (electrons and holes), the luminescent organic compound forms an excited state and emits light when the excited state returns to the ground state. From this mechanism, such a light emitting element is called a current excitation type light emitting element.

An inorganic EL element is classified into a distributed inorganic EL element and a thin-film inorganic EL element by the element structure. A dispersed inorganic EL device has a light emitting layer in which particles of a light emitting material are dispersed in a binder, and a light emitting mechanism is donor acceptor recombination type light emission using a donor level and an acceptor level. The thin-film inorganic EL device has a structure in which a light emitting layer is interposed between dielectric layers and between the electrodes, and the light emitting mechanism is localized light emission using a cabinet electron transition of metal ions. In addition, it demonstrates using an organic electroluminescent element as a light emitting element here.

In the light emitting element, at least one of the pair of electrodes may be translucent to extract light emission. Then, a transistor and a light emitting element are formed on the substrate, and the upper surface ejection extracts light emission from the surface on the opposite side of the substrate, the lower surface ejection extracts light emission from the surface on the substrate side, or from the surface on the side opposite to the substrate and the substrate. There is a light emitting device having a double-sided injection structure that extracts light emission, and any light emitting device having an injection structure can be applied.

11 shows an example of a light emitting device using a light emitting element as a display element. The light emitting element 4513 is electrically connected to the transistor 4010 formed in the pixel portion 4002. In addition, although the structure of the light emitting element 4513 shown in FIG. 11 is a laminated structure of the 1st electrode 4030, the electroluminescent layer 4511, and the 2nd electrode 4031, it is not limited to the structure shown in figure. The configuration of the light emitting element 4513 can be appropriately changed in accordance with the direction of the light extracted from the light emitting element 4513 and the like.

The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable that an opening is formed on the first electrode 4030 using a photosensitive resin material, and the sidewall of the opening is formed to be an inclined surface formed with a continuous curvature.

The electroluminescent layer 4511 may be composed of a single layer or a plurality of layers may be laminated.

A protective film may be formed over the second electrode 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, and the like do not enter the light emitting element 4513. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed. In addition, a filler 4414 is formed and sealed in a space sealed by the first substrate 4001, the second substrate 4006, and the seal member 4005. It is preferable to package (encapsulate) with a protective film (bonding film, an ultraviolet curable resin film, etc.) and a cover material with high airtightness and few degassing so that it may not be exposed to external air in this way.

As the filler 4514, an ultraviolet curable resin or a thermosetting resin can be used in addition to an inert gas such as nitrogen or argon, and PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB (polyvinyl buty) LAL) or EVA (ethylene vinyl acetate copolymer) can be used.

If necessary, optical films such as polarizing plates or circular polarizing plates (including elliptical polarizing plates), retardation plates (λ / 4 plate and λ / 2 plates) and color filters may be appropriately formed on the emitting surface of the light emitting element. In addition, an antireflection film may be formed on the polarizing plate or the circularly polarizing plate. For example, antiglare treatment can be applied to diffuse the reflected light by the unevenness of the surface and to reduce the glare.

It is also possible to provide an electronic paper for driving electronic ink as a display device. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has the advantage of being easy to read as paper, low power consumption, and a thin and light shape compared to other display devices.

The electrophoretic display device can be considered in various forms, but a plurality of microcapsules containing a first particle having a positive charge and a second particle having a negative charge are dispersed in a solvent, and an electric field is applied to the microcapsule. By applying, the particles in the microcapsules are moved in opposite directions to display only the color of the particles collected on one side. In addition, 1st particle | grains or 2nd particle | grains contain dye and do not move when there is no electric field. In addition, the color of a 1st particle | grain and the color of a 2nd particle | grain shall be different (including colorlessness).

Dispersion of the microcapsules in a solvent is called an electronic ink. Color display is also possible by using the particle | grains which have a color filter or a pigment | dye.

Moreover, the display apparatus which uses the twist ball display system as an electronic paper is also applicable. The twisted ball display method is arranged between a first electrode and a second electrode, which is an electrode used for a display element, and arranges spherical particles, which are colored in white and black, and generates a potential difference between the first electrode and the second electrode to produce spherical particles. It is a method of displaying by controlling a direction.

12 shows an active matrix electronic paper as one form of a semiconductor device. The electronic paper in FIG. 12 is an example of a display device using a twist ball display system.

It has a black region 4615a and a white region 4615b between the first electrode 4030 connected to the transistor 4010 and the second electrode 4031 formed on the second substrate 4006, and is filled with a liquid around it. A spherical particle 4613 including a cavity 4612 is formed, and the periphery of the spherical particle 4613 is filled with a filler 4614 such as resin. The second electrode 4031 corresponds to a common electrode (counter electrode). The second electrode 4031 is electrically connected to the common potential line.

In addition, in FIG. 10-12, as a 1st board | substrate 4001 and the 2nd board | substrate 4006, the board | substrate which has flexibility can also be used, For example, the plastic substrate etc. which have transparency are used. Can be. As the plastic, a fiberglass-reinforced plastics (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film or an acrylic resin film can be used. Moreover, the sheet | seat of the structure which interposed aluminum foil between PVF film or a polyester film can also be used.

In this embodiment, a silicon oxide film is used as the insulating layer 4020, and an aluminum oxide film is used as the insulating layer 4024. The insulating layer 4020 and the insulating layer 4024 can be formed by sputtering or plasma CVD. It is preferable that the insulating layer 4020 in contact with the amorphous oxide semiconductor layer has an excess oxygen region.

The aluminum oxide film formed as the insulating layer 4024 on the amorphous oxide semiconductor layer has a high blocking effect (block effect) that does not transmit the film to both impurities such as hydrogen and moisture and oxygen.

Therefore, the aluminum oxide film functions as a protective film to prevent the incorporation of impurities such as hydrogen and moisture, which become fluctuating factors, into the amorphous oxide semiconductor layer and the release of oxygen from the amorphous oxide semiconductor layer during and after the fabrication process. .

The transistor 4010 and the transistor 4011 have an excess oxygen region, thereby suppressing the formation of oxygen vacancies and having a highly purified amorphous oxide semiconductor layer. In addition, the transistor 4010 and the transistor 4011 have a silicon oxide film as a gate insulating layer. The amorphous oxide semiconductor layer included in the transistor 4010 and the transistor 4011 forms a region having an excess of oxygen rather than the stoichiometric composition ratio by the oxygen injection treatment, and insulates the heat treatment after the injection on the amorphous oxide semiconductor layer. Since it is performed in the state in which the film containing an aluminum oxide film or an aluminum oxide film was formed as the layer 4024, oxygen release from an amorphous oxide semiconductor layer can be prevented by the said heat processing. Therefore, the amorphous oxide semiconductor layer obtained can be made into the film containing the area | region which has excessive content of oxygen rather than stoichiometric composition ratio.

The amorphous oxide semiconductor layer included in the transistor 4010 and the transistor 4011 is a high purity film dehydrated or dehydrogenated and supplemented with oxygen vacancies. Therefore, by using the amorphous oxide semiconductor layer in the transistor 4010 and the transistor 4011, the variation in the threshold voltage V _th of the transistor due to oxygen deficiency can be reduced and the shift in the threshold voltage can be suppressed. have.

As the insulating layer 4021 serving as the planarization insulating layer, an organic material having heat resistance such as acrylic resin, polyimide, benzocyclobutene resin, polyamide, epoxy resin and the like can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) such as siloxane resins, PSG (phosphorus glass), BPSG (phosphorous boron glass) and the like can be used. In addition, the insulating layer 4021 may be formed by laminating a plurality of insulating layers formed of these materials.

The formation method of the insulating layer 4021 is not specifically limited, According to the material, sputtering method, SOG method, spin coat, dip, spray application | coating, droplet ejection method (inkjet method etc.), screen printing, offset printing, etc. can be used. Can be.

The first electrode 4030 and the second electrode 4031 may be, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, or indium tin containing titanium oxide. Conductive materials having light transmissivity, such as oxide, ITO, indium zinc oxide, indium tin oxide added with silicon oxide, and graphene, can be used.

The first electrode 4030 and the second electrode 4031 may include tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), and tantalum (Ta). , Metals such as chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or alloys thereof, or It can form using one or more types from metal nitride.

The first electrode 4030 and the second electrode 4031 can be formed using a conductive composition containing a conductive polymer (also called a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, the polyaniline or its derivative (s), polypyrrole or its derivative (s), polythiophene or its derivative (s), or the copolymer which consists of two or more types of aniline, pyrrole and thiophene, or its derivative (s), etc. are mentioned.

Moreover, you may provide the protection circuit for protection of a drive circuit. It is preferable to comprise a protection circuit using a nonlinear element.

By applying the transistors shown in Embodiments 1 to 4 as described above, a semiconductor device having various functions can be provided.

(Embodiment 6)

By using the transistors exemplified in the first to fourth embodiments, a semiconductor device having an image sensor function for reading information of an object can be manufactured.

13A shows an example of a semiconductor device having an image sensor function. FIG. 13A is an equivalent circuit of the photosensor, and FIG. 13B is a sectional view showing a part of the photosensor.

In the photodiode 602, one electrode is electrically connected to the photodiode reset signal line 658, and the other electrode is electrically connected to the gate of the transistor 640. In the transistor 640, one of the source or the drain is electrically connected to the photosensor reference signal line 672, and the other of the source or the drain is electrically connected to one of the source or the drain of the transistor 656. The transistor 656 has a gate electrically connected to the gate signal line 659 and the other of the source or the drain to the photosensor output signal line 671.

In addition, in the circuit diagram in this specification, in order to make it clear from the transistor containing an amorphous oxide semiconductor layer, the symbol of the transistor using an amorphous oxide semiconductor layer is described as "OS". In Fig. 13A, the transistors 640 and 656 are transistors containing an amorphous oxide semiconductor layer in which an excess oxygen region is formed by the oxygen injection process shown in the transistors in the first to fourth embodiments.

FIG. 13B is a cross-sectional view showing the photodiode 602 and the transistor 640 in the photosensor, and the photodiode 602 and the transistor functioning as a sensor on a substrate 601 (TFT substrate) having an insulating surface. 640 is formed. The substrate 613 is formed on the photodiode 602 and the transistor 640 by using an adhesive layer 608.

An insulating layer 631, an insulating layer 632, an interlayer insulating film 633, and an interlayer insulating film 634 are formed on the transistor 640. The photodiode 602 is formed on the interlayer insulating film 633, and between the electrodes 641a and 641b formed on the interlayer insulating film 633, and the electrode 642 formed on the interlayer insulating film 634. The first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c are sequentially stacked from the 633 side.

The electrode 641b is electrically connected to the conductive layer 643 formed on the interlayer insulating film 634, and the electrode 642 is electrically connected to the electrode 645 via the electrode 641a. The electrode 645 is electrically connected to the gate electrode of the transistor 640, and the photodiode 602 is electrically connected to the transistor 640.

Here, a semiconductor film having a p-type conductivity type as the first semiconductor film 606a, and a high resistance semiconductor film (i-type semiconductor film) and the third semiconductor film 606c as the second semiconductor film 606b. The pin type photodiode which laminate | stacks the semiconductor film which has n type conductivity type is illustrated.

The first semiconductor film 606a is a p-type semiconductor film and can be formed of an amorphous silicon film containing an impurity element imparting a p-type. The first semiconductor film 606a is formed by a plasma CVD method using a semiconductor material gas containing a group 13 impurity element (for example, boron (B)). As the semiconductor material gas, silane (SiH ₄ ) may be used. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like may be used. After the amorphous silicon film containing no impurity element is formed, the impurity element may be introduced into the amorphous silicon film by using a diffusion method or an ion implantation method. The impurity element may be diffused by introducing the impurity element by ion implantation or the like, followed by heating. In this case, as the method of forming the amorphous silicon film, an LPCVD method, a vapor phase growth method, a sputtering method, or the like may be used. It is preferable to form the film thickness of the 1st semiconductor film 606a so that it may become 10 nm or more and 50 nm or less.

The second semiconductor film 606b is an i-type semiconductor film (intrinsic semiconductor film), and is formed of an amorphous silicon film. In forming the second semiconductor film 606b, an amorphous silicon film is formed by a plasma CVD method using a semiconductor material gas. As the semiconductor material gas, silane (SiH ₄ ) may be used. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like may be used. The second semiconductor film 606b may be formed by the LPCVD method, the vapor phase growth method, the sputtering method, or the like. The film thickness of the second semiconductor film 606b is preferably formed to be 200 nm or more and 1000 nm or less.

The third semiconductor film 606c is an n-type semiconductor film, and is formed of an amorphous silicon film containing an impurity element imparting n-type. For forming the third semiconductor film 606c, a semiconductor material gas containing a group 15 impurity element (for example, phosphorus (P)) is used by plasma CVD. As the semiconductor material gas, silane (SiH ₄ ) may be used. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like may be used. After the amorphous silicon film containing no impurity element is formed, the impurity element may be introduced into the amorphous silicon film by using a diffusion method or an ion implantation method. The impurity element may be diffused by introducing the impurity element by ion implantation or the like, followed by heating. In this case, as the method of forming the amorphous silicon film, an LPCVD method, a vapor phase growth method, a sputtering method, or the like may be used. The film thickness of the third semiconductor film 606c is preferably formed to be 20 nm or more and 200 nm or less.

Note that the first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c are not amorphous semiconductors, and may be formed using polycrystalline semiconductors, and may be microcrystalline (semi-amorphous semiconductors). Semiconductor: SAS)) may be used.

Microcrystalline semiconductors belong to an intermediate metastable state between amorphous and single crystals in consideration of the free energy of the cast. That is, a semiconductor having a thermodynamically stable third state, which has short-range order and lattice strain. Columnar or acicular crystals are growing in the normal direction with respect to the substrate surface. The microcrystalline silicon, which is a representative example of the microcrystalline semiconductor, is shifted to the lower wave side than the 520 cm ^-1 where the Raman spectrum represents single crystal silicon. In other words, the peak of the Raman spectrum of the microcrystalline silicon between 480cm ^-1 to 520cm ^-1 showing an amorphous silicon indicates a single crystalline silicon. Moreover, in order to terminate unbound water (dangling bond), hydrogen or a halogen is contained at least 1 atomic% or more. Further, by containing rare gas elements such as helium, argon, krypton, and neon to further promote lattice deformation, stability is increased and a good microcrystalline semiconductor film is obtained.

The microcrystalline semiconductor film can be formed by a high frequency plasma CVD method having a frequency of several tens of MHz to several hundred MHz or a microwave plasma CVD apparatus having a frequency of 1 GHz or more. Typically, silicon hydrides such as SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , and SiHCl ₃ can be formed by diluting with hydrogen. In addition to hydrogen, silicon hydride may be diluted with one or more rare gas elements selected from helium, argon, krypton, and neon to form a microcrystalline semiconductor film. The flow rate ratio of hydrogen to silicon hydride at this time is 5 times or more and 200 times or less, preferably 50 times or more and 150 times or less, and more preferably 100 times. Further, in the gas containing silicon, CH _4, C ₂ H _6, such as a hydrocarbon gas, GeH _4, GeF ₄ may be such as even the incorporation of germanium screen gas, such as F _2.

In addition, since the mobility of the holes generated in the photoelectric effect is smaller than the mobility of the electrons, the pin-type photodiode has a better characteristic of making the p-type semiconductor film side the light-receiving surface. Here, the example which converts the light which the photodiode 602 receives from the surface of the board | substrate 601 in which the pin type photodiode is formed into an electrical signal is shown. In addition, since the light from the semiconductor film side having a conductivity type opposite to the semiconductor film side serving as the light receiving surface becomes disturbing light, the electrode may be a conductive film having light shielding properties. The n-type semiconductor film side can also be used as the light receiving surface.

As the insulating layer 632, the interlayer insulating film 633, and the interlayer insulating film 634, an insulating material is used, and depending on the material, the sputtering method, the plasma CVD method, the SOG method, the spin coat, the dip, the spray coating, and the droplet ejection It can form using a method (inkjet method etc.), screen printing, offset printing, etc.

In this embodiment, an aluminum oxide film is used as the insulating layer 631. The insulating layer 631 can be formed by sputtering or plasma CVD.

The aluminum oxide film formed as the insulating layer 631 on the amorphous oxide semiconductor layer has a high blocking effect (block effect) that does not transmit the film to both impurities such as hydrogen and moisture and oxygen.

Therefore, the aluminum oxide film functions as a protective film to prevent the incorporation of impurities such as hydrogen and moisture, which become fluctuating factors, into the amorphous oxide semiconductor layer and the release of oxygen from the amorphous oxide semiconductor layer during and after the fabrication process. .

In the present embodiment, the transistor 640 has an oxygen excess region to suppress the formation of oxygen vacancies and to have a highly purified amorphous oxide semiconductor layer. In addition, the transistor 640 has a silicon oxide film as a gate insulating layer. The amorphous oxide semiconductor layer included in the transistor 640 forms a region having an excess of oxygen rather than the stoichiometric composition ratio by the oxygen injection treatment, and the heat treatment after the injection is performed as the insulating layer 631 on the amorphous oxide semiconductor layer. Since it is performed in the state in which the aluminum oxide film was formed, it can prevent that oxygen is discharge | released from an amorphous oxide semiconductor layer by the said heat processing. Therefore, the amorphous oxide semiconductor layer obtained can be made into the film containing the area | region which has excessive content of oxygen rather than stoichiometric composition ratio.

The amorphous oxide semiconductor layer included in the transistor 640 is a high purity film dehydrated or dehydrogenated by heat treatment after the amorphous oxide semiconductor layer is formed. Therefore, by using the amorphous oxide semiconductor layer in the transistor 640, the variation in the threshold voltage V _th of the transistor due to oxygen deficiency can be reduced, and the shift in the threshold voltage can be suppressed.

As the insulating layer 632, examples of the inorganic insulating material include an oxide insulating film, a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or a nitride such as a silicon oxide layer, a silicon oxynitride layer, an aluminum oxide layer, or an aluminum oxynitride layer. A single layer or a stack of nitride insulating films such as an aluminum oxide layer can be used.

As the interlayer insulating films 633 and 634, an insulating layer functioning as a planarization insulating layer is preferable in order to reduce surface irregularities. As the interlayer insulating films 633 and 634, organic insulating materials having heat resistance, such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin, can be used, for example. In addition to the above organic insulating material, a single layer or lamination of a low dielectric constant material (low-k material) such as siloxane resin, PSG (phosphorus glass), BPSG (phosphorus glass) or the like can be used.

By detecting the light incident on the photodiode 602, the information of the object to be detected can be read. In addition, a light source such as a backlight can be used when reading the information to be detected.

As described above, a transistor having an amorphous oxide semiconductor layer which is highly purified and contains excessive oxygen to compensate for oxygen deficiency is suppressed in fluctuation in electrical characteristics of the transistor and is electrically stable. Therefore, by using the transistor, a highly reliable semiconductor device can be provided.

The present embodiment can be implemented in appropriate combination with the configuration described in the other embodiments.

(Seventh Embodiment)

The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). As the electronic apparatus, for example, a television device (also called a television or a television receiver), a monitor for a computer, a camera such as a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone or a mobile phone device). And a large game machine such as a portable game machine, a portable information terminal, an audio reproducing apparatus, and a pachining machine. An example of an electronic apparatus including the semiconductor device described in the above embodiment will be described.

FIG. 14A is a notebook PC, and is composed of a main body 3001, a housing 3002, a display portion 3003, a keyboard 3004, and the like. By applying the semiconductor device described in any one of the above embodiments to the display portion 3003, a highly reliable notebook PC can be obtained.

14B is a portable information terminal (PDA), in which a display portion 3023, an external interface 3025, operation buttons 3024, and the like are formed in the main body 3021. There is also a stylus 3022 as an accessory for manipulation. By applying the semiconductor device described in any one of the above embodiments to the display unit 3023, a more reliable portable information terminal PDA can be obtained.

14C illustrates an example of an electronic book. For example, the electronic book is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by the shaft portion 2711, and the opening and closing operation can be performed with the shaft portion 2711 as the shaft. This configuration makes it possible to perform operations similar to books on paper.

The display portion 2705 is built in the housing 2701, and the display portion 2707 is built in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen or may be configured to display different screens. By setting the structure to display different screens, for example, sentences can be displayed on the right display unit (display unit 2705 in Fig. 14C), and images can be displayed on the left display unit (display unit 2707 in Fig. 14C). By applying the semiconductor device described in any one of the above embodiments to the display portion 2705 and the display portion 2707, an electronic book with high reliability can be obtained. When the transflective or reflective liquid crystal display device is used as the display portion 2705, the use in a relatively bright situation is also expected, so that a solar cell can be formed, power generation by the solar cell, and charging with a battery can be performed. You may do so. In addition, the use of a lithium ion battery as a battery has advantages such as miniaturization.

In addition, in FIG. 14C, the housing 2701 is equipped with the operation part etc. are shown. For example, the housing 2701 includes a power source 2721, an operation key 2723, a speaker 2725, and the like. The page can be turned by the operation key 2723. In addition, it is good also as a structure provided with a keyboard, a pointing device, etc. on the same surface as the display part of a housing. In addition, it is good also as a structure provided with the external connection terminal (earphone terminal, a USB terminal, etc.), a recording medium insertion part, etc. in the back surface or side surface of a housing. The electronic book may be configured to have a function as an electronic dictionary.

The electronic book may be configured to transmit and receive information wirelessly. It is also possible to make the structure which purchases and downloads desired book data etc. from an electronic book server by radio.

FIG. 14D is a mobile telephone and is composed of two housings, a housing 2800 and a housing 2801. The housing 2801 is provided with a display panel 2802, a speaker 2803, a microphone 2804, a pointing device 2806, a camera lens 2807, an external connection terminal 2808, and the like. The housing 2800 includes a solar cell 2810, an external memory slot 2811, and the like for charging a portable information terminal. In addition, the antenna is embedded in the housing 2801. By applying the semiconductor device described in any one of the above embodiments to the display panel 2802, a highly reliable mobile phone can be obtained.

In addition, the display panel 2802 has a touch panel, and a plurality of operation keys 2805 displayed by video are shown by dotted lines in FIG. 14D. In addition, a booster circuit for boosting the voltage output from the solar cell 2810 to a voltage required for each circuit is also mounted.

In the display panel 2802, the direction of display is appropriately changed depending on the use form. In addition, since the camera lens 2807 is provided on the same plane as the display panel 2802, video telephony is possible. The speaker 2803 and the microphone 2804 are not limited to a voice call, and video calls, recording, and playback can be performed. In addition, the housing 2800 and the housing 2801 can slide to be in an overlapped state in the unfolded state as shown in FIG. 14D, and can be miniaturized for portable use.

The external connection terminal 2808 can be connected to various cables such as an AC adapter and a USB cable, and can perform charging and data communication with a PC. In addition, a recording medium can be inserted into the external memory slot 2811, and a larger amount of data can be stored and moved.

In addition to the above functions, an infrared communication function, a television reception function, or the like may be provided.

FIG. 14E is a digital video camera, and is composed of a main body 3051, a display portion A 3057, an eyepiece portion 3053, an operation switch 3054, a display portion B 3055, a battery 3056, and the like. By applying the semiconductor device described in any one of the above embodiments to the display portion (A) 3057 and the display portion (B) 3055, a highly reliable digital video camera can be obtained.

14F shows an example of a television device. In the television apparatus, the display portion 9603 is incorporated in the housing 9601. An image can be displayed by the display portion 9603. In addition, the structure which supported the housing 9601 by the stand 9605 is shown here. By applying the semiconductor device described in any one of the above embodiments to the display portion 9603, a highly reliable television device can be obtained.

The operation of the television device can be performed by an operation switch included in the housing 9601 or a separate remote controller. In addition, it is good also as a structure which forms the display part which displays the information output from the said remote controller in a remote controller.

In addition, a television device is provided with a receiver, a modem, or the like. General television broadcasts can be received by the receiver and connected to a wired or wireless communication network via a modem, so that one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) It is also possible to perform information communication.

The present embodiment can be implemented in appropriate combination with the configuration described in the other embodiments.

(Example 1)

In this embodiment, evaluation was made as to the characteristics of the aluminum oxide film used as the barrier film in the semiconductor device according to the disclosed invention. The results are shown in Figures 15A1-18D. As an evaluation method, secondary ion mass spectrometry (SIMS) and elevated temperature desorption spectroscopy (TDS) were used.

First, evaluation by SIMS analysis is shown. As a comparative example, a silicon oxide film having a thickness of 100 nm was formed on a glass substrate by a sputtering method, and a silicon oxide film was formed on a glass substrate by a sputtering method with a thickness of 100 nm, and a silicon oxide film was formed on the glass substrate by a sputtering method. Example Sample A was prepared in which an aluminum oxide film was formed with a thickness of 100 nm.

In Comparative Example Sample A and Example Sample A, the silicon oxide film deposition conditions used a silicon oxide (SiO ₂ ) target as a target, and the distance between the glass substrate and the target was 60 mm, pressure 0.4 Pa, power supply 1.5 kW, The substrate temperature was 100 ° C. under an oxygen (oxygen flow rate 50 sccm) atmosphere.

Example In the sample A, the aluminum oxide film formation conditions are, as a target of aluminum oxide (Al ₂ O _3), and using the target, the 60mm distance between the glass substrate and the target, pressure 0.4Pa, power supply 1.5kW, argon and oxygen (Argon flow rate 25 sccm: Oxygen flow rate 25 sccm) The substrate temperature was 250 degreeC in atmosphere.

A pressure cooker test (PCT: Pressure Cooker Test) was performed on Comparative Sample A and Example Sample A. In the present Example, as a PCT test, Comparative Example Sample A and the implementation were carried out under conditions of a temperature of 130 ° C., a humidity of 85%, H ₂ O (water): D ₂ O (heavy water) = 3: 1 atmosphere, and 2.3 atmosphere (0.23 MPa). Example Sample A was held for 100 hours.

As the SIMS analysis, using SSDP (Substrate Side Depth Profile) -SIMS, the concentrations of H atoms and D (deuterium) atoms of each sample were measured for Comparative Example Sample A and Example Sample A before and after the PCT test. .

15A1 shows the concentration profiles of H atoms and D atoms by SIMS analysis before PCT test of Comparative Example Sample A and after PCT test of Comparative Example Sample A in FIG. 15A2. In FIG. 15A1 and FIG. 15A2, the D atom concentration (D expected) profile predicted is a concentration profile calculated from the profile of H atoms with an abundance ratio of D atoms of 0.015%. Therefore, the amount of D atoms mixed in the sample by the PCT test is a difference between the measured D atom concentration (D profile) and the expected D atom concentration (D expected). 15B1 shows the concentration profile of the D atom before the PCT test, and the concentration profile of the D atom after the PCT test is obtained by subtracting the predicted D atom concentration from the measured D atom concentration.

Similarly, FIG. 16A1 shows concentration profiles of H atoms and D atoms by SIMS before PCT test of Example Sample A, and FIG. 16A2 shows concentration profiles of H atoms and D atoms by SIMS after PCT test of Example Sample A. do. 16B1 shows the concentration profile of the D atom before the PCT test and FIG. 16B2 shows the concentration profile after the PCT test.

In addition, the SIMS analysis result of this Example has shown the result quantified all by the standard sample of a silicon oxide film.

As shown in Figs. 15A1 to 15B2, the concentration profile of the measured D atom and the predicted D atom concentration profile overlapped before the PCT test are increased at a high concentration after the PCT test. It is understood that the D atom is mixed in the silicon oxide film. Therefore, it was confirmed that the silicon oxide film of the comparative example sample was low in barrier property against moisture (H ₂ O, D ₂ O) from the outside.

On the other hand, as shown in Figs. 16A1 to 16B2, Example Sample A in which an aluminum oxide film was laminated on a silicon oxide film had only slightly invaded D atoms on the surface of the aluminum oxide film after the PCT test, and the aluminum oxide film depth was 30 nm. After the vicinity, no intrusion of D atoms appears in the silicon oxide film. Therefore, it was confirmed that the aluminum oxide film has a high barrier property against moisture (H ₂ O, D ₂ O) from the outside.

Next, the evaluation performed by TDS analysis is shown. The sample produced the Example sample B in which the silicon oxide film | membrane 100 nm in thickness was formed on the glass substrate by the sputtering method as an example sample, and the aluminum oxide film 20 nm in thickness was formed on the silicon oxide film by sputtering method. In addition, as a comparative example, after measuring the sample sample B by TDS analysis, the aluminum oxide film was removed from the sample sample B, and the comparative sample sample B in which only the silicon oxide film was formed on the glass substrate was produced.

In Comparative Example Sample B and Example Sample B, the silicon oxide film deposition conditions were a silicon oxide (SiO ₂ ) target as a target, and the distance between the glass substrate and the target was 60 mm, pressure 0.4 Pa, power supply 1.5 kW, The substrate temperature was 100 ° C. under an oxygen (oxygen flow rate 50 sccm) atmosphere.

EXAMPLES In sample B, the film forming conditions of the aluminum oxide film were aluminum aluminum (Al ₂ O ₃ ) targets as targets, and the distance between the glass substrate and the targets was 60 mm, pressure 0.4 Pa, power supply 1.5 kW, argon and oxygen. (Argon flow rate 25 sccm: Oxygen flow rate 25 sccm) The substrate temperature was 250 degreeC in atmosphere.

In Comparative Example Sample B and Example Sample B, further treatment was performed under nitrogen atmosphere for 1 hour under conditions of 300 ° C. heat treatment, 450 ° C. heat treatment and 600 ° C. heat treatment.

In Comparative Sample B and Example B, TDS analysis was performed on samples produced under four conditions of no heat treatment, 300 ° C. heat treatment, 450 ° C. heat treatment, and 600 ° C. heat treatment. In Comparative Sample B and Example B, there was no heat treatment in FIGS. 17A and 18A, 300 ° C. heat treatment in FIGS. 17B and 18B, 450 ° C. heat treatment in FIGS. 17C and 18C, and 600 ° C. heat treatment in FIGS. 17D and 18D. The TDS analysis result of measured M / z = 32 (O ₂ ) of each sample which was performed is shown.

As shown in Figs. 17A to 17D, in Comparative Example Sample B, oxygen was released from the silicon oxide film in Fig. 17A without heat treatment, but in the sample subjected to the 300 ° C heat treatment of Fig. 17B, the amount of oxygen was greatly reduced, In the sample which performed the 450 degreeC heat processing of FIG. 17C, and the sample which performed the 600 degreeC heat processing of FIG. 17D, it was below the background of TDS measurement.

17A to 17D show that at least 90% of the excess oxygen contained in the silicon oxide film is released to the outside from the silicon oxide film by a heat treatment at 300 ° C, and almost all of the heat treatment is performed at 450 ° C and 600 ° C. It can be seen that excess oxygen contained in the silicon oxide film is released to the outside of the silicon oxide film. Therefore, it was confirmed that the silicon oxide film had a low barrier property against oxygen.

On the other hand, in Example Sample B in which an aluminum oxide film was formed on a silicon oxide film, as shown in Figs. 18A to 18D, a sample without heat treatment was also used for a sample subjected to heat treatment at 300 ° C, 450 ° C, and 600 ° C. Equal amounts of oxygen were released.

18A to 18D show that the aluminum oxide film is formed on the silicon oxide film so that the excess oxygen contained in the silicon oxide film is not easily released to the outside even if heat treatment is performed, and the state contained in the silicon oxide film is considerable. It can be seen that it is maintained. Therefore, it was confirmed that the aluminum oxide film had a high barrier property against oxygen.

From the above results, it was confirmed that the aluminum oxide film has both a barrier property against hydrogen and moisture and a barrier property against oxygen, and functions suitably as a barrier film against hydrogen, water, and oxygen.

Therefore, the aluminum oxide film is mixed in the amorphous oxide semiconductor layer with impurities such as hydrogen and moisture, which are factors of fluctuation, during the fabrication process and after fabrication of the transistor including the amorphous oxide semiconductor layer, and oxygen from the amorphous oxide semiconductor layer. It can function as a protective film to prevent release.

Therefore, the amorphous oxide semiconductor layer formed is of high purity because impurities such as hydrogen and moisture are not mixed, and oxygen release is prevented, so that the content of oxygen with respect to the stoichiometric composition ratio of the amorphous oxide semiconductor layer in the crystal state is high. It contains excess area. Therefore, by using the amorphous oxide semiconductor layer in the transistor, the variation in the threshold voltage V _th of the transistor due to oxygen vacancies can be reduced, and the shift in the threshold voltage can be suppressed.

(Example 2)

In the present Example, the crystal state of the oxide semiconductor layer was observed.

As a sample, a 300 nm thick silicon oxide film was formed on a glass substrate by a sputtering method, a 100 nm thick In-Ga-Zn-O film was formed on a silicon oxide film by a sputtering method, and on an In-Ga-Zn-O film Example Sample C1 in which an aluminum oxide film was formed with a thickness of 100 nm by sputtering was produced.

The film forming conditions of the silicon oxide film use a silicon oxide (SiO ₂ ) target as a target, and the distance between the glass substrate and the target is 60 mm, pressure 0.4 Pa, RF power 1.5 kW, argon and oxygen (argon flow rate 25 sccm: oxygen flow rate 25 sccm). ) In the atmosphere, the substrate temperature was set at 100 ° C.

In addition, the film forming conditions of the In—Ga—Zn—O film were formed by using an oxide target of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 2 [mol ratio] as the composition ratio, and using the glass substrate and the target. The board | substrate temperature was 250 degreeC in 60 mm, pressure 0.4 Pa, RF power supply 0.5 kW, argon, and oxygen (argon flow volume 30 sccm: oxygen flow rate 15 sccm) atmosphere.

In addition, the silicon oxide film and the In-Ga-Zn-O film were continuously formed without releasing to air, and then heat-treated (first heat treatment) at 400 ° C. for 30 minutes in a reduced pressure atmosphere.

Thereafter, an aluminum oxide film was formed under the following conditions. Specifically, an aluminum oxide (Al ₂ O ₃ ) target is used as a target, and the distance between the glass substrate and the target is 60 mm, pressure 0.4 Pa, RF power supply 2.5 kW, argon and oxygen (argon flow rate 25 sccm: oxygen flow rate 25 sccm). In the atmosphere, the substrate temperature was set at 250 ° C.

Next, oxygen was injected into the In—Ga—Zn—O film through the aluminum oxide film of Example Sample C1 to prepare Example Sample C2. Example In sample C2, oxygen ( ¹⁸ O) ions were implanted through an aluminum oxide film through an In—Ga—Zn—O film by an ion implantation method. Oxygen ⁽¹⁸ O) of the ion implantation conditions were an acceleration voltage of 80kV, with a dose of 1.0 × 10 ¹⁶ ions / ㎠.

Further, Example Sample C2 was subjected to heat treatment (second heat treatment) at 450 ° C. for 1 hour in a nitrogen atmosphere to prepare Example Sample C3.

The cross sections of the example samples C1 to C3 obtained in the above steps are cut out, and the acceleration voltage is 300 kV under a high-resolution transmission electron microscope ("H9000-NAR" manufactured by Hitachi High-Technologies Corp .: TEM), and the cross section of the In-Ga-Zn-O film Observation was performed. 19A to 19C show TEM images of Example Samples C1 to C3.

FIG. 19A shows a TEM image of 8 million times magnification at the interface between the In—Ga—Zn—O film and the aluminum oxide film of Example Sample C1. FIG. 19B shows a TEM image of 8 million times magnification at the interface between the In—Ga—Zn—O film and the aluminum oxide film of Example Sample C2. In FIG. 19C, the TEM image of 8 million times magnification in the interface of the In-Ga-Zn-O film and aluminum oxide of Example sample C3 is shown.

In the In—Ga—Zn—O film shown in FIG. 19A, since the lattice image could be observed, it was confirmed that Example Sample C1 had a crystal region.

On the other hand, in the In—Ga—Zn—O film after the oxygen injection treatment shown in FIG. 19B, the lattice image shown in FIG. 19A was not observed.

In addition, in the In—Ga—Zn—O film shown in FIG. 19C after the oxygen injection treatment and heat treatment at 450 ° C., no lattice image was observed as in FIG. 19B. From this, it was confirmed that Example Sample C3 is amorphous.

As described above, it was confirmed that the amorphous region was maintained by performing oxygen injection into the oxide semiconductor layer having the crystal region, and the crystal region became an amorphous state and then heat treated at 450 ° C. or lower.

400: substrate 401: oxide semiconductor layer
402: base insulating layer 404: amorphous oxide semiconductor layer
406: gate insulating layer 410: gate electrode
412: insulating layer 421: oxygen
510: transistor 520: transistor
530: transistor 540: transistor
601 substrate 602 photodiode
608: adhesive layer 613: substrate
631: insulating layer 632: insulating layer
633: interlayer insulating film 634: interlayer insulating film
640: transistor 641a: electrode
641b: electrode 642: electrode
643: conductive layer 645: electrode
656: transistor 658: photodiode reset signal line
659: Gate signal line 671: Photo sensor output signal line
672: reference signal line 2701: housing
2703 housing 2705 display part
2707: display portion 2711: shaft portion
2721: power 2723: operation keys
2725: Speaker 2800: Housing
2801 housing 2802 display panel
2803: Speaker 2804: Microphone
2805: operation key 2806: pointing device
2807: Camera lens 2808: External connection terminal
2810: solar cell 2811: external memory slot
3001: main body 3002: housing
3003: display unit 3004: keyboard
3021: main body 3022: stylus
3023: Display unit 3024: Operation button
3025: external interface 3051: main body
3053 eyepiece 3054 operation switch
3055: display unit (B) 3056: battery
3057: display portion (A) 4001: substrate
4002: Pixel portion 4003: Signal line driver circuit
4004: Scan Line Driver Circuit 4005: Seal Material
4006: substrate 4008: liquid crystal layer
4010: transistor 4011: transistor
4013 Liquid crystal element 4015 Connection terminal electrode
4016 Terminal electrode 4018 FPC
4019: anisotropic conductive film 401a: oxide semiconductor layer
4020: insulation layer 4021: insulation layer
4023: insulating layer 4024: insulating layer
4030: electrode 4031: electrode
4032: insulation layer 4033: insulation layer
404a: amorphous oxide semiconductor layer 405a: source electrode
405b: drain electrode 4510: partition wall
4511 electroluminescent layer 4513 light emitting element
4514: Filling 4612: Cavity
4613 Spherical Particles 4614 Filler
606a: semiconductor film 606b: semiconductor film
606c: semiconductor film 9601: housing
9603 display unit 9605 stand
4018a: FPC 4615a: black area
4615b: white area

Claims (31)

In the method of manufacturing a transistor,
Forming an amorphous oxide semiconductor layer;
Forming a gate insulating layer in contact with the amorphous oxide semiconductor layer;
Injecting oxygen into the amorphous oxide semiconductor layer such that the amorphous oxide semiconductor layer includes a region containing oxygen that exceeds the stoichiometric composition ratio;
Forming a gate electrode on the gate insulating layer;
Forming an insulating layer comprising aluminum oxide on the gate electrode. The method of claim 1,
A method of manufacturing a transistor, wherein oxygen is injected before forming the gate insulating layer. The method of claim 1,
And the gate insulating layer includes a region containing oxygen that exceeds the stoichiometric composition ratio. The method of claim 1,
A first heating step of the amorphous oxide semiconductor layer prior to forming the gate insulating layer such that a crystalline region is formed in the amorphous oxide semiconductor layer,
And the crystal region is converted into an amorphous structure by injection of oxygen thereto. The method of claim 4, wherein
A second heating step of the amorphous oxide semiconductor layer after forming the insulating layer,
And wherein said second heating step is performed to maintain said amorphous structure. The method of claim 1,
The insulating layer comprises a first layer and a second layer over the first layer,
The second layer comprises aluminum oxide,
And the first layer comprises aluminum oxide and another metal oxide. The method according to claim 6,
Wherein the first layer comprises a region containing oxygen that exceeds the stoichiometric composition ratio. In the method of manufacturing a transistor,
Forming an oxide semiconductor layer having a crystal region;
Contacting the oxide semiconductor layer to form a gate insulating layer;
Injecting oxygen into the oxide semiconductor layer such that the crystal region is converted to an amorphous structure including a region containing oxygen that exceeds the stoichiometric composition ratio;
Forming a gate electrode on the gate insulating layer;
Forming an insulating layer comprising aluminum oxide on the gate electrode. The method of claim 8,
A method of manufacturing a transistor, wherein oxygen is injected before forming the gate insulating layer. The method of claim 8,
And the gate insulating layer includes a region containing oxygen that exceeds the stoichiometric composition ratio. The method of claim 8,
After the insulating layer is formed, further comprising the step of heating the oxide semiconductor layer,
And wherein said heating step is performed to maintain an amorphous structure of said oxide semiconductor layer. The method of claim 8,
The insulating layer comprises a first layer and a second layer over the first layer,
The second layer comprises aluminum oxide,
And the first layer comprises aluminum oxide and another metal oxide. 13. The method of claim 12,
Wherein the first layer comprises a region containing oxygen that exceeds the stoichiometric composition ratio. In the method of manufacturing a transistor,
Forming a gate electrode on the substrate;
Forming a gate insulating layer on the gate electrode;
Forming an amorphous oxide semiconductor layer on the gate insulating layer;
Injecting oxygen into the amorphous oxide semiconductor layer such that the amorphous oxide semiconductor layer includes a region containing oxygen that exceeds the stoichiometric composition ratio;
Forming an insulating layer comprising aluminum oxide on the amorphous oxide semiconductor layer. 15. The method of claim 14,
A method of manufacturing a transistor in which oxygen is injected after the gate insulating layer is formed. 15. The method of claim 14,
And the gate insulating layer includes a region containing oxygen that exceeds the stoichiometric composition ratio. 15. The method of claim 14,
A first heating step of the amorphous oxide semiconductor layer prior to forming the gate insulating layer such that a crystalline region is formed in the amorphous oxide semiconductor layer,
And the crystal region is converted into an amorphous structure by injection of oxygen thereto. The method of claim 17,
A second heating step of the amorphous oxide semiconductor layer after forming the insulating layer,
And wherein said second heating step is performed to maintain said amorphous structure. 15. The method of claim 14,
The insulating layer comprises a first layer and a second layer over the first layer,
The second layer comprises aluminum oxide,
And the first layer comprises aluminum oxide and another metal oxide. The method of claim 19,
Wherein the first layer comprises a region containing oxygen that exceeds the stoichiometric composition ratio. In the method of manufacturing a transistor,
Forming a gate electrode on the substrate;
Forming a gate insulating layer on the gate electrode;
Forming an oxide semiconductor layer including a crystal region on the gate insulating layer;
Injecting oxygen into the oxide semiconductor layer such that the crystal region is converted to an amorphous structure including a region containing oxygen that exceeds the stoichiometric composition ratio;
Forming an insulating layer comprising aluminum oxide on the oxide semiconductor layer. 22. The method of claim 21,
A method of manufacturing a transistor, wherein oxygen is injected after forming the insulating layer. 22. The method of claim 21,
And the gate insulating layer includes a region containing oxygen that exceeds the stoichiometric composition ratio. 22. The method of claim 21,
After the insulating layer is formed, further comprising the step of heating the oxide semiconductor layer,
And wherein said heating step is performed to maintain an amorphous structure of said oxide semiconductor layer. 22. The method of claim 21,
The insulating layer comprises a first layer and a second layer over the first layer,
The second layer comprises aluminum oxide,
And the first layer comprises aluminum oxide and another metal oxide. The method of claim 25,
Wherein the first layer comprises a region containing oxygen that exceeds the stoichiometric composition ratio. In a semiconductor device comprising a transistor,
The transistor is:
A gate electrode;
An amorphous oxide semiconductor;
A gate insulating layer interposed between the gate electrode and the amorphous oxide semiconductor;
An insulating layer including aluminum oxide on the gate electrode, the amorphous oxide semiconductor, and the gate insulating layer,
The amorphous oxide semiconductor includes a region containing oxygen in excess of the stoichiometric composition ratio. The method of claim 27,
And the gate insulating layer includes a region containing oxygen that exceeds the stoichiometric composition ratio. The method of claim 27,
The insulating layer comprises a first layer and a second layer over the first layer,
The second layer comprises aluminum oxide,
And the first layer comprises aluminum oxide and another metal oxide. 30. The method of claim 29,
And the first layer includes a region containing oxygen that exceeds the stoichiometric composition ratio. 28. An electronic device comprising the semiconductor device according to claim 27.

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