KR20120121426A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: A semiconductor integrated circuit is provided to improve operational reliability by equally loading signals inputted to each semiconductor chip regardless of an order of stacks. CONSTITUTION: A first chip through via transfers a first signal to a second semiconductor chip. The first chip through via is arranged passing through first and second semiconductor chips. First wiring(260) electrically connects a first internal circuit(212). A second chip through via transfers a second signal to the first semiconductor chip. Second wiring(280) electrically connects a second internal circuit(242).

Description

[0001] SEMICONDUCTOR INTEGRATED CIRCUIT [0002]

The present invention relates to semiconductor design technology, and more particularly, to a semiconductor integrated circuit having a three dimensional (3D) stack package structure.

In general, packaging technology for semiconductor integrated circuits has been continuously developed to meet the demand for miniaturization and mounting reliability. Recently, as the miniaturization of electric / electronic products and high performance are required, various technologies for stack packages have been developed.

The term "stack" in the semiconductor industry refers to stacking at least two or more semiconductor chips or packages vertically. According to such a stack package, for example, in the case of a semiconductor memory device, a memory capacity of twice as much as a memory capacity that can be realized in a semiconductor integration process It can implement a product having. In addition, since stack packages have advantages in terms of increasing memory capacity and efficiency of mounting density and footprint area, research and development on stack packages are being accelerated.

A stack package can be manufactured by stacking individual semiconductor chips, and then stacking stacked semiconductor chips at once, and stacking individual packaged semiconductor chips. The individual semiconductor chips of the stack package are formed of metal wires or through silicon vias. (Through Silicon Via (TSV), etc. are electrically connected. In particular, a stack package using a through silicon via (TSV) is a structure in which a through silicon via (TSV) is formed in a semiconductor chip so that physical and electrical connections between the semiconductor chips are made vertically by the through silicon via (TSV).

1 is a diagram illustrating a semiconductor chip in which a through silicon via (TSV) is inserted.

Referring to FIG. 1, a hole is formed in an upper surface of a semiconductor chip A, and a through silicon via B is formed by filling a hole with a highly conductive metal such as copper (Cu), and then through a through silicon via ( When the lower surface of the semiconductor chip A is cut so that the lower end of B) is exposed to the outside, the semiconductor chip C for the stack is formed. A plurality of such semiconductor chips C are stacked to be mounted on a package substrate such as a printed circuit board (PCB) to form a semiconductor integrated circuit. Such a semiconductor integrated circuit is called a 3D stack package semiconductor integrated circuit.

2 is a perspective view illustrating a 3D stack package semiconductor integrated circuit.

Referring to FIG. 2, a 3D stack package semiconductor integrated circuit (hereinafter referred to as a “semiconductor integrated circuit”) 100 may include first to fourth semiconductor chips 110, 120, 130, and 140 stacked in order from the bottom, and an external portion thereof. A first through silicon via 150 disposed through the first semiconductor chip 110, a first through silicon via 150, and a first signal applied to the first semiconductor chip 110. The first wiring 160a for electrically connecting the first internal circuit 112 included in the first semiconductor chip 110 and the second signal applied from the outside to the first semiconductor chip 110 are provided. The second through silicon via 170 disposed through the first semiconductor chip 100 and the second signal transmitted through the second through silicon via 170 are transferred to the fourth semiconductor chip 140. To the third through silicon via 180 disposed through the fourth to fourth semiconductor chips 120, 130, and 140, and the first semiconductor chip 100. The second semiconductor wire 160b for electrically connecting the second through silicon via 170 and the third through silicon via 180 and the second signal transmitted through the third through silicon via 180 to the fourth semiconductor chip. A second wiring 190 is provided for transferring to the second internal circuit 142 provided at the. Here, the first and second signals are signals of the same series, and all signals having similar timing relationships may be applied. For example, the first and second signals may be clock signals CLKB inverted from the clock signals CLK.

Meanwhile, the first and second through silicon vias 150 and 170 may include one through silicon via vertically penetrating only the first semiconductor chip 110, and the third through silicon via 180 may include the second through second vias. And four through silicon vias 181, 183, and 185 that vertically penetrate the four semiconductor chips 120, 130, and 140, respectively. For reference, although not illustrated in the drawing, the first through fourth semiconductor chips 110, 120, 130, and 140 corresponding to the first through third through silicon vias 150, 170, and 180 configured as described above, respectively, may be used. An insulating layer is provided between the first through third through silicon vias 150, 170, and 180 and the corresponding first through fourth semiconductor chips 110, 120, 130, and 140, respectively, in order to electrically isolate the first through third vias.

Hereinafter, the operation of the semiconductor integrated circuit 100 having the above configuration will be described.

When the first and second signals are applied from the outside, the first signal is transmitted to the first internal circuit 112 through the first through silicon via 150 and the first wiring 160, and the second signal is the second signal. The through silicon via 170, the second wiring 160b, the third through silicon via 180, and the third wiring 190 are transferred to the second internal circuit 142.

Then, the first and second internal circuits 112 and 142 perform predetermined operations in response to the first and second signals, respectively.

According to the semiconductor integrated circuit 100, as the first and second signals are transmitted through the first and second through silicon vias 150 and 170, the current consumption and the signal delay may be reduced, but the bandwidth is improved. ) Has the advantage of excellent operating performance.

However, the semiconductor integrated circuit 100 according to the related art having the above configuration has the following problems.

FIG. 3A shows a circuit diagram that equally expresses the loading, that is, the loading from the A node to the B node, until the first signal is input from the outside and reaches the first internal circuit 112. 3b shows a circuit diagram equivalently expressing the loading from the second signal to the second internal circuit 142, that is, the loading from the A 'node to the B' node.

First, referring to FIG. 3A, between the node A and the node B, the loading C _TSV1 by the first through silicon via 150 and the loading by the first wiring 160 R _{on - chip1} , C _{on - chip1} ) Will exist. In this case, the first aneunde through not being includes the resistance component (R _TSV1) loading (C _TSV1) according to the silicon via 150, which is the resistance component of the first wiring 160 _- negligible compared to (R _{on chip1)} Because it is small (R _{on - chip1} ? R _TSV1 ). This will be described in more detail below. Therefore, as the insulating film is provided between the first semiconductor chip 110 and the first through silicon via 150, a parasitic capacitor is formed, and only the capacitance according to the formed parasitic capacitor is loaded ( C _TSV1 ).

Referring to Figure 3b, A loaded by the 'node and B', the second load by the through-silicon vias 170 between the node (C _TSV2) and a second wire (160a) (R _{on - chip2,} C _{on - chip2} ), loading (C _TSV3 ) by the third through silicon via 180, and loading (R _{on - chip3} , C _on-chip3 ) by the third wiring 190. In this case, the resistance components R _TSV2 are not included in the loadings C _TSV2 and C _TSV3 by the second and third through silicon vias 170 and 180, as described above. This is because they are negligibly small compared to the resistive components R _{on - chip 2} and R _{on - chip 3} of 160b and 190. In other words, the semiconductor integrated circuit 100 typically has a thickness of 1 mm or less. The thickness of the semiconductor integrated circuit 100 is 1 mm or less means that the vertical lengths of the second and third through silicon vias 170 and 180 are It means less than 1mm. However, since the frequency currently used for a memory device or the like is several GHZ or less, the length of the wavelength is several cm even when the dielectric constants of the semiconductor chips 110, 120, 130, and 140 are considered. As such, the vertical lengths of the second and third through silicon vias 170 and 180 are negligibly small compared to the wavelength of the frequency, so that the second and third through silicon vias 170 and 180 can be regarded as one node. will be. Accordingly, if the resistance components R _TSV2 and R _TSV3 by the second and third through silicon vias 170 and 180 and the IR drop due to the inductance are insignificant, the second and third through silicon vias 170 and 180 may be _replaced . It can be seen as a node. However, since parasitic capacitors are formed between the first to fourth semiconductor chips 110, 120, 130, and 140 and the second and third through silicon vias 170 and 180, parasitic capacitors are formed. The three through silicon vias 170 and 180 have only loadings C _TSV2 and C _TSV3 according to the formed parasitic capacitors.

Here, the first through-the same as the silicon via 150 is loaded (C _TSV1) a second load (C _TSV2) by the through-silicon via 170 by, the loading due to the first wire (160a) (R _{on - chip1} , C _{on - chip 1} ) is _equal to the _sum of the loadings (R _{on - chip 2} , C _{on - chip 2} ) (R _{on - chip 3} , C _{on - chip} 3) by the second and third wires 160b, 190. The second signal is more affected by the loading C _TSV3 by the third through silicon via 180 than the first signal. This causes a time difference between the first and second signals reaching the first and second internal circuits 112 and 142, and the time difference means a skew between the first and second signals. . In summary, since the loading affecting the input signal is differently reflected according to the stacking order of the first to fourth semiconductor chips 110, 120, 130, and 140, the first to fourth semiconductor chips 110, 120, Skew is generated between the signals input to the 130 and 140, respectively.

Accordingly, in the case of the semiconductor integrated circuit 100, for example, a memory device in which timing is important, malfunctions due to timing errors are caused as skew occurs between the first and second signals as described above. There is this.

It is an object of the present invention to provide a semiconductor integrated circuit in which signals input to each semiconductor chip have the same loading regardless of the stacking order of the semiconductor chips.

According to an aspect of the present invention, the present invention provides a semiconductor integrated circuit including first and second semiconductor chips that are stacked and share a signal through chip through vias, wherein the first signal is externally provided to the second semiconductor. A first chip through via disposed through the first and second semiconductor chips for delivery to the chip; First wirings for electrically connecting the first chip through via and the first internal circuit provided in the second semiconductor chip; A second chip through via disposed through the first semiconductor chip to transmit an externally provided second signal to the first semiconductor chip; Second wirings for electrically connecting the second chip through via and the second internal circuit provided in the first semiconductor chip; And a dummy chip through via connected to the second wiring and disposed through the second semiconductor chip. Here, the first and second signals are signals of the same series and refer to signals having the same timing.

According to another aspect of the present invention, the present invention provides a semiconductor integrated circuit having first and second semiconductor chips that share a signal through chip through vias and are sequentially stacked, the internalized first provided in the first semiconductor chip. A first chip through via disposed through the second semiconductor chip to transmit a signal to the second semiconductor chip; First wirings for electrically connecting the first chip through via and the first internal circuit provided in the second semiconductor chip; A second wiring for transferring an internalized second signal provided from the first semiconductor chip to a second internal circuit provided in the first semiconductor chip; And a dummy chip through via connected to the second wiring and disposed through the second semiconductor chip. Here, the first and second signals are signals of the same series and refer to signals having the same timing.

In the present invention, since the signals input to each semiconductor chip have the same loading regardless of the stacking order of the semiconductor chips, the timing can be accurately considered, thereby improving the operation reliability of the semiconductor integrated circuit.

1 is a diagram for describing a semiconductor chip in which a through silicon via (TSV) is inserted;
2 is a perspective view of a semiconductor integrated circuit according to the prior art.
FIG. 3A is an equivalent circuit diagram of loading from node A to node B shown in FIG. 2; FIG.
FIG. 3B is an equivalent circuit diagram of loading from node A 'to node B' shown in FIG. 2; FIG.
4 is a perspective view of a semiconductor integrated circuit according to the first embodiment of the present invention.
FIG. 5A is an equivalent circuit diagram of loading from node A to node B shown in FIG. 4; FIG.
FIG. 5B is an equivalent circuit diagram of loading from node A 'to node B' shown in FIG. 4; FIG.
6 is a perspective view of a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 7A is an equivalent circuit diagram of loading from node A to node B shown in FIG. 6; FIG.
FIG. 7B is an equivalent circuit diagram of loading from node A 'to node B' shown in FIG. 6; FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

The semiconductor integrated circuit described in the embodiment of the present invention refers to a semiconductor integrated circuit having a three dimensional stack package structure. Accordingly, the semiconductor integrated circuit according to an exemplary embodiment of the present invention will be described with an example in which four semiconductor chips are stacked for convenience of description, and only a signal transmitted to the first and fourth semiconductor chips will be described as an example.

4 shows a semiconductor integrated circuit according to a first embodiment of the present invention.

Referring to FIG. 4, a semiconductor integrated circuit 200 including first to fourth semiconductor chips 210, 220, 230, and 240 that are sequentially stacked and share a signal through a through silicon via (TSV). The first through silicon via 250 disposed through the first to fourth semiconductor chips 210, 220, 230, and 240 to transmit an externally provided first signal to the fourth semiconductor chip 240 may include: First wiring 260 for electrically connecting the first through silicon via 250 and the first internal circuit 242 provided in the fourth semiconductor chip 240, and a second signal provided from the outside. The second through silicon via 270 disposed through the first semiconductor chip 210, the second through silicon via 270, and the first semiconductor chip 210 are provided to the first semiconductor chip 210. A second wiring 280 for electrically connecting the second internal circuit 212 and the second to fourth semiconductor chips 220, 230, which are connected to the second wiring 280. A dummy through silicon via 290 disposed through 240. Here, the first and second signals are signals of the same series and refer to signals having the same timing. For example, the first and second signals may be clock signals CLKB inverted from the clock signals CLK.

The semiconductor integrated circuit 200 may be disposed on an upper surface of the fourth semiconductor chip 240, and may include a first connection pad P1 for substantially connecting the first through silicon via 250 and the first wiring 260. And a first dummy connection pad P2 disposed on an upper surface of the fourth semiconductor chip 240 and connected to one end of the dummy chip through via 290. At this time, the first dummy connection pad P2 is not connected to any wiring provided in the fourth semiconductor chip 240.

Although not illustrated in the drawing, the semiconductor integrated circuit 200 may further include an insulating layer surrounding the first and second through silicon vias 250 and 270 and the dummy through silicon vias 290, respectively. Accordingly, the first and second through silicon vias 250 and 270 and the dummy through silicon vias 290 and the first through fourth semiconductor chips 210, 220, 230, and 240 corresponding thereto are electrically separated from each other. .

Meanwhile, the first through silicon via 250 includes four through silicon vias 251, 253, 255, and 257 that vertically penetrate the first to fourth semiconductor chips 210, 220, 230, and 240, respectively. Three connection pads are included between the four through silicon vias 251, 253, 255, and 257. In addition, since the second through silicon via 270 is vertically penetrated only through the first semiconductor chip 210, the second through silicon via 270 includes only one through silicon via. In addition, the dummy through silicon via 290 includes three through silicon vias 291, 293, and 295 vertically penetrating the second through fourth semiconductor chips 220, 230, and 240, respectively, and three through silicon vias. Three connection pads are included between the vias 291, 293, and 295 and the second through silicon vias 270. Here, in the present exemplary embodiment, the dummy through silicon via 290 is disposed at the same position in the vertical direction as the second through silicon via 270, but is not necessarily limited thereto and is only connected to the second wiring 280. If so, the second through silicon via 270 may be disposed at a position different from the vertical direction.

Hereinafter, the operation of the semiconductor integrated circuit 200 according to the first embodiment of the present invention having the above configuration will be described.

When the first and second signals are applied from the outside, the first signal is transmitted to the first internal circuit 242 through the first through silicon via 250 and the first wiring 260, and the second signal is transmitted to the second signal. The through silicon via 270 and the second wiring 280 are transferred to the second internal circuit 212.

In this case, the loading until the first signal is input to the first through silicon via 250 and reaches the first internal circuit 242, that is, the loading from the A node to the B node is expressed as an equivalent circuit, FIG. 5A. Same as Referring to FIG. 5a, the loading on the A node between the B node of the first through-silicon vias (250) (C _TSV1) and the loading by the first wiring _{(260) (R on - chip1} , C on - chip1) is present Done. Here, the first aneunde through not containing the the resistance component (R _TSV1) loading (C _TSV1) according to the silicon via 250, which is the resistance component of the first wiring 260 _- negligible compared to (R _{on chip1)} Because it is small (R _{on - chip1} ? R _TSV1 ). In other words, the semiconductor integrated circuit 200 typically has a thickness of 1 mm or less, and the thickness of the semiconductor integrated circuit 200 is 1 mm or less means that the vertical length of the first through silicon via 250 is 1 mm or less. Done. However, since the frequency currently used for semiconductor integrated circuits such as memory devices is several GHZ or less, the length of the wavelength is several cm even when the dielectric constants of the semiconductor chips 210, 220, 230, and 240 are taken into account. As such, the fact that the vertical length of the first through silicon via 250 is negligibly small compared to the wavelength of the frequency may refer to the first through silicon via 250 as a node. Therefore, when the resistance component R _TSV1 due to the first through silicon via 250 and the IR drop due to inductance are insignificant, the first through silicon via 250 may be regarded as one node. However, since a parasitic capacitor is formed between the first to fourth semiconductor chips 210, 220, 230, and 240 and the first through silicon via 250, the first through silicon via 250 is formed. Only the capacitance according to the formed parasitic capacitor will have a loading (C _TSV1 ).

In addition, when the second signal is input to the second through silicon via 270 and reaches the second internal circuit 212, that is, the loading from the node A 'to the node B' is represented by an equivalent circuit. Same as 5b. Referring to FIG. 5B, the loading C _TSV2 by the second through silicon via 270, the loading C _TSV3 by the dummy through silicon via 290, and the second wiring between the node A ′ and the B ′ node are _illustrated . There is loading (R _{on - chip 2} , C _{on - chip 2} ) by 280. Here, the second no through-silicon vias not include the 270 loads (C _TSV1) and dummy load by a through-silicon via (290) (C _TSV3) has a resistance component (R _TSV1) by which, as described above the 2, the resistance component of the wire 280 _- because small negligible compared to (R _{on chip2)} (R _{on - chip1} ? R _TSV1 ). In this way, the second load (C _TSV3) by the through-silicon vias loaded by the (270) (C _TSV1) and dummy through silicon via 290 is a structure that shares the same node.

Thus, the loading between node A and node B is equal to the loading between node A 'and node B', so that skew between the first and second signals is minimized.

Meanwhile, the first and second internal circuits 242 and 212 perform predetermined operations in response to the first and second signals, respectively.

According to the first exemplary embodiment of the present invention, there is an advantage in that malfunctions due to timing errors can be prevented by minimizing skew between signals input to each semiconductor chip regardless of the stacking order of the semiconductor chips.

6 is a perspective view of a semiconductor integrated circuit according to a second embodiment of the present invention.

The second embodiment of the present invention is an embodiment according to the case where the first and second signals generated therein and having the same timing are transferred to semiconductor chips stacked at different positions, respectively.

Referring to FIG. 6, a semiconductor integrated circuit 300 including first to fourth semiconductor chips 310, 320, 330, and 340 which share a signal through a through silicon via (TSV) and are sequentially stacked. The first through silicon via 310 for vertically penetrating the first semiconductor chip 310 and receiving an external signal, and the first and the first internally provided in the first semiconductor chip 310 and internalized in response to the external signal. A first internal circuit 312 for generating a second signal, a first wiring 360a for electrically connecting the first through silicon via 350 and the first internal circuit 312, and a first internal circuit ( A second through silicon via 370 disposed through the second to fourth semiconductor chips 320, 330, and 340 to transfer the internalized first signal output from the 312 to the fourth semiconductor chip 340; And a second double for electrically connecting the second through silicon via 370 and the second internal circuit 342 provided in the fourth semiconductor chip. A third wire 360b for transmitting the internalized second signal output from the line 380 and the first internal circuit 312 to the third internal circuit 314 provided in the first semiconductor chip 310; A dummy through silicon via 390 connected to the third wiring and disposed through the second to fourth semiconductor chips 320, 330, and 340, and an internalized first signal output from the first internal circuit 312. Fourth wiring 360c for transmitting the second through silicon via 370 is provided.

The semiconductor integrated circuit 300 may include a first connection pad P11 disposed on an upper surface of the fourth semiconductor chip 340 to substantially connect the second through silicon via 370 and the second wiring 280. The first dummy connection pad P21 is further provided on the top surface of the fourth semiconductor chip 340 and connected to one end of the dummy through silicon via 390. At this time, the first dummy connection pad P21 is not connected to any wiring provided in the fourth semiconductor chip 340.

Although not illustrated in the drawing, the semiconductor integrated circuit 200 further includes an insulating layer surrounding the first and second through silicon vias 350 and 370 and the dummy through silicon via 390, respectively. Accordingly, the first and second through silicon vias 350 and 370 and the dummy through silicon vias 390 and the first through fourth semiconductor chips 310, 320, 330, and 340 corresponding thereto are electrically separated from each other. .

Meanwhile, the second through silicon via 370 includes three through silicon vias 371, 373, and 375 vertically penetrating the second to fourth semiconductor chips 320, 330, and 340, respectively, and three through silicon vias 370. Two connection pads are included between the silicon vias 371, 373, and 375. The dummy through silicon via 390 includes three through silicon vias 391, 393, and 395 vertically penetrating the second through fourth semiconductor chips 320, 330, and 340, respectively, and three through silicon vias. Similarly to the second through silicon via 370, the vias 391, 393, and 395 include two connection pads. For reference, in the present exemplary embodiment, the dummy through silicon via 390 is illustrated as being disposed in the center portion of the third wiring 360b. It may be arrange | positioned in another position.

Hereinafter, the operation of the semiconductor integrated circuit 300 according to the second embodiment of the present invention having the above configuration will be described.

When an external signal is applied through the first through silicon via 360a, the first internal circuit 312 generates internalized first and second signals corresponding to the external signal. In this case, the first and second signals are signals of the same series, and all signals having the same timing may be applied. For example, the first and second signals may be clock signals CLK and inverted clock signals CLKB.

Subsequently, the first signal output from the first internal circuit 312 is transferred to the second internal circuit 342 through the fourth wiring 360c, the first through silicon via 370, and the second wiring 380. Delivered. In this case, the loading until the first signal is input to the fourth wiring 360c and reaches the second internal circuit 342, that is, the loading from the A node to the B node is expressed as an equivalent circuit, as shown in FIG. 7A. . _Referring to FIG. 7A, between the node A and the node B, the loading (R _on-chip1 , C _on-chip1 ) by the fourth wiring 360c and the loading (C _TSV1 ) by the first through silicon via 370 and There is a loading (R _{on - chip 2} , C _{on - chip} 2) by the second wiring 380. Of course, the resistive component R _TSV1 is not included in the loading C _TSV1 by the first through silicon via 370. This is because, as described in the first embodiment of the present invention, it is small enough to be ignored compared to the resistance components R _{on -chip 1} and R _{on - chip} 2 of the second and fourth wirings 380 and 360a (see FIG. 5A). . Therefore, when the resistance component R _TSV1 due to the first through silicon via 370 and the IR drop due to inductance are insignificant, the first through silicon via 370 may be regarded as one node D, and the second As the insulating layer is provided between the fourth to fourth semiconductor chips 320, 330, and 340 and the first through silicon via 370, only the capacitance of the parasitic capacitor formed as the loading C _TSV1 may be provided.

At the same time, the second signal output from the first internal circuit 312 is transmitted to the third internal circuit 314 through the third wiring 360b. In this case, the loading until the second signal is input to the third wiring 360b and reaches the third internal circuit 314, that is, the loading from the node A 'to the node B' is represented by an equivalent circuit. Same as 7B, between the node A 'and the node B', loading (R _{on - chip 3} , C _{on - chip} 3) corresponding to half of the third wiring ₃₆₀ c _- corresponds to the fourth wiring _{360 c-} , and Loading (C _TSV2 ) by the dummy through silicon via 390-corresponding to the first through silicon via 370-and loading corresponding to the other half of the third wiring 280 (R _{on - chip4} , C _{on) -chip4} ) _{-corresponding to} the second wiring 380-exists. Here, since the dummy through silicon via 390 may be viewed as a node D 'as described above, the dummy through silicon via 390 may be disposed between the second through fourth semiconductor chips 320, 330, and 340. Only the capacitance according to the parasitic capacitor formed in the will have a loading (C _TSV2 ).

Accordingly, the loading between node A and node B is equal to the loading between node A 'and node B', so that skew between the first and second signals is minimized.

Meanwhile, the second and third internal circuits 342 and 314 perform predetermined operations in response to the first and second signals, respectively.

According to the second exemplary embodiment of the present invention, there is an advantage in that malfunctions due to timing errors can be prevented by minimizing skew between signals input to each semiconductor chip regardless of the stacking order of the semiconductor chips.

Although the technical spirit of the present invention has been described in detail with reference to the above embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

For example, in the exemplary embodiment of the present invention, a dummy through silicon via is provided in order to ensure that signals input to a plurality of stacked semiconductor chips have the same loading, but the present invention is not limited thereto. It is also possible to have a circuit that can adjust the loading, such as a delay circuit, in place of the silicon via.

200: semiconductor integrated circuit 210: first semiconductor chip
212: first internal circuit 220: second semiconductor chip
230: third semiconductor chip 240: fourth semiconductor chip
242: second internal circuit 250: first through silicon via
260: first wiring 270: second through silicon via
280: second wiring 290: dummy through silicon via

Claims (18)

A semiconductor integrated circuit comprising first and second semiconductor chips stacked to share signals through chip through vias, the semiconductor integrated circuit comprising:
A first chip through via disposed through the first and second semiconductor chips to transmit an externally provided first signal to the second semiconductor chip;
First wirings for electrically connecting the first chip through via and a first internal circuit provided in the second semiconductor chip;
A second chip through via disposed through the first semiconductor chip to transmit an externally provided second signal to the first semiconductor chip;
Second wirings for electrically connecting the second chip through via and a second internal circuit provided in the first semiconductor chip; And
A dummy chip through via connected to the second wiring and penetrating the second semiconductor chip.
Semiconductor integrated circuit comprising a.
The method of claim 1,
And the first and second signals are signals of the same series.
The method according to claim 1 or 2,
An insulating film is further provided around each of the first and second chip through vias and the dummy chip through via;
And the insulating layer electrically insulates between the first and second chip through vias and the first and / or second semiconductor chips corresponding to the dummy chip through vias, respectively.
The method of claim 3,
And a first connection pad disposed on an upper surface of the second semiconductor chip and configured to substantially connect the first chip through via and the first wiring.
The method of claim 3,
And the first chip through via comprises third and fourth chip through vias respectively disposed corresponding to the first and second semiconductor chips.
The method of claim 5,
And a second connection pad for electrically connecting the third and fourth chip through vias.
The method of claim 3,
A first dummy connection pad disposed on an upper surface of the second semiconductor chip and connected to one end of the dummy chip through via;
And the first dummy connection pad is not connected to any wiring provided in the second semiconductor chip.
The method of claim 3,
The dummy chip through via may include first and second dummy chip through vias disposed corresponding to the first and second semiconductor chips, respectively; And
And a second dummy connection pad for electrically connecting the first and second dummy chip through vias.
The method of claim 1,
And the first and second chip through vias and the dummy chip through vias include through silicon vias (TSVs).
A semiconductor integrated circuit comprising first and second semiconductor chips that share a signal through chip through vias and are sequentially stacked,
A first chip through via disposed through the second semiconductor chip to transfer the internalized first signal provided from the first semiconductor chip to the second semiconductor chip;
First wirings for electrically connecting the first chip through via and a first internal circuit provided in the second semiconductor chip;
A second wiring for transferring an internalized second signal provided from the first semiconductor chip to a second internal circuit provided in the first semiconductor chip; And
A dummy chip through via connected to the second wiring and penetrating the second semiconductor chip.
Semiconductor integrated circuit comprising a.
The method of claim 10,
And the internalized first and second signals are signals of the same series.
The method according to claim 10 or 11,
An insulating film is further provided around the first chip through via and the dummy chip through via;
And the insulating layer electrically insulates the first and second chip vias from the first and / or second semiconductor chips, respectively.
The method of claim 12,
A third internal circuit provided in the first semiconductor chip and configured to generate the internalized first and second signals in response to a signal applied from the outside;
Third wirings for transmitting the internalized second signal output from the third internal circuit to the first chip through via;
A second chip through via disposed through the first semiconductor chip to transmit a signal applied from the outside to the third internal circuit; And
And a fourth wiring for electrically connecting the second chip through via and the third internal circuit.
The method of claim 13,
The sum of the loadings of the first and third wirings is equal to the loading of the second wirings.
The method of claim 13,
And an insulating film surrounding the second chip through via.
The method of claim 13,
And a first connection pad disposed on an upper surface of the second semiconductor chip, the first connection pad for substantially connecting the chip through via and the first wiring.
The method of claim 13,
A first dummy connection pad disposed on an upper surface of the second semiconductor chip and connected to one end of the dummy chip through via;
And the first dummy connection pad is not connected to any wiring provided in the second semiconductor chip.
The method of claim 12,
The first chip through via and the dummy chip through via include a through silicon via (TSV).

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