KR20120121144A - Method and apparatus for transmitting and receiving data in wireless communication system - Google Patents

Abstract

PURPOSE: A method and apparatus for transmitting and receiving data in a wireless communication system are provided to transmit and receive data of a variable length by determining an expansion parity check matrix from mother matrices without an additional parity. CONSTITUTION: A data transmission method includes following steps. One parity check matrix is selected from a plurality of parity check matrices according to an information word length or a given parity bit size. Data is encoded by the selected parity check matrix. The encoded data as is transmitted. A process of selecting the parity check matrix includes a process of successively comparing the information word length or the given parity bit size with a plurality of thresholds. The process of selecting the parity check matrix includes a process of determining a corresponding parity check matrix according to comparison results. [Reference numerals] (AA) Information word part; (BB) First parity part; (CC) Second parity part; (DD) Third parity part

Description

METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING DATA IN WIRELESS COMMUNICATION SYSTEM}

The present invention relates to a wireless communication system, and more particularly, to an apparatus and method for transmitting and receiving data in a wireless communication system.

In a wireless communication system, link performance may be significantly degraded by channel noise, fading, and inter-symbol interference (ISI). Accordingly, in order to implement high-speed digital communication systems requiring high data throughput and reliability, such as next-generation mobile communication, digital broadcasting, and portable Internet, it is required to develop a technique for overcoming noise, fading, and inter-symbol interference. As a part of the research to overcome the noise, the recent studies on error-correcting codes have been actively conducted as a method for improving the reliability of communication by efficiently restoring information distortion.

The Low Density Parity Check (LDPC) code, first introduced by Gallager in the 1960s, has long been forgotten due to the complexity of implementing it at the time. However, as the turbo code proposed by Berrou, Glavieux, and Thitimajshima in 1993 approached Shannon's channel capacity, it was repeated with much interpretation of the performance and characteristics of the turbo code. Much research has been conducted on channel coding based on iterative decoding and graphs. With this, the LDPC code was re-studied in the late 1990s, and decoding was performed by applying iterative decoding based on a sum-product algorithm on a Tanner graph corresponding to the LDPC code. It turns out that the performance is close to that of Shannon's channel capacity.

개 비트 혹은 심벌들로 구성되어 있는 정보어를 입력받아 LDPC 부호화를 하여

개 비트 혹은 심벌들로 구성되어 있는 부호어(codeword)를 생성한다. 이하 설명의 편의를 위해,

개 비트들을 포함하는 정보어를 입력받아

개 비트들로 구성되는 부호어를 가정한다. 즉,

개의 입력 비트들인 정보어

를 LDPC 부호화하면, 부호어

가 생성된다. 즉, 상기 부호어는 다수의 비트들로 구성되어 있는 비트열이며, 부호어 비트는 각각의 비트들을 의미한다. 또한 상기 정보어는 다수의 비트들로 구성되어 있는 비트열이며, 정보어 비트는 정보어를 구성하는 각각의 비트를 의미한다. 이때, 시스테메틱(systematic) 부호인 경우, 부호어

로 구성된다. 여기서,

는 패리티 비트들이고, 패리티 비트들의 개수

이다.The LDPC code is generally defined as a parity-check matrix and can be expressed using a bipartite graph collectively referred to as a turner graph. LDPC code is

LDPC encoding by receiving an information word consisting of four bits or symbols

Generates a codeword consisting of four bits or symbols. For convenience of description below,

Receives an information word containing

Assume a codeword consisting of four bits. In other words,

Information bits

Is a codeword

Is generated. That is, the codeword is a bit string consisting of a plurality of bits, and the codeword bit means each bit. The information word is a bit string consisting of a plurality of bits, and the information word bits mean each bit constituting the information word. In this case, in the case of a systematic code, a codeword

It consists of. here,

Are parity bits, and the number of parity bits

to be.

및

로 이미 결정된 상황에서 부호화가 수행된다. 그러므로,

보다 더 짧은 길이의 정보어가 입력되거나,

보다 더 짧은 길이의 부호어를 생성하고자 하는 경우, 적절한 방법이 필요하다. 예를 들어, 상기 주어진 정보어 비트수

보다 부호화기에 입력되어야 할 정보어 비트수

가 작을 경우, 송신단은 정보어에서

개 비트들을 단축(shortening)한다. 또한, 필요한 패리티의 길이

가 상기 패리티 길이

보다 작을 경우, 송신단은

개 비트들을 천공(puncturing)한다. 상기

는 실제 전송되는 사용되는 패리티의 길이로서, 입력되는 정보어의 길이

와 전송에 필요한 부호율에 따라 결정된다.In general, according to the LDPC code, the information word length and the code word length

And

The encoding is performed in a situation that has already been determined as. therefore,

Shorter information words are entered,

In order to generate codewords of shorter length, an appropriate method is needed. For example, the number of bits of information word given above

The number of bits of information words to be input to the encoder

Is small, the transmitting end

Shorten the dog bits. Also, the required length of parity

Is the parity length

If less, the transmitting end

Punch the dog bits. remind

Is the length of the parity to be actually transmitted, and the length of the information word to be input.

And the code rate required for transmission.

When some bits are shortened or punctured by the length of the information word and the parity, there may be a difference in performance depending on how the parity check matrix is designed. Therefore, in order to support variable length, there is a need for a method of designing the parity check matrix so as to optimize the performance of the system and a coding decoding method.

When the same signal is simultaneously transmitted by satellite and terrestrial wave, the receiver may improve reception performance when the two signals are combined and received. However, there is a limitation in a method of combining signals from a satellite wave transmission system and a terrestrial wave transmission system in a receiver in a system for encoding and decoding based on a parity check matrix designed to fit a fixed length as described above.

Accordingly, there is a need for a method of designing a parity check matrix and a coded decoding method for receiving the same signal transmitted from two different systems.

An object of the present invention is to provide a method and apparatus for transmitting and receiving variable length data in a wireless communication system.

Another object of the present invention is to provide a method and apparatus for improving reception performance when simultaneously transmitting satellite signals and terrestrial signals in the same signal in a wireless communication system.

According to a first aspect of the present invention for achieving the above objects, in a method for data transmission in a system, a parity check matrix of one of a plurality of parity check matrices is selected according to an information word length or a given parity bit size. And encoding the data by using the selected parity check matrix, and transmitting the encoded data.

According to a second aspect of the present invention for achieving the above objects, in a method for receiving data in a system, one of the plurality of parity check matrices is selected according to an information word length or a given parity bit size. And decoding the received data by using the selected parity check matrix.

According to a third aspect of the present invention for achieving the above object, in a method for receiving data in a broadcast system, receiving a satellite broadcast signal and a terrestrial broadcast signal, and receiving the satellite broadcast signal and the terrestrial broadcast signal And a second parity check matrix used in the satellite broadcast signal based on a first parity check matrix used for the terrestrial broadcast signal when combining the satellite broadcast signal and the terrestrial broadcast signal. And a step of decoding the broadcast signal using the second parity check matrix.

According to a fourth aspect of the present invention for achieving the above objects, in an apparatus for data transmission in a system, a parity check matrix of one of a plurality of parity check matrices is selected according to an information word length or a given parity bit size. And a parity check matrix extracting unit, an encoder for encoding data using the selected parity check matrix, and a transmitter for transmitting the encoded data.

According to a fifth aspect of the present invention for achieving the above objects, in an apparatus for receiving data in a system, a parity check matrix of one of a plurality of parity check matrices is selected according to an information word length or a given parity bit size. And a decoder for decoding the received data by using the parity check matrix extracting unit and the selected parity check matrix.

According to a sixth aspect of the present invention for achieving the above objects, there is provided an apparatus for receiving data in a broadcast system, comprising: a receiver for receiving a satellite broadcast signal and a terrestrial broadcast signal, and receiving the satellite broadcast signal and the terrestrial broadcast signal. Determining whether to combine, and when combining the satellite broadcast signal and the terrestrial broadcast signal, determining a second parity check matrix used in the satellite broadcast signal based on a first parity check matrix used for the terrestrial broadcast signal. And a control unit and a decoder for decoding the broadcast signal using the second parity check matrix.

As described above, by determining the extended parity check matrix from the parent matrix without additional parity, there is an advantage that data of variable length can be transmitted and received. In addition, it is possible to improve reception performance in a broadcast system that simultaneously transmits satellite signals and terrestrial signals.

1 is an example of the parity check matrix H1 of the LDPC code consisting of four rows and eight columns.
2 illustrates a Tanner graph.
3 is an example parity check matrix according to an embodiment of the present invention;
4 is an example of an additional parity check matrix of variable length based on a matrix according to an embodiment of the present invention;
5 is an example of an additional parity check matrix of variable length based on a parent matrix according to another embodiment of the present invention;
6 is an example of a parity check matrix according to another embodiment of the present invention;
7 is a flowchart for designing an additional parity check matrix of variable length based on a matrix according to an embodiment of the present invention.
8 is an example of a parity check matrix according to an embodiment of the present invention.
9 is an example of a parity check matrix according to another embodiment of the present invention;
10 is an example of a parity check matrix according to another embodiment of the present invention;
11 is an example of a parity check matrix according to another embodiment of the present invention;
12 is a block diagram of a transmitter in a wireless communication system according to a first embodiment of the present invention.
FIG. 13 is a flowchart illustrating selecting a parity check matrix for data transmission according to the first embodiment of the present invention.
14 is a flowchart illustrating selecting a parity check matrix for data transmission according to a second embodiment of the present invention.
FIG. 15 is a block diagram of a broadcast transmission device block in a broadcast system using a terrestrial broadcast system and a satellite broadcast system according to a second embodiment of the present invention.
16 is a block diagram of a broadcast receiving device block in a broadcast system using both a terrestrial broadcast system and a satellite broadcast system according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In the following description of the present invention, detailed descriptions of related well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention. The following terms are defined in consideration of the functions of the present invention, and these may be changed according to the intention of the user, the operator, or the like. Therefore, the definition should be based on the contents throughout this specification.

Hereinafter, the present invention will be described with respect to a data transmission and reception method and apparatus in a wireless communication system.

Hereinafter, the present invention uses terms and names defined in Digital Video Broadcasting the 2nd Generation Terrestrial (DVB-T2) system and Digital Video Broadcasting Next Genration Handheld (DVB-NGH) system, which are one of the European digital broadcasting standards. do. However, the present invention is not limited to the above terms and names, and may be equally applied to other systems.

Hereinafter, a method of designing a general parity check matrix will be described based on a graph representation method of the LDPC code with reference to FIGS. 1 and 2.

1 is an example of the parity check matrix H ₁ of the LDPC code consisting of four rows and eight columns.

Referring to FIG. 1, since the parity check matrix H ₁ has 8 columns, a parity check matrix H ₁ generates a codeword having a length of 8, and the code generated through H ₁ represents an LDPC code, and each column is encoded. Corresponds to 8 bits.

2 illustrates a Tanner graph.

Referring to FIG. 2, FIG. 2 is a Tanner graph corresponding to H ₁ of FIG. 1.

The Tanner graph of the LDPC code includes eight variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214), x ₈ (216) and four check nodes (218, 220, 222, 224). Here, the i th column and the j th row of the parity check matrix H ₁ of the LDPC code correspond to the variable nodes x _i and j th check nodes, respectively. In addition, the meaning of a value of 1, that is, a non-zero value of a point where the jth column and the jth row of the parity check matrix H ₁ of the LDPC code intersect, is the variable node x _i on the Tanner graph as shown in FIG. It means that there is an edge connecting the j th test node.

In the Tanner graph of the LDPC code, the degree of the variable node and the check node means the number of line segments connected to each node, which is determined in the column or row corresponding to the node in the parity check matrix of the LDPC code. It is equal to the number of nonzero entries. For example, in FIG. 2, the variable nodes x ₁ 202, x ₂ 204, x ₃ 206, x ₄ 208, x ₅ 210, x ₆ 212, and x ₇ ( 214, and the order of x ₈ (216) is 4, 3, 3, 3, 2, 2, 2, 2, respectively, in order, and the order of test nodes 218, 220, 222, and 224, respectively, in order. 6, 5, 5, 5. In addition, the number of non-zero elements in each column of the parity check matrix H ₁ of FIG. 1 corresponding to the variable nodes of FIG. 2 is equal to the above-described orders 4, 3, 3, 3, 2, 2, and 2. , The same as 2, and the number of nonzero elements in each row of the parity check matrix H ₁ of FIG. 1 corresponding to the check nodes of FIG. 2 is the above-described orders 6, 5, 5, 5 In order.

On the other hand, there is a difference in encoding / decoding performance of the LDPC code based on the parity check matrix due to the distribution of the orders. The order distribution is an order distribution of x columns, and thus, an optimal order distribution can be obtained for a (N, K) code given by a density evolution method. N means codeword length, and K means information word length. The density evolution method is a well known method so as not to be described in detail in the present invention. In addition, the encoding / decoding performance also differs due to the cycle characteristics between the variable nodes on the bipartite graph of FIG. 2. The cycle characteristic means a number of times of returning from the given variable node to the check node back to the variable node. In general, the encoding / decoding performance based on the parity check matrix corresponding to the bipartite graph having many short cycle structures is not good. Therefore, in order to improve LDPC encoding / decoding performance, the optimal order distribution and cycle characteristics should be considered.

Hereinafter, in order to support a variable length, a method and a coded decoding method of designing the parity check matrix to optimize the performance of the system will be described.

The present invention considers an example of a parity check matrix in which a parity check matrix having a structure as shown in FIGS. 3 to 5 supports a variable length.

3 shows a mother matrix (or referred to as a first parity check matrix) of the present invention. Here, the mother matrix is divided into a matrix H ₀ 301 of the information word part and a matrix P ₀ 302 of the parity part.

The (say N or _parity1) Fig N _parity generated on the basis of the mother matrix of 3 more than the number of parity bits N + N _{parity1 parity2} If two parity bits are needed, a second parity check matrix is designed by adding H ₁ 404, P _{1 , 0} 405, P _{0 , 1} 403, P _{1 , 1} 406 as shown in FIG. 4. can do. That is, the second parity check matrix may include submatrices H ₀ 401, H ₁ 404 of the information word part, and partial matrices P ₀ 402, P _{1 , 0} 405 of the first parity part. The partial matrix P _{0 , 1} (403) + P _{1 , 1} (406) of the two parity parts is divided.

The H ₀ 401 of FIG. 4 is the same as the H ₀ 301 of FIG. 3. The P ₀ 402 of FIG. 4 is the same as the P ₀ 302 of FIG. 3. The matrix P _{0 , 1} 403 may be a zero matrix.

Generated based on the second parity check matrix, N + N _{parity1 parity2} that More number than the parity bits N _parity1 + N _parity2 + N _parity3 of when the parity bits are required, H _{2 (509)} and _{P 2, 0 (510) P} 2, 1 (511) as shown in Figure 5 P _2, A third parity check matrix may be designed by adding ₂ (512) P _{0 , 2} (507) P _{1 , 2} 508. That is, the third parity check matrix includes partial matrices H ₀ 501, H ₁ 504, H ₂ 509 and the first parity part partial matrix P ₀ 502, P _{1 , 0} of the information word part. 505, P _{2 , 0} 510 and the second parity part submatrices P _{0 , 1} 503, P _{1 , 1} 506, P _2,1 511 and the third parity part partial matrices P _0, is divided into _{2 (507), P 1,} 2 (508), P 2, 2 (512).

The H ₀ 501 of FIG. 5 is the same as the H ₀ 301 of FIG. 3 and the H ₀ 401 of FIG. 4. The P ₀ 502 of FIG. 5 is the same as the P ₀ 302 of FIG. 3 and the P ₀ 401 of FIG. 4. The H ₁ 504 of FIG. 5 is the same as the H ₁ 404 of FIG. 4. The P _{1 , 0} 505 of FIG. 5 is the same as the P _{1 , 0} 405 of FIG. 4. The P _{1 , 1} 506 of FIG. 5 is the same as the P _{1 , 1} 406 of FIG. 4. The P _{0 , 1} 503 of FIG. 5 is the same as the P _{0 , 1} 403 of FIG. 4.

The parity check matrix can be further extended by the above methods.

인 모행렬(mother matrix)에 행렬 H₁과 행렬 P_{1 ,0}, P_1,1+P_0,1을 덧붙임으로써 제2 패리티 검사 행렬을 사용하는 LDPC 부호의 부호율을

으로 낮추고, H₂와 행렬 P_{2 ,0}, P_{2 ,1}, P_{2 ,2}, P_0,2, P_{1 , 2}을 덧붙임으로써 제3 패리티 검사 행렬을 사용하는 LDPC 부호의 부호율을

으로 낮추는 구조를 갖는다. 상기 H_i와 P_i를 덧붙임으로써 더 낮은 부호율을 지원할 수 있으므로 다양한 부호율을 지원하는 패리티 검사 행렬을 설계할 수 있다.3 to 5, the parity check matrix of the present invention has a code rate

The matrix H ₁ and matrix P _{1 , 0} , Add P _1,1 + P _0,1 to find the code rate of the LDPC code using the second parity check matrix.

Lower the code rate of the LDPC code using the third parity check matrix by adding H ₂ and the matrix P _{2 , 0} , P _{2 , 1} , P _{2 , 2} , P _0,2 , P _{1 , 2}

It has a lowering structure. By adding the H _i and P _i can support a lower code rate, it is possible to design a parity check matrix that supports a variety of code rates.

Design rules of the first parity sub-matrix to the third parity sub-matrix are as follows.

Rule 1

In order to limit the increase in the decoding complexity of the code including the additional parity, the highest order of the columns is limited to D. That is, the number of '1's included in the corresponding column is limited to D.

Rule 2

The second parity check matrix is designed in consideration of the order and cycle characteristics of the first parity check matrix in order to gradually increase the additional parity. Thereafter, a third parity check matrix is designed in consideration of the order and cycle characteristics of the second parity check matrix. That is, the parity check matrix is optimized in consideration of the order and cycle characteristics of the parity check matrix before increasing.

Factors affecting the performance of the LDPC code are the distribution and cycle characteristics of the parity check matrix '1'. Therefore, an additional parity check matrix is designed in consideration of sequentially increasing the additional parity as in Rule 2.

Hereinafter, a method of designing a parity check matrix of the present invention based on the parity check matrix having the structure of FIG. 6 will be described in detail.

The parity check matrix illustrated in FIG. 6 is a systematic structure in which a codeword includes an information word as it is. Hereinafter, the present invention will be described based on the parity check matrix of FIG. 4, but the range to which the present invention is applicable is not limited to the parity check matrix as shown in FIG. 4.

은 LDPC 부호어의 길이이고,

은 정보어의 길이를 의미한다. 상기 부호어 또는 상기 정보어의 길이는 상기 부호어 또는 상기 정보어에 포함되는 비트들의 개수를 의미한다. M은 정보어에 대응되는 부분 행렬(610)에서 열의 패턴이 반복되는 간격이고,

는 상기 정보어에 대응되는 부분 행렬(610)에서 각 열이 쉬프트(shift)되는 크기로서, 정수 M 및

의 값은

이 성립하도록 결정된다. 이때,

도 정수가 된다. 상기 M 및 상기

의 구체적인 값은 부호어 길이와 부호율에 따라 달라질 수 있다.In FIG. 6,

Is the length of the LDPC codeword,

Is the length of the information word. The length of the codeword or information word refers to the number of bits included in the codeword or information word. M is the interval in which the pattern of the column is repeated in the partial matrix 610 corresponding to the information word,

Is the magnitude of each column shifted in the partial matrix 610 corresponding to the information word, integer M and

The value of

It is determined to hold. At this time,

Is also an integer. M and above

The specific value of may vary depending on the codeword length and the code rate.

개의 열(column)들을 포함하고, 상기 패리티에 대응되는 부분 행렬(620)은

개의 열들을 포함한다. 상기 패리티 검사 행렬의 행(row)의 개수는 상기 패리티에 대응되는 부분 행렬(320)의 열의 개수

와 동일하다.Referring to FIG. 6, the parity check matrix is divided into a partial matrix 610 corresponding to the information word and a partial matrix 620 corresponding to parity. The partial matrix 610 corresponding to the information word

Partial matrix 620 including two columns and corresponding to parity

Contains ten columns. The number of rows of the parity check matrix is the number of columns of the partial matrix 320 corresponding to the parity.

.

번째 열(column)부터

번째 열을 포함하는 상기 패리티에 대응되는 부분 행렬(620)에서. 무게-1(weight-1), 즉, 1 값을 가지는 원소들의 위치는 이중 대각(dual diagonal) 구조를 가진다. 따라서, 상기 패리티에 대응되는 부분 행렬(620)에 포함되는 열들 중, 상기

번째 열을 제외한 나머지 열들의 차수(degree)는 모두 2이며, 상기 번째 열의 차수는 1이다.Of the parity check matrix

From the first column

In the partial matrix 620 corresponding to the parity including the first column. Weight-1, that is, the position of elements having a value of 1 has a dual diagonal structure. Therefore, of the columns included in the partial matrix 620 corresponding to the parity, the

The order of the remaining columns except the first column is all 2, and the order of the first column is 1.

번째 열을 포함하는 부분 행렬의 구조는 다음과 같은 규칙에 따른다. 첫째, 패리티 검사 행렬에서 정보어에 대응되는

개의 열들은 M개씩 동일 그룹에 속하며, 총

개의 열 그룹(column group)들로 구분된다. 동일한 열 그룹 내에 속한 열들은 서로

만큼 쉬프트된 관계를 가진다. 둘째, i번째

열 그룹의 0 번째 열의 차수를

라 하고, 1이 있는 각 행(row)의 위치를

이라 하면, i번째 열 그룹 내의 j번째 열에서 무게-1이 위치한 행의 인덱스 는 하기 <수학식 1>과 같이 결정된다.Referring to FIG. 6, the partial matrix 610 corresponding to the information word in the parity check matrix, that is, from the 0th column

The structure of the partial matrix including the first column is as follows. First, corresponding to the information word in the parity check matrix

Columns belong to the same group of M items,

It is divided into column groups. Columns within the same column group are

Has a shifted relationship. Second, i

The order of the 0th column of the column group

The position of each row with 1

In this case, the index of the row where the weight-1 is located in the jth column in the ith column group is determined as in Equation 1 below.

는 i번째 열 그룹 내의 j번째 열에서 k번째 무게-1이 있는 행의 인덱스, 상기 은 LDPC 부호어의 길이, 상기

은 정보어의 길이, 상기

는 i번째 열 그룹의 0 번째 열의 차수, 상기 M은 하나의 열 그룹에 속하는 열(column) 개수를 의미한다.In Equation (1) above,

Is the index of the row with the k th weight-1 in the j th column in the i th column group, Is the length of the LDPC codeword,

Is the length of the information word,

Is the order of the 0 th column of the i th column group, and M is the number of columns belonging to one column group.

로 동일하다. 상기 규칙들에 따라 상기 패리티 검사 행렬에 대한 정보를 저장하고 있는 LDPC 부호는 다음과 같이 간략하게 표현될 수 있다.According to the above rules, the orders of the columns belonging to the i th column group are all

Same as According to the rules, the LDPC code that stores information about the parity check matrix may be briefly expressed as follows.

가 30,

가 15,

가 3인 경우, 3개의 열 그룹의 0번째 열에서 무게-1이 위치한 행의 위치 정보는 하기 <수학식 2>과 같은 수열들로 표현될 수 있다. 하기 <수학식 2>와 같은 수열들은 '무게-1 위치 수열(weight-1 position sequence)'이라 지칭될 수 있다.As a specific example,

30,

15,

Is 3, the position information of the row where the weight-1 is located in the 0th column of the 3 column group may be represented by the following sequence. Sequences such as Equation 2 may be referred to as a weight-1 position sequence.

는 i번째 열 그룹 내의 j번째 열에서 k번째 무게-1이 있는 행의 인덱스를 의미한다.In Equation 2,

Is the index of the row with the k th weight-1 in the j th column in the i th column group.

Weight-1 position sequences, such as Equation 3, representing the index of the row where 1 is positioned in the 0th column of each column group may be more simply expressed as shown in Table 1 below.

Column group index Order of the column group Index of row where 1 is located in column 0 of column group 0 4 1 2 8 10 One 3 0 9 13 2 2 0 14

<Table 1> shows the position of an element having a weight-1, that is, a value of 1 in the parity check matrix, and the i th weight-1 position sequence has weight-1 in the 0 th column belonging to the i th column group. It is represented by the indices of a row.

Hereinafter, a method of designing an additional parity check matrix by using the parity check matrix having the structure of FIG. 6 as a parent matrix (first parity check matrix) will be described in detail.

7 is a flowchart for designing an additional parity check matrix of variable length based on a parent matrix according to an embodiment of the present invention.

Referring to FIG. 7, the transmitter sets a matrix in step 700. For example, the parity check matrix having the structure of FIG. 6 may be used as the first parity check matrix. Further, for each of the plurality of code rates, the highest order, the highest order column group number, and the number of column groups of order x are determined.

For example, the number of columns of the column group having the structure of FIG. 6 is 72, the number of column groups of the information word part is 15, the length of the codeword is 4320, and the parity check matrix has a code rate of 1/4. For example, the number of the highest 13 orders of thermal groups and the number of 4 orders of thermal groups are shown in Table 2 below. The highest degree is the maximum number of '1's present in the columns of the parity check matrix, and the number of column groups of degree 4 is the number of column groups whose number of' 1's is 4 in the corresponding column of the column group. The column group relates to the information word part of the parity check matrix having the structure of FIG. 6, and thus, the parity part has a fixed form.

Code rate Number of column groups of degree 13 Number of column groups of degree 4 Noise threshold (dB) 1/4 3 12 -3.04

That is, the maximum number of '1' of the columns of the parity check matrix is 13, the number of column groups whose number of '1' of the columns of the parity check matrix is 13 is 3, and the number of '1' of the columns of the parity check matrix is 3. The number of column groups with 4 is 12.

The parity check matrix having a code rate of 1/4 in Table 2 may be expressed as shown in Table 3 below by the same method as that of Table 1 below.

Column group index Order of the column group Index of row where 1 is located in column 0 of column group 0 4 1343 1563 2745 3039 One 4 1020 1147 1792 2609 2 4 2273 2320 2774 2976 3 4 665 2539 2669 3010 4 4 581 1178 1922 2998 5 4 633 2559 2869 2907 6 4 876 1213 2191 2261 7 4 916 1217 1632 2798 8 4 500 992 1230 2630 9 4 1842 2038 2169 2312 10 4 595 679 1206 1486 11 4 1087 2681 2894 3123 12 13 73 185 355 1381 1672 1998 2406 2577 2600 2834 3084 3115 3150 13 13 22 65 390 1022 1046 1465 1498 1682 1879 2108 2164 2203 3106 14 13 127 213 714 816 1031 1456 1815 2097 2183 2404 2934 2999 3153

= (4320-1080)/72=45이므로, 두 번째 열(column)의 1이 있는 행(row) 인덱스는 1343+45=1388, 1563+45=1608, 2745+45=2790, 3039+45=3084이다.
The parity check matrix of Table 3 may be expressed as shown in FIG. 8. The parity check matrix of FIG. 8 represents a parity check matrix having the same shape as the parity check matrix of FIG. 6, and the parity part has a double diagonal structure. The information word parts indicate the order of each column group. As mentioned above, since the parity check matrix of Table 3 has the structure of FIG. 6, the row index of 1 in the first column is the row index of the row in the 0th column of the inverse group. The same values as the index are 1343, 1563, 2745, and 3039. 6 of the above

= (4320-1080) / 72 = 45, so the row index with 1 in the second column is 1343 + 45 = 1388, 1563 + 45 = 1608, 2745 + 45 = 2790, 3039 + 45 = 3084.

Then, the transmitter limits the highest order of the additional parity check matrix in step 702. That is, the number of '1's included in columns in the additional parity check matrix is limited.

According to the present invention, in the structure of FIG. 6, the parity check matrices of Table 3 are matrixed, the highest order of a column group is limited to 13 (that is, '1 present in the corresponding column of the column group). Is not more than 13), N _parity2 , N _parity3 , and N _parity4 are each set to 1440 columns.

Then, in step 704, the transmitter includes '1' included in the additional parity check matrix H ₁ , H ₂ , or H ₃ using a density evolution method based on the highest order of the limited additional parity check matrix. Determine the number of '. The parity parts of the second parity matrix, the third parity matrix, and the fourth parity matrix have a double diagonal structure to maintain the same shape as the first parity matrix.

That is, after considering all the "1" distributions to be included in the additional parity check matrix based on the highest order of the limited additional parity check matrix, the order distributions of H ₁ , H ₂ , and H ₃ are optimized in terms of noise threshold. In other words, within the highest order range of the limited additional parity check matrix, the order distribution of H ₁ , H ₂ , H ₃ having a high noise threshold among the order distributions of all H ₁ , H ₂ , H ₃ is selected. Here, in order to consider gradually increasing the additional parity according to the above <Rule 2> H ₁ → H ₂ → H ₃ Optimize sequentially.

Table 4 below shows optimized order distributions of H ₁ , H ₂ , and H ₃ based on the matrix of Table 3 above. At this time, the column groups having the highest order of the matrix and the column group of the order 4 are distinguished. The order and number of column groups located below the column groups having the highest order are shown in Table 4 below.

Parity Part of  Number of additional columns Under the highest-order column group Under group of columns of order 4 Degree 3 One 2 20 x 72 Column group Count 0 4 8 40 x 72 0 4 8 60 x 72 0 4 8

In the optimized order distribution of Table 4, the column groups added under the highest order column group are selected such that the order of the corresponding variable node is 13, and the column groups added under the column block having degree 4 are similar. The order of magnitude is chosen to continue to be added. As described above, by adding the partial matrix to the parity check matrix and generating and transmitting additional parity, the code gain is generated in terms of noise threshold compared with Table 2 above.

The number of '1's to be added to each corresponding column group (highest order column group, order 4 column group) is determined based on the density evolution method.

In step 706, the transmitter determines the position of '1' of the additional parity check matrix to have the minimum length of the cycle. That is, the cycle characteristics are also sequentially optimized when H _i is added to have excellent cycle characteristics. To optimize the cycle characteristics, first determine the exponent of the circulating permutation matrices to maximize the girth, which means the minimum length of the cycles in the parity check matrix, and after maximizing the gus, minimize the number of cycles corresponding to the gus do.

Based on the above-mentioned rules in order to add an additional parity bit N _parity2 = 1440 using the parity check matrix of FIG. 6, which can be expressed as shown in Table 3, as a matrix (or first parity check matrix) A second parity check matrix having the structure of FIG. 4 designed as described above will be described.

The second parity check matrix may be expressed as shown in FIG. 9. First, the first parity part and the second parity part of the parity check matrix have a double diagonal structure. The information word part is composed of two partial matrices H0 and H1 as shown in FIG. 4, and the partial matrix H0 is the same as the information word part of the parent matrix. I can express it.

The parity check matrix of FIG. 9 illustrates a second parity check matrix based on a parity check matrix having the same form as the parity check matrix of FIG. 6. The information word part indicates the order of each column group. As you can see, a column of order 0 is added below the column group of order 13. Further, under the column group of degree 4, there are column groups of degree 2 and column groups of degree 1.

만큼 쉬프트된 관계를 가진다. 상기 M은 열 그룹의 열의 개수로 상기 모행렬과 동일한 값을 갖도록 하나 변경 가능함은 당연하다. 둘째, H₁의 i번째

열 그룹의 0 번째 열의 차수를

라 하고, 1이 있는 각 행(row)의 위치를

이라 하면, i번째 열 그룹 내의 j번째 열에서 무게-1이 위치한 행의 인덱스는 하기 <수학식 3>과 같이 결정된다.The added column groups of the partial matrix H ₁ have the same shape as that of the column group of H ₀ , which is the partial matrix of the matrix described with reference to FIG. 6. That is, the columns that belong to the same column group are at each other at the position of the 0th column of the column group.

Has a shifted relationship. The M is the number of columns in the column group, but it can be changed to have the same value as the matrix. Second, the i th of H ₁

The order of the 0th column of the column group

The position of each row with 1

In this case, the index of the row where the weight-1 is located in the j th column in the i th column group is determined as in Equation 3 below.

A parity check matrix having a code rate of 1/4 in Table 3 may be expressed as 20 × 72 = N _parity2 = 1440 according to an embodiment of the present invention, as shown in Table 5 below.

Heat group Index of row where 1 is located in column 0 of column group index Degree H0 H1 0 6 1343 1563 2745 3039 3405 4360 One 6 1020 1147 1792 2609 3623 4348 2 6 2273 2320 2774 2976 3337 4426 3 6 665 2539 2669 3010 3694 4631 4 6 581 1178 1922 2998 3898 4613 5 6 633 2559 2869 2907 4015 4364 6 6 876 1213 2191 2261 3842 4379 7 6 916 1217 1632 2798 3487 3996 8 5 500 992 1230 2630 4609 9 5 1842 2038 2169 2312 4630 10 5 595 679 1206 1486 4112 11 5 1087 2681 2894 3123 4601 12 13 73 185 355 1381 1672 1998 2406 2577 2600 2834 3084 3115 3150 13 13 22 65 390 1022 1046 1465 1498 1682 1879 2108 2164 2203 3106 14 13 127 213 714 816 1031 1456 1815 2097 2183 2404 2934 2999 3153

As mentioned above, since the parity check matrix of Table 5 is an extended parity matrix in the structure of FIG. 6, the row index with 1 of the first column of the partial matrix H ₀ is the inverse group. 1343, 1563, 2745, and 3039 are the same values as the index of the row where 1 is located in the 0th column. The indices of the row 1 in the first column of the partial matrix H1 are 3405 and 4360.

= (4320-1080)/72=45이므로 부분 행렬 H0의 두 번째 열(column)의 1이 있는 행(row) 인덱스는, 1343+45=1388, 1563+45=1608, 2745+45=2790, 3039+45=3084이다. 또한

= (1440)/72=20이므로, 상기 부분 행렬 H₁의 두 번째 열(column)의 1이 있는 행(row) 인덱스는 상기 도 6의 3405+20=3425, 4360+20=4380이다. 이를 도 9에서 상세하게 도시 하였다.
6 of the above

= (4320-1080) / 72 = 45, so the row index with 1 in the second column of submatrix H0 is 1343 + 45 = 1388, 1563 + 45 = 1608, 2745 + 45 = 2790, 3039 + 45 = 3084. Also

= (1440) / 72 = 20, the row index with ₁ of the second column of the partial matrix H ₁ is 3405 + 20 = 3425, 4360 + 20 = 4380 of FIG. This is illustrated in detail in FIG. 9.

A parity check matrix having a code rate of 1/4 in Table 5 may be illustrated in FIG. 10 when the additional parity bit N _parity3 = 1440 according to an embodiment of the present invention. The first parity part, the second parity part, and the third parity part of FIG. 10 have a double diagonal structure. The information word part is composed of three partial matrices H ₀ , H ₁ , and H ₂ , and each of them is composed of a plurality of column groups. 10 shows the order of each column group.

만큼 쉬프트된 관계를 가진다. 상기 M은 열 그룹의 열의 개수로 상기 모행렬과 동일한 값을 갖도록 하나 변경 가능함은 당연하다. 둘째, H₂의 i번째

열 그룹의 0 번째 열의 차수를

라 하고, 1이 있는 각 행(row)의 위치를

이라 하면, i번째 열 그룹 내의 j번째 열에서 무게-1이 위치한 행의 인덱스는 하기 <수학식 4>과 같이 결정된다.The column groups of the added partial matrix H ₂ have the same shape as that of the column group of H ₀ , which is the partial matrix of the matrix described with reference to FIG. 6. That is, the columns that belong to the same column group are at each other at the position of the 0th column of the column group.

Has a shifted relationship. The M is the number of columns in the column group, but it can be changed to have the same value as the matrix. Second, the i th of H ₂

The order of the 0th column of the column group

The position of each row with 1

In this case, the index of the row where the weight-1 is located in the j th column in the i th column group is determined as in Equation 4 below.

An embodiment of the third parity check matrix is shown in Table 6 below based on Table 5.

Heat group Index of row where 1 is located in column 0 of column group index Degree H0 H1 H2 0 8 1343 1563 2745 3039 3405 4360 5080 5264 One 8 1020 1147 1792 2609 3623 4348 4728 4805 2 8 2273 2320 2774 2976 3337 4426 4974 5591 3 8 665 2539 2669 3010 3694 4631 4712 5758 4 7 581 1178 1922 2998 3898 4613 5706 5 7 633 2559 2869 2907 4015 4364 5882 6 7 876 1213 2191 2261 3842 4379 4876 7 7 916 1217 1632 2798 3487 3996 5890 8 7 500 992 1230 2630 4609 4757 5283 9 7 1842 2038 2169 2312 4630 5347 5981 10 7 595 679 1206 1486 4112 4749 5513 11 7 1087 2681 2894 3123 4601 5659 5735 12 13 73 185 355 1381 1672 1998 2406 2577 2600 2834 3084 3115 3150 13 13 22 65 390 1022 1046 1465 1498 1682 1879 2108 2164 2203 3106 14 13 127 213 714 816 1031 1456 1815 2097 2183 2404 2934 2999 3153

A parity check matrix having a code rate of 1/4 in Table 6 may be illustrated in FIG. 11 when the additional parity bit N _parity4 = 1440 according to an embodiment of the present invention. The first parity part, the second parity part, the third parity part, and the fourth parity part of FIG. 11 have a double diagonal structure. The information word part is composed of four partial matrices H ₀ , H ₁ , and H ₂ H ₃ , each of which consists of a plurality of column groups. 11 shows the order of each column group.

An embodiment of the fourth parity check matrix based on the <Table 6> is shown in the following <Table 7>.

Heat group Index of row where 1 is located in column 0 of column group index Degree H0 H1 H2 H3 0 8 1343 1563 2745 3039 3405 4360 5080 5264 6447 One 8 1020 1147 1792 2609 3623 4348 4728 4805 7321 2 8 2273 2320 2774 2976 3337 4426 4974 5591 6817 3 8 665 2539 2669 3010 3694 4631 4712 5758 6924 4 7 581 1178 1922 2998 3898 4613 5706 7073 7083 5 7 633 2559 2869 2907 4015 4364 5882 7526 7556 6 7 876 1213 2191 2261 3842 4379 4876 7455 7512 7 7 916 1217 1632 2798 3487 3996 5890 6228 6911 8 7 500 992 1230 2630 4609 4757 5283 6419 6714 9 7 1842 2038 2169 2312 4630 5347 5981 6518 7009 10 7 595 679 1206 1486 4112 4749 5513 6230 6705 11 7 1087 2681 2894 3123 4601 5659 5735 6302 7280 12 13 73 185 355 1381 1672 1998 2406 2577 2600 2834 3084 3115 3150 13 13 22 65 390 1022 1046 1465 1498 1682 1879 2108 2164 2203 3106 14 13 127 213 714 816 1031 1456 1815 2097 2183 2404 2934 2999 3153

It is well known that column groups of the information word part of the parity check matrix designed above can produce the same codeword set even if they are permutated in units of column groups.

Thereafter, the procedure of the present invention is terminated.

12 is a block diagram of a transmitter and a receiver in a wireless communication system according to a first embodiment of the present invention.

As shown in FIG. 12A, the transmitter includes a parity check matrix extractor 1200, a controller 1202, and an LDPC encoder 1204.

을 입력받아 패리티 검사 행렬

에 대해

를 만족하는 부호어

를 출력한다.The LDPC encoder 1204 performs LDPC encoding by using a first parity check matrix or a second parity check matrix provided from the parity check matrix extractor 1200. Here, LDPC encoding is input bits

Parity check matrix

About

Codeword that satisfies

.

The parity check matrix extractor 1200 may generate a second parity check matrix or store first and second parity check matrices through a first parity check matrix under the control of the controller 1202. A parity check matrix or a second parity check matrix is provided to the LDPC encoder 1204. The parity check matrix extractor 1200 may provide additional parity bits sequentially generated up to the Nth parity check matrix to the LDPC encoder 1204.

Although not shown, the transmitter includes a modulator for modulating the hatching bits provided from the LDPC encoder 1204, an RF transmitter for up-converting a baseband signal into a radio frequency signal and transmitting the frequency through an antenna. It may further include. In addition, although not shown in the figure, the LDPC encoder 1204 may include a perforator. The control unit 1202 informs whether the perforator is in use.

The controller 1202 controls the overall operation of the transmitter. In particular, in addition to the present invention, the controller 1202 selects a corresponding parity check matrix for LDPC encoding and provides the result to the parity check matrix extractor 1200.

In the parity check matrix selection method according to the first embodiment of the present invention, when the LDPC encoder 1204 is encoded, the parent matrix, the first parity check matrix, the second parity check matrix, or the first according to the length of the input information word. A parity check matrix can be selected and encoded. Hereinafter will be described in detail with reference to FIG.

As shown in FIG. 12B, the receiver includes a parity check matrix extractor 1220, a controller 1222, a demodulator 1224, and an LDPC decoder 1226. Although not shown, the receiver further includes a functional block for frequency downconverting the RF signal received from the antenna into a baseband signal.

The LDPC decoder 1226 performs decoding corresponding to the encoding performed by the LDPC encoder 1204 based on the first parity check matrix or the second parity check matrix provided from the parity check matrix extractor 1220. do. Although not shown in the figure, the decoder 1226 may include a function corresponding to the perforator of FIG. The control unit 1222 tells whether or not to use the perforator.

The parity check matrix extractor 1220 may generate a second parity check matrix or store first and second parity check matrices through a first parity check matrix, and store the first parity check matrix or the second parity check matrix. To the LDPC decoder 1226. The parity check matrix extractor 1220 may provide the LDPC decoder 1226 with additional parity bits sequentially generated up to an Nth parity check matrix. When the parity check matrix extractor 1220 provides the LDPC decoder 1226 with the first parity check matrix and the generated additional parity bits to the LDPC decoder 1226 at the same time, the LDPC decoder 1226 and the additional parity Decoding is performed using the bits and the parity check matrix.

The controller 1222 controls the overall operation of the receiver. In particular, in addition to the present invention, the controller 1222 selects a corresponding parity check matrix for LDPC encoding and provides the result to the parity check matrix extractor 1220.

FIG. 13 is a flowchart illustrating selecting a parity check matrix for data transmission according to the first embodiment of the present invention.

Referring to FIG. 13, and performs the control unit (1202, 1222) is LDPC encoded based on the mother matrix proceeds to step 1202 if K _S <K _th Compare K _S and K _th in step 1300.

On the other hand, the controller 1202, 1222 proceeds to step 1304 if K _S ≥ K _th and sets i = 2.

와

를 비교하여,

이면 1308단계로 진행하여, i번째 패리티 검사 행렬을 기반으로 LDPC 부호화를 수행한다.Subsequently, the controllers 1202 and 1222 proceed to step 1306.

Wow

By comparing

In step 1308, the LDPC encoding is performed based on the i th parity check matrix.

이면 1310단계로 진행하여, i를 1씩 증가시킨다.On the other hand, the control unit 1202 and 1222

If the process proceeds to step 1310, i is increased by one.

Thereafter, the controllers 1202 and 1222 proceed to step 1306 if i <L, and the controllers 1202 and 1222 terminate the procedure of the present invention if i≥L.

)과 입력되는 정보어의 길이(

)를 비교하여 패리티 검사 행렬을 선택한다.That is, the controllers 1202 and 1222 may select a threshold value for selecting the parity check matrix.

) And the length of the information word entered (

) To select the parity check matrix.

를 정의한다.That is, to distinguish the length of the information word,

.

를 결정하는 방법은 시스템마다 다를 수 있다. 그 일례로 아래와 같이 패리티 비트의 개수를 계산하여

를 결정할 수 있다. 천공하는 비트의 개수는 이하 <수학식 5>와 같이 구할 수 있다.

The method of determining this may vary from system to system. For example, calculate the number of parity bits as follows

Can be determined. The number of bits to be punctured can be obtained as in Equation 5 below.

The A and B values determine the number of bits to be punctured by arbitrary constant values.

Assuming that the parity parts of the parity check matrix exist from the first parity part to the m th parity part, the number of parity bits transmitted without being punctured may be obtained as in Equation 5 below.

가

이 되는

값이

이고, 상기

가

이

되는 값이

이다.
remind

end

Being

The value is

And

end

this

Value is

to be.

As another method of parity check matrix selection of the first embodiment of the present invention, a parity check matrix may be determined based on given parity bits. This will be described with reference to FIG. 7.

14 is a flowchart illustrating selecting a parity check matrix for data transmission according to a second embodiment of the present invention.

와 m를 비교하여

이면 1402단계로 진행하여 모행렬을 기반으로 LDPC 부호화를 수행한다.Referring to FIG. 14, the controllers 1202 and 1222 in step 1400.

By comparing

In step 1402, the LDPC encoding is performed based on the parent matrix.

이면 1404단계로 진행하여 i=2로 설정한다.On the other hand, the control unit 1202 and 1222

If so, go to step 1404 and set i = 2.

와

를 비교하여,

이면 1408단계로 진행하여, i번째 패리티 검사 행렬을 기반으로 LDPC 부호화를 수행한다.Subsequently, the controllers 1202 and 1222 proceed to step 1406.

Wow

By comparing

In step 1408, the LDPC encoding is performed based on the i th parity check matrix.

이면 1410단계로 진행하여, i를 1씩 증가시킨다.On the other hand, the control unit 1202 and 1222

If the process proceeds to step 1410, i is increased by one.

Thereafter, the controllers 1202 and 1222 proceed to step 1406 if i <L, and the controllers 1202 and 1222 end if i≥L.

)과 입력되는 패리티 비트 길이(

)를 비교하여 패리티 검사 행렬을 선택한다.
That is, the controllers 1202 and 1222 may select a threshold value for selecting the parity check matrix.

) And the input parity bit length (

) To select the parity check matrix.

FIG. 15 is a block diagram of a broadcast transmission device block in a broadcast system using a terrestrial broadcast system and a satellite broadcast system according to a second embodiment of the present invention.

As shown in FIG. 15, the broadcasting apparatus includes a controller 1500, a first transmitter 1510, and a second transmitter 1520.

 The first transmitter 1510 includes a first LDPC encoder 1511 and a first modulator 1512 for transmitting a satellite broadcast signal, and the second transmitter 1520 is for transmitting a terrestrial broadcast signal. A second LDPC coder 1521 and a second modulator 1522 are included.

 The first LDPC encoder 1511 of the first transmitter 1510 performs LDPC encoding on an information word by using a parity check matrix extended by using a parity check matrix used for terrestrial waves as a matrix. That is, the first LDPC coder 1511 multiplies the extended parity check matrix to determine an LDPC codeword that becomes zero. In addition, the first modulator 1512 of the first transmitter 1510 modulates the codeword from the first LDPC coder 1511.

 The second transmitter 1520 performs the LDPC encoding on the information word by using the parity check matrix (or matrix) used by the second LDPC encoder 1521 in terrestrial waves. That is, the second LDPC coder 1521 multiplies the extended parity check matrix to determine an LDPC codeword that becomes zero. The second modulator 1522 modulates a code word from the second LDPC coder 1521.

The controller 1500 performs overall control on the broadcast transmission device. In particular, in addition to the present invention, an extended parity check matrix for satellite broadcasting is selected and provided to the first transmitter 1510, and a parity check matrix for satellite broadcasting (ie, a matrix without additional parity) is selected. Provided to the second transmitter 1520. In this case, the extended parity check matrix provided to the first transmitter 1510 is generated by extending from a matrix provided to the second transmitter 1520 (see the flowchart of FIG. 4).

Although the first transmitter 810 and the second transmitter 820 are shown in one broadcast transmission device block for convenience of description, the first transmitter 810 and the second transmitter 820 are separate. It may be configured as a broadcast transmission device.

As described above, in a system that simultaneously broadcasts a satellite system and a terrestrial system, the terminal (or broadcast receiving apparatus) may receive two signals independently, or may combine the two signals. . When the two signals are combined, the parity check matrix used in the satellite system uses a parity check matrix extended by using a parity check matrix used for terrestrial waves as a matrix.

16 is a block diagram of a broadcast receiving device block in a broadcast system using both a terrestrial broadcast system and a satellite broadcast system according to a second embodiment of the present invention.

Referring to FIG. 16, the broadcast receiving apparatus determines whether to combine the satellite broadcast signal and the terrestrial broadcast signal in step 1600. That is, even if the satellite reception signal and the terrestrial broadcast signal are not combined, if the broadcast reception device receives a good satellite broadcast signal or a good terrestrial broadcast signal, the broadcast receiving device proceeds to step 1602 to select a parity check matrix according to a code rate. Decode the broadcast signal.

On the other hand, if it is impossible to watch a good satellite broadcast signal or a good terrestrial broadcast signal, the process proceeds to step 1604 to determine the terrestrial code rate or code length, and in step 1606 the parity check matrix extended by using the parity check matrix used for terrestrial waves as a matrix. After selecting, decode the satellite broadcast signal.

Thereafter, the procedure of the present invention is terminated.

As described above, the parity check matrix used in the LDPC coder of the satellite system and the parity check matrix used in the LDPC coder of the terrestrial system are illustrated.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by the equivalents of the claims.

1202, 1222: controller, 1200, 1220: parity check matrix extraction unit, LDPC encoder: 1204.

Claims (30)

A method for data transmission in a system,
Selecting one parity check matrix among a plurality of parity check matrices according to the information word length or a given parity bit size;
Encoding data using the selected parity check matrix;
Transmitting the encoded data.
The method of claim 1,
The process of selecting the parity check matrix,
Sequentially comparing the information word length or the given parity bit size with a plurality of threshold values;
And determining the parity check matrix according to the comparison result.
The method of claim 1,
The plurality of parity check matrices include a matrix having no additional parity bits, extended parity check matrices in which an information word submatrix and a parity submatrix are added to the parent matrix, or an information word subparity and a parity submatrix in the parity check matrix. And extended parity check matrices added.
The method of claim 1,
Determining the plurality of parity check matrices;
The process of determining the plurality of parity check matrix,
Setting up a matrix with no additional parity bits,
Determining a highest order for an extended parity check matrix in which at least one information word submatrix and a parity submatrix are added to the mother matrix;
Determining a number of 1's to be included in the information word sub-matrix to be added by using a density evloution method based on the highest order;
Determining a position of 1 of the information word sub-matrix to be added such that the extended parity check matrix has a minimum length of cycles.
The method of claim 1,
Determining the plurality of parity check matrices;
The process of determining the plurality of parity check matrix,
determining a highest order for the m th parity check matrix in which at least one information word submatrix and the parity submatrix are added to the m-1 th parity check matrix, wherein m = 1, 2, ..., An integer that is M.
Determining a number of 1's to be included in the information word sub-matrix to be added by using a density evloution method based on the highest order;
Determining a position of 1 of the information word sub-matrix to be added such that the extended parity check matrix has a minimum length of cycles.
The method according to claim 4 or 6,
Wherein the parity submatrices of some of the at least one parity submatrices are of a dual diagonal structure.
A method for receiving data in a system,
Selecting one parity check matrix among a plurality of parity check matrices according to an information word length or a given parity bit size;
And decoding the received data by using the selected parity check matrix.
8. The method of claim 7,
The process of selecting the parity check matrix,
Sequentially comparing the information word length or the given parity bit size with a plurality of threshold values;
And determining the parity check matrix according to the comparison result.
8. The method of claim 7,
The plurality of parity check matrices include a matrix having no additional parity bits, extended parity check matrices in which an information word submatrix and a parity submatrix are added to the parent matrix, or an information word subparity and a parity submatrix in the parity check matrix. And extended parity check matrices added.
8. The method of claim 7,
Determining the plurality of parity check matrices;
The process of determining the plurality of parity check matrix,
Setting up a matrix with no additional parity bits,
Determining a highest order for an extended parity check matrix in which at least one information word submatrix and a parity submatrix are added to the mother matrix;
Determining a number of 1's to be included in the information word sub-matrix to be added by using a density evloution method based on the highest order;
Determining a position of 1 of the information word sub-matrix to be added such that the extended parity check matrix has a minimum length of cycles.
8. The method of claim 7,
Determining the plurality of parity check matrices;
The process of determining the plurality of parity check matrix,
determining a highest order for the m th parity check matrix in which at least one information word submatrix and the parity submatrix are added to the m-1 th parity check matrix, wherein m = 1, 2, ..., An integer that is M.
Determining a number of 1's to be included in the information word sub-matrix to be added by using a density evloution method based on the highest order;
Determining a position of 1 of the information word sub-matrix to be added such that the extended parity check matrix has a minimum length of cycles.
The method according to claim 10 or 11,
Wherein the parity submatrices of some of the at least one parity submatrices are of a dual diagonal structure.
In the method for receiving data in a broadcast system,
Receiving a satellite broadcast signal and a terrestrial broadcast signal;
Determining whether to combine the satellite broadcast signal and the terrestrial broadcast signal;
Determining a second parity check matrix used in the satellite broadcast signal based on a first parity check matrix used for the terrestrial broadcast signal when the satellite broadcast signal and the terrestrial broadcast signal are combined;
And decoding a broadcast signal using the second parity check matrix.
8. The method of claim 7,
Determining a second parity check matrix used in the satellite broadcast signal based on the first parity check matrix used for the terrestrial broadcast signal,
Determining a highest order for a second parity check matrix in which at least one information word submatrix and a parity submatrix are added to the first parity check matrix, wherein m = 1, 2, ..., M Integer.
Determining a number of 1's to be included in the information word sub-matrix to be added by using a density evloution method based on the highest order;
Determining a position of 1 of the information word sub-matrix to be added such that the extended parity check matrix has a minimum length of cycles.
15. The method of claim 14,
Wherein the parity submatrices of some of the at least one parity submatrices are of a dual diagonal structure.
An apparatus for transmitting data in a system, the apparatus comprising:
A parity check matrix extracting unit for selecting one parity check matrix among a plurality of parity check matrices according to the information word length or a given parity bit size;
An encoder for encoding data using the selected parity check matrix;
And a transmitter for transmitting the encoded data.
17. The method of claim 16,
The parity check matrix extraction unit,
Sequentially comparing the information word length or the given parity bit size with a plurality of thresholds,
And determine the parity check matrix according to the comparison result.
17. The method of claim 16,
The plurality of parity check matrices include a matrix having no additional parity bits, extended parity check matrices in which an information word submatrix and a parity submatrix are added to the parent matrix, or an information word subparity and a parity submatrix in the parity check matrix. And extended parity check matrices added.
17. The method of claim 16,
And a controller configured to determine the plurality of parity check matrices.
The control unit,
Set a matrix with no additional parity bits,
Determine a highest order for the extended parity check matrix in which at least one information word submatrix and a parity submatrix are added to the mother matrix;
Determining the number of 1s to be included in the information word sub-matrix to be added, using a density evloution method based on the highest order,
And determine the position of one of the information word submatrices to be added such that the extended parity check matrix has a minimum length of cycles.
17. The method of claim 16,
And a controller configured to determine the plurality of parity check matrices.
The control unit,
Determine the highest order for the m th parity check matrix with at least one information word submatrix and a parity submatrix added to the m-1 th parity check matrix, where m = 1, 2, ..., M Integer.
Determining the number of 1s to be included in the information word sub-matrix to be added, using a density evloution method based on the highest order,
And determine the position of one of the information word submatrices to be added such that the extended parity check matrix has a minimum length of cycles.
21. The method according to claim 19 or 20,
And wherein some of the at least one parity submatrices have a dual diagonal structure.
An apparatus for receiving data in a system,
A parity check matrix extracting unit for selecting one parity check matrix among a plurality of parity check matrices according to the information word length or a given parity bit size;
And a decoder for decoding received data using the selected parity check matrix.
23. The method of claim 22,
The parity check matrix extraction unit,
Sequentially comparing the information word length or the given parity bit size with a plurality of thresholds,
And determine the parity check matrix according to the comparison result.
23. The method of claim 22,
The plurality of parity check matrices include a matrix having no additional parity bits, extended parity check matrices in which an information word submatrix and a parity submatrix are added to the parent matrix, or an information word subparity and a parity submatrix in the parity check matrix. And extended parity check matrices added.
23. The method of claim 22,
And a controller configured to determine the plurality of parity check matrices.
The control unit,
Set a matrix with no additional parity bits,
Determine a highest order for the extended parity check matrix in which at least one information word submatrix and a parity submatrix are added to the mother matrix;
Determining the number of 1s to be included in the information word sub-matrix to be added, using a density evloution method based on the highest order,
And determine the position of one of the information word submatrices to be added such that the extended parity check matrix has a minimum length of cycles.
8. The method of claim 7,
And a controller configured to determine the plurality of parity check matrices.
Determine the plurality of parity check matrices,
Determine the highest order for the m th parity check matrix with at least one information word submatrix and a parity submatrix added to the m-1 th parity check matrix, where m = 1, 2, ..., M Integer.
Determining the number of 1s to be included in the information word sub-matrix to be added, using a density evloution method based on the highest order,
And determine the position of one of the information word submatrices to be added such that the extended parity check matrix has a minimum length of cycles.
27. The method of claim 25 or 26,
And wherein some of the at least one parity submatrices have a dual diagonal structure.
An apparatus for receiving data in a broadcasting system,
A receiver for receiving satellite broadcast signals and terrestrial broadcast signals;
Determine whether to combine the satellite broadcast signal and the terrestrial broadcast signal;
A control unit for determining a second parity check matrix used in the satellite broadcast signal based on a first parity check matrix used for the terrestrial broadcast signal when the satellite broadcast signal and the terrestrial broadcast signal are combined;
And a decoder for decoding a broadcast signal using the second parity check matrix.
The method of claim 28,
The control unit,
Determining a second parity check matrix used in the satellite broadcast signal based on a first parity check matrix used in the terrestrial broadcast signal,
Determine the highest order for the second parity check matrix with at least one information word submatrix and the parity submatrix added to the first parity check matrix, where m = 1, 2, ..., M.
Determining the number of 1s to be included in the information word sub-matrix to be added, using a density evloution method based on the highest order,
And determine the position of one of the information word submatrices to be added such that the extended parity check matrix has a minimum length of cycles.
30. The method of claim 29,
And wherein some of the at least one parity submatrices have a dual diagonal structure.

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