KR20120119323A - Semiconductor memory device and method of operating thereof - Google Patents

Abstract

PURPOSE: A semiconductor memory device and an operating method thereof are provided to improve an operation speed by shortening data input time. CONSTITUTION: A plurality of latch circuits are respectively connected to sensing nodes and latch data. A plurality of bit line connecting circuits transmit the latched data to bit lines of a memory block(110MB). A column selecting circuit(160) simultaneously transmits data from the outside to two or more sensing nodes in response to a column selection signal. A control circuit(120) controls the latch circuits by outputting control signals. [Reference numerals] (120) Control circuit; (130) Voltage generating circuit; (140) Row decoder; (160) Column selecting circuit; (170) Input and output circuit; (180) Pass/fail check circuit; (AA) Column address generating unit

Description

Semiconductor memory device and method of operation thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of operating the same, and more particularly, to a semiconductor memory device for improving an operating speed and a method of operating the same.

Fast input of large amounts of data from the outside into the semiconductor memory device can improve the overall operation speed.

Referring to the case of a NAND flash memory device as an example, the data input / output circuit sequentially transfers data input from the outside to the page buffers, and the page buffers latch the transferred data. Thereafter, a plurality of data latched in the page buffers are stored in the memory cells at one time by a program operation.

Meanwhile, as the number of bit lines of a memory block increases, the number of page buffers increases and the amount of data stored in memory cells at one time increases. In addition, as the amount of data stored at one time increases, the overall data storage speed increases. However, the time required for much data to enter the page buffers increases.

An embodiment of the present invention provides a semiconductor memory device and a method of operating the same which can improve the overall operation speed by shortening the input time of data for storing in the memory cells.

In an embodiment, a semiconductor memory device may include a plurality of latch circuits respectively connected to sensing nodes and latching data, and for transferring data latched to the latch circuits to bit lines of a memory block. A plurality of bit line connection circuits configured to respectively connect the sensing nodes and the bit lines in response to the bit line connection signal, and simultaneously transmit data received from the outside to at least two or more sensing nodes in response to the column selection signal. A column select circuit, and a control circuit that controls the latch circuits to latch the data transferred from the column select circuit to the sensing nodes.

A method of operating a semiconductor memory device according to an exemplary embodiment of the present invention includes inputting data for latching to latch circuits connected to sensing nodes, and a column selection signal for selecting at least two latch circuits among the latch circuits. Generating the data; simultaneously transmitting the data received from the outside to the at least two sensing nodes in response to the column selection signal, and storing the data transferred to the sensing nodes in the latch circuits.

The embodiment of the present invention can improve the overall operation speed by shortening the input time of data for storing in the memory cells.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating the memory block shown in FIG. 1.
FIG. 3 is a circuit diagram for describing the page buffer shown in FIG. 1.
FIG. 4 is a circuit diagram for describing a column selection circuit and an input / output circuit shown in FIG. 1.
5 is a waveform diagram illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

1 is a circuit diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention. FIG. 2 is a circuit diagram illustrating the memory block shown in FIG. 1.

In an exemplary embodiment, a semiconductor memory device may include a memory array 110 including a plurality of memory blocks 110MB, a program operation, a read operation, and a test of memory cells included in a selected page of the memory cell block 110MB. Operating circuits 130, 140, 150, 160, 170, 180 configured to perform an operation, and control circuits 120 configured to control the operating circuits 130, 140, 150, 160, 170, 180. In the case of a NAND flash memory device, the operation circuit includes a voltage supply circuit 130, 140, a page buffer group 150, a column select circuit 160, an input / output circuit 170, and a face / fail check circuit 180. .

The memory array 110 includes a plurality of memory blocks 110MB.

Referring to FIG. 2, each memory block includes a plurality of strings STe1 to STek and STo1 to STok connected between the bit lines BLe1 to BLek and BLo1 to BLok and the common source line CSL. That is, the strings ST1 to ST2k are respectively connected to the corresponding bit lines BL1 to BL2k and commonly connected to the common source line CSL. Each string STe1 includes a source select transistor SST having a source connected to the common source line CSL, a plurality of memory cells C0e1 to Cne1, and a drain select transistor (drain) connected to the bit line BLe1 DST). The memory cells C0e1 to Cne1 are connected in series between the select transistors SST and DST. The gates of the source select transistors SST are connected to the source select line SSL and the gates of the memory cells C0e1 to Cne1 are connected to the word lines WL0 to WLn respectively and the gate of the drain select transistor DST Is connected to a drain select line (DSL).

In the NAND flash memory device, memory cells included in a memory cell block may be divided into physical page units or logical page units. For example, memory cells C0e1 to C0ek and C0ek to C0ok connected to one word line (eg, WL0) constitute one physical page PAGE0. In addition, even-numbered memory cells C0e1 to C0ek connected to one word line (eg, WL0) constitute one even physical page, and odd-numbered memory cells C0ek to C0ok constitute one odd physical page. Can be. These pages (or even pages and odd pages) are the basic unit of program operation or read operation.

Referring back to FIGS. 1 and 2, the control circuit 120 may perform an internal command to perform a program operation, a read operation, or a test operation in response to a command signal CMD input through the input / output circuit 170 from the outside. The signal CMDi is output, and PB control signals PB_SIGNALS for controlling the page buffers PB1 to PBk included in the page buffer group 150 are output according to the type of operation. The operation in which the control circuit 120 controls the page buffer group 150 will be described later. The control circuit 120 also outputs the row address signal RADD and the column address signal CADD in response to the address signal ADD input from the outside through the input / output circuit 170. [

In particular, the column address generation unit 120CADD generates a column selection signal CS [k: 1] corresponding to the column address signal CADD in order to sequentially select the page buffers PB1 to PBk one by one. A column select signal CS [k: 1] may be generated such that two or more page buffers are selected at the same time in order to simultaneously transmit the same data to the at least two or more page buffers according to the signal CMD. For example, the column address generator 120CADD may select the column selection signal CS [such that the page buffers PB1 to PBk are sequentially connected to the column selection circuit 160 one by one in a general operation mode such as a program operation or a read operation. k: 1]), and in the test operation mode, at least two or more page buffers are simultaneously selected by the column selector circuit to simultaneously transfer data to sensing nodes (or sensing nodes and latch circuits) of the at least two page buffers. The column select signal CS [k: 1] may be output to be connected to the 160. The column address generator 120CADD may be included in the control circuit 120.

The voltage supply circuits 130 and 140 may generate operating voltages (eg, Vpgm, Vread, and Vpass) necessary for program operation, read operation, and test operation of the memory cells in response to the internal command signal CMDi of the control circuit 120. Supply to local lines including the drain select line DSL, the word lines WL0,..., WLn, and the source select line SSL of the selected memory cell block. This voltage supply circuit includes a voltage generator circuit 130 and a row decoder 140.

The voltage generation circuit 130 may globalize the operating voltages (eg, Vpgm, Vread, and Vpass) required for program operation, read operation, or test operation of the memory cells in response to the internal command signal CMDi of the control circuit 120. Output to lines For example, for a program operation, the voltage generation circuit 130 outputs a program voltage Vpgm for applying to memory cells of a selected page and a pass voltage Vpass for applying to unselected memory cells as global lines. . For the read operation, the voltage generation circuit 130 outputs the read voltage Vread for applying to the memory cells of the selected page and the pass voltage Vpass for applying to the unselected memory cells as global lines. The voltage generation circuit 130 outputs the program voltage Vpgm and the pass voltage Vpass in the test operation related to data storage, like the program operation, and the read voltage Vread and the read operation in the test operation related to the data read. The pass voltage Vpass may be output.

In response to the row address signals RADD of the control circuit 120, the row decoder 140 selects a memory block 110MB in which the operating voltages output from the voltage generation circuit 130 as global lines are selected in the memory array 110. Connect the global lines and the local lines DSL, WL0 to WLn, SSL so that they can be transferred to the local lines DSL, WL0 to WLn, SSL. Thus, the program voltage Vpgm or the read voltage Vread is applied to the local word line (eg, WL0) connected to the selected cell (eg, C0e1) through the global word line from the voltage generation circuit 130. In addition, a pass voltage Vpass is applied to the local word lines (eg, WL1 to WLn) connected to the unselected cells C1e1 to Cne1 through the global word lines from the voltage generation circuit 130. In the erase operation, the erase voltage Vera may be applied to all of the memory cells in the block. Accordingly, data is stored in the selected cell C0e1 by the program voltage Vpgm, or data stored in the selected cell C0e1 is read by the read voltage Vread.

The page buffer groups 150 respectively include a plurality of page buffers PB1 to PBk connected to the memory array 110 through bit lines BLe1 to BLek and BLo1 to BLok. The page buffers PB1 to PBk of the page buffer group 150 are input to store data in the memory cells C0e1 to C0ek or C0o1 to C0ok in response to the PB control signal PB_SIGNALS of the control circuit 120. In order to selectively precharge the bit lines BLe1 to BLek or BLo1 to BLok according to the data, or to read data from the memory cells C0e1 to C0ek or C0o1 to C0ok, the bit lines BLe1 to BLek or BLo1 to BLok. Senses the voltage.

For example, when program data (e.g., '0' data) is input to the page buffer PB1 for storage in the memory cell C0e1, in the program operation, the page buffer PB1 stores the program data (E. G., Ground voltage) to the bit line BLe1 of the memory cell array C0e1. As a result, the threshold voltage of the memory cell C0e1 rises by the program voltage Vpgm applied to the word line WL0 in the programming operation and the program allowable voltage applied to the bit line BLe1. When the erase data (e.g., '1' data) is input to the page buffer PB1 to be stored in the memory cell C0e1, in the program operation, the page buffer PB1 stores the erase data in the memory cell C0e1, (For example, power supply voltage) to the bit line BLe1 of the bit line BLe1. As a result, even if the program voltage Vpgm is applied to the word line WL0 in the program operation, the threshold voltage of the memory cell C0e1 does not rise due to the program inhibition voltage applied to the bit line BLe1. As the threshold voltages are different from each other, different data can be stored in the memory cell.

On the other hand, in the read operation, the page buffer group 150 precharges all the selected bit lines (e.g., BLe1 to BLek) among the even bit lines BLe1 to BLek and the odd bit lines BLo1 to BLok, All of the bit lines (e.g., BLo1 to BLok) are discharged. When the read voltage Vread is applied to the selected word line WL0 from the voltage supply circuits 130 and 140, the bit lines of the memory cells in which the program data is stored maintain the precharge state, and the memory cell in which the erase data is stored. Bit lines are discharged. The page buffer group 150 senses the voltage change of the bit lines BLe1 to BLek and latches the data of the memory cells corresponding to the sensing result.

The specific configuration of the page buffer will be described later.

The column select circuit 160 selects the page buffers PB1 to PBk included in the page buffer group 150 in response to the column select signal CS [k: 1] output from the column address generator 120CADD. do. That is, the column select circuit 160 sequentially transfers data to be stored in the memory cells to the page buffers PB1 to PBk in response to the column select signal CS [k: 1]. In addition, the page buffers PB1 to sequentially in response to the column selection signal CS [k: 1] so that data of memory cells latched to the page buffers PB1 to PBk by the read operation may be output to the outside. PBk).

In particular, the column select circuit 160 transmits data to be stored in the memory cells to the sensing nodes SO1 to SOk of the page buffers PB1 to PBk or terminals of the latch circuits of the page buffers PB1 to PBk. To QA and QB and sensing nodes SO1 to SOk at the same time. In addition, the same data is simultaneously transmitted to the sensing nodes SO1 to SOk of two or more page buffers in response to the column selection signal CS [k: 1], or terminals of the latch circuits of the page buffers PB1 to PBk. To QA and QB and sensing nodes SO1 to SOk at the same time. Details will be described later.

The input / output circuit 170 transfers data to the column selection circuit 160 under the control of the control circuit 120 to input data input from the outside into the page buffer group 150 for storage in memory cells during a program operation. do. When the column selection circuit 160 transfers the data transferred from the input / output circuit 170 to the page buffers PB1 to PBk of the page buffer group 150 according to the method described above, the page buffers PB1 to PBk are input. The stored data is stored in an internal latch circuit. In addition, during the read operation, the input / output circuit 170 outputs data transferred from the page buffers PB1 to PBk of the page buffer group 150 through the column select circuit 160 to the outside.

The pass / fail check circuit 180 passes / passes in response to the comparison result signals PF [1] to PF [k] respectively output from the page buffers PB1 to PBk in the program verify operation performed after the program operation. Output the fail signal (PF_SIGNAL). Specifically, in the program verify operation, the threshold voltage of the memory cell is compared with the target voltage, and the result is latched in the internal latch circuit of the page buffers PB1 to PBk. The latched comparison result signals PF [1] to PF [k] are output to the pass / fail check circuit 180. The pass / fail check circuit 180 outputs a pass / fail signal PF_SIGNAL indicating whether the program operation is completed to the control circuit 120 in response to the comparison result signals PF [1] to PF [k]. . In response to the pass / fail signal PF_SIGNAL, the control circuit 120 determines whether a memory cell having a threshold voltage lower than a target voltage exists among memory cells in which the program data is stored, and determines whether to repeat the program operation according to the result. Decide

FIG. 3 is a circuit diagram for describing the page buffer shown in FIG. 1.

Referring to FIG. 3, the page buffer PB1 operates under the control of the control circuit 120 of FIG. 1, and the signals PRECHb, TRAN, RST, SET, PBSENSE, BLSe, BLSo, DISCHe, DISCHo) can be output from the control circuit.

The page buffer PB1 includes a bit line connection circuit BLC, a precharge circuit P101, and a plurality of latch circuits 150L1 to 150L3.

The switching elements N105 and N107 of the bit line connection circuit BLC select one bit line among the even bit line BLe1 and the odd bit line BLo1 in response to the bit line selection signals BLSe and BLSo. In addition, the switching elements N101 and N103 may precharge the unselected bit line during the program operation or discharge the unselected bit line during the read operation in response to the discharge signals DISCHe and DISCHo. The switching element N109 connects the bit line selected by the switching elements N105 and N107 and one latch circuit of the latch circuits 150L1 to 150L3 in response to the connection signal PBSENSE. The latch circuits LC1 to LC3 are connected in parallel to the switching element N109 and the connection node of the switching element N109 and the latch circuits LC1 to LC3 becomes the sensing node SO.

The precharge circuit P101 performs an operation of precharging the sensing node SO in response to the precharge signal PRECHB.

The number of the latch circuits LC1 to LC3 may be changed according to the design, and the case where three latch circuits LC1 to LC3 are provided will be described as an example. Typically, only one latch circuit LC1 to LC3 is activated. Among these, the first latch circuit LC1 temporarily stores data input from the column select circuit 160 and transfers the data to the second latch circuit LC2 or transfers data read from the memory cell by a read operation to the column select circuit. In order to output to 160, a temporary storage operation may be performed. The second latch circuit LC2 may apply a program inhibit voltage or a program permission voltage to the bit line during the program operation according to the data transmitted from the first latch circuit LC1. The second latch circuit LC2 may also temporarily store the data stored in the memory cell in response to the voltage of the bit line during the read operation and transfer the data to the first latch circuit LC1. The third latch circuit LC3 latches the comparison result value between the threshold voltage of the memory cell and the target voltage in the verify operation performed after the program operation and outputs a comparison result signal corresponding to the comparison result value to the pass / 180). ≪ / RTI >

The latch circuits include a plurality of switching elements and a latch. The first latch circuit LC1 will be described as an example.

The first latch circuit LC1 is configured to connect the first node QA of the latch LAT to the sensing node SO in response to a latch LAT for latching data and a transmission signal TRAN. N111, switching elements N113 and N115 respectively connected to the non-inverting terminal QA and the inverting terminal QB of the latch LAT and operating in response to the set signal SET and the reset signal RST, respectively. And a switching element N117 connected between the switching elements N113 and N115 and the ground terminal and operating according to the potential of the sensing node SO. For reference, the column selection circuit 160 of FIG. 1 may include the sensing node SO and the non-inverting terminal QA of the latch LAT1 of the page buffer PB1 selected in response to the column selection signal CS [k: 1]. ) And inverting terminal QB.

Since signals of different waveforms are input to the other latch circuits LC2 and LC3, only one latch circuit can be activated or perform different functions even if they have the same configuration.

FIG. 4 is a circuit diagram for describing a column selection circuit and an input / output circuit shown in FIG. 1.

Referring to FIG. 4, the input / output circuit 170 outputs data input from the outside through the data line DL to the first internal data line BITOUT and outputs inverted data to the second internal data line BITOUTb. .

The column select circuit 160 includes a plurality of first data transmitters 160Ai and 160Aj and a plurality of second data transmitters 160Bi and 160Bj. The first data transfer units 160Ai and 160Aj connect the first internal data line BITOUT and the second internal data line BITOUTb with a page buffer selected by the column select signals CSi and CSj. In addition, the second data transmitters 160Bi and 160Bj connect the first internal data line BITOUT to the sensing nodes SOi and SOj of the page buffer selected by the column select signal CS [k: 1].

The column select circuit 160 connects one selected page buffer and the internal data lines BITOUT and BITOUTb in response to the column select signal CS [k: 1], or two or more page buffers and the internal data line. (BITOUT, BITOUTb) can be connected at the same time. When the column select circuit 160 connects two or more page buffers and the internal data lines BITOUT and BITOUTb simultaneously in response to the column select signal CS [k: 1], the first internal data line BITOUT The data transferred to the non-inverting terminals QAi and QAj and the sensing nodes SOi and SOj of the latches included in the selected two or more page buffers PBi and PBj are transferred to the second internal data line BITOUTb. Inverted data transferred to) is transferred to the inverting terminals QBi and QBj of the latches included in the two or more page buffers PBi and PBj.

Hereinafter, an operation method of the semiconductor memory device described above will be described.

5 is a waveform diagram illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention.

3 to 5, data for inputting to the latch circuits connected to the sensing nodes SOi and SOj is input to the data input / output circuit 170. The input / output circuit 170 outputs the input data to the first internal data line BITOUT and outputs the inverted data to the second internal data line BITOUTb.

In addition, the sensing nodes SO are precharged by the precharge circuit P101 that operates in response to the precharge signal PRECHb before data is transferred. In addition, the latches LAT of the page buffers are initialized. That is, as the switching device N117 is turned on by the voltage of the precharged sensing node SO and the switching device N115 is turned on by the reset signal RST, the non-inverting terminal QA of the latch LAT is turned on. Becomes low level and inverting terminal QB becomes high level. This stores zero data in the latch circuits before the data is stored in the latch circuits.

The column select signal CS [k: 1] is output from the column address generator (120CADD in FIG. 1). In this case, in a specific mode such as the test mode, the column address generation unit may select a column selection signal CS [to select at least two or more page buffers (more specifically, latch circuits) among the page buffers (more specifically, latch circuits). k: 1]). For example, the column select signal CS [k: 1] may be output so that 8, 16, 32, 64 or more page buffers can be grouped and selected simultaneously. The column selection signal CS [k: 1] is changed by the column address generator 120CADD so that the next group of page buffers can be simultaneously selected after data is input to the page buffers of the selected group.

The data received by the input / output circuit 170 received from the outside is at least two or more page buffers (more specifically, sensing nodes) through the column selection circuit 160 in response to the column selection signal CS [k: 1]. At the same time. At this time, the same data is simultaneously delivered to two or more page buffers (more specifically, sensing nodes). When the high level data (solid line display) is input, the voltage level of the sensing node SO (solid line display) is maintained, and when the low level data (dotted line display) is input, the voltage level of the sensing node SO (dotted line display). Is lowered.

Since the sensing node SO is formed of metal wires on the substrate and an insulating film is present between the metal wires and the substrate, the sensing node SO has a capacitor component. In addition, since the sensing node SO is also connected to the switching elements, the sensing node SO has more capacitor components. Accordingly, the sensing node S0 having the capacitor component may function as a buffer for temporarily storing data.

On the other hand, the non-inverting terminal QA and the inverting terminal QB of the latch circuits LC1 are also connected to the first internal data line BITOUT and the second internal data line by the column select signal CS [k: 1]. Data stored in the latch circuits LC1 may be changed according to data transmitted through BITOUTb. However, the input / output circuit 170 is connected to the latch circuits LC1 through fairly long internal data lines BITOUT and BITOUTb and controls the latch circuits LC1 having a large driving capability of the input / output circuit 170. Since it is not large enough, the data stored in the latch circuits LC1 may not be changed by the data output from the input / output circuit 170. However, since the driving capability of the input / output circuit 170 is large enough to simultaneously change the voltage levels of the sensing nodes SO, the voltage levels of the sensing nodes SO are dependent on the data output from the input / output circuit 170. Enough change.

The operation of storing the data transferred to the sensing nodes SO in the latch circuits (more specifically, the latch) is performed. Specifically, for example, the switching element N113 is turned on by the set signal SET. In addition, it is determined whether the switching element N117 is turned on according to the voltage level of the sensing node SO (that is, the voltage level of the data transferred to the sensing node). When the high level data is transferred to the sensing node SO, since the switching element N117 is turned on, the non-inverting terminal QB of the latch LAT is connected to the ground terminal through the switching elements N117 and N113. . As a result, the inverting terminal QB of the latch LAT becomes a low level (solid line) and the non-inverting terminal QA becomes a high level (solid line). As a result, the latch circuit LC1 stores high level data. When the low level data is transferred to the sensing node SO, since the switching device N117 is turned off, the non-inverting terminal QB of the latch LAT is not connected to the ground terminal. Accordingly, the inverting terminal QB of the latch LAT maintains a high level (dotted line) and the non-inverting terminal QA maintains a low level (dotted line). As a result, the latch circuit LC1 stores low level data.

As a result, the same data may be stably stored at the same time in the latch circuits of two or more page buffers.

When data is simultaneously input to the latch circuits without storing the data in the latch circuits through the sensing node, it is difficult to accurately input data into the latch circuits because the driving capability of the input / output circuit is insufficient as described above. This can take a long time. In order to input data quickly, the driving capability of the input / output circuit must be increased, which may cause a problem that the size of the input / output circuit must be increased and the chip size must be increased.

However, using the semiconductor memory device and the operation method described above, the data can be quickly input to multiple page buffers at the same time, thereby improving the operation speed.

110: memory array 110 MB: memory block
PAGE0: Page ST1 ~ ST2k: String
120: control circuit 130: voltage generating circuit
140: row decoder 150: page buffer group
160: column selection circuit 170: input and output circuit
180: pass / fail check circuit

Claims (16)

A plurality of latch circuits, each coupled to the sensing nodes, for latching data;
A plurality of bit line connection circuits configured to respectively connect the sensing nodes and the bit lines in response to a bit line connection signal to transfer data latched to the latch circuits to bit lines of a memory block, respectively;
A column selection circuit configured to simultaneously transmit data received from the outside to at least two or more said sensing nodes in response to a column selection signal; And
And a control circuit for controlling the latch circuits so that the latch circuits latch the data transferred from the column select circuit to the sensing nodes.
The method of claim 1,
And a precharge circuit configured to precharge the sensing node in response to a precharge signal before the data is transferred to the sensing node.
The method of claim 1, wherein the latch circuit,
A latch for latching the data;
A first switching element operating according to a potential of the sensing node and connected to a ground terminal;
A second switching element connected between the non-inverting terminal of the latch and the first switching element and operating in response to a reset signal;
A third switching element connected between the inverting terminal of the latch and the first switching element and operating in response to a set signal; And
And a fourth switching element connected between the non-inverting terminal of the latch and the sensing node and operating in response to a transmission signal.
The method of claim 1,
And the column selection circuit is configured to transfer the data to the latch circuit as well.
The method of claim 1, wherein the column selection circuit,
A first data transmitter configured to transmit the data to the sensing node in response to the column selection signal; And
And a second data transfer unit configured to transfer the data to the latch circuit in response to the column select signal.
The method of claim 1,
And an input / output circuit configured to generate the inverted data using the data received from the outside, and to transmit the data and the inverted data to the column selection circuit.
The method according to claim 6,
And the latch circuit includes a latch for latching the data, wherein the column select circuit is configured to transfer the data to a non-inverting terminal of the latch and to transfer inverted data to an inverting terminal of the latch.
The method of claim 7, wherein the column selection circuit,
A first data transmitter configured to transmit the data to the sensing node in response to the column selection signal; And
And a second data transfer unit configured to transmit the data to a non-inverting terminal of the latch in response to the column select signal and to transmit the inverted data to the inverting terminal of the latch.
The method of claim 1,
The column selection circuit is configured to simultaneously transfer the same data to at least two sensing nodes in a test mode.
The method of claim 1,
And a column address generator configured to generate the column select signal.
11. The method according to claim 9 or 10,
And the column address generator outputs the column select signal to simultaneously transmit the same data to at least two sensing nodes in the test mode.
Inputting data for input into latch circuits respectively connected to the sensing nodes;
Generating a column select signal for selecting at least two or more latch circuits of the latch circuits;
Simultaneously transmitting data received from the outside to at least two sensing nodes in response to the column selection signal; And
Storing the data transferred to the sensing nodes in the latch circuits.
13. The method of claim 12,
Precharging the sensing node before the data is transferred to the sensing node.
13. The method of claim 12,
Storing zero data in the latch circuits before the data is stored in the latch circuits.
The method of claim 12, wherein the data is passed to the sensing nodes.
And operating the same data to the sensing nodes.
13. The method of claim 12,
And the latch circuits are divided into a plurality of groups, and data transmitted simultaneously to sensing nodes of the group for each group are simultaneously stored as latch circuits in the group.

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