KR20120118783A - Sense amplifier - Google Patents

Sense amplifier Download PDF

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Publication number
KR20120118783A
KR20120118783A KR1020110036382A KR20110036382A KR20120118783A KR 20120118783 A KR20120118783 A KR 20120118783A KR 1020110036382 A KR1020110036382 A KR 1020110036382A KR 20110036382 A KR20110036382 A KR 20110036382A KR 20120118783 A KR20120118783 A KR 20120118783A
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KR
South Korea
Prior art keywords
pmos transistor
bit line
pmos
voltage
sense amplifier
Prior art date
Application number
KR1020110036382A
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Korean (ko)
Inventor
김동훈
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020110036382A priority Critical patent/KR20120118783A/en
Publication of KR20120118783A publication Critical patent/KR20120118783A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

PURPOSE: A sense amplifier is provided to reduce power consumption by maintaining a threshold voltage property and an operation current property of the PMOS load transistor. CONSTITUTION: An NMOS driving unit(N3,N4) is connected to a ground voltage terminal. A PMOS driving unit(P3,P4) is cross-coupled with the NMOS driving unit and is selectively driven according to a voltage applied to a bit line. A load resistor(R1,R2) is connected between a power voltage applying terminal and the PMOS driving unit. The PMOS driving unit includes a first PMOS transistor and a second PMOS transistor.

Description

Sense amplifier

Embodiments of the present invention relate to a sense amplifier, and a technique for reducing power consumption in a sense amplifier for sensing and amplifying data of a semiconductor memory device.

BACKGROUND With the development of technology in computer systems and electronic communication fields, semiconductor memory devices used for storing information are gradually becoming lower in cost, smaller in size, and larger in capacity. In addition, the demand for energy efficiency is also increasing, and the development of technology for semiconductor devices is being made in the direction of suppressing unnecessary current consumption.

In general, a cell array that stores data of a DRAM device has a structure in which many cells each consisting of one NMOS transistor and a capacitor are connected to word lines and bit lines connected in a mesh shape.

Such a semiconductor memory device is for storing data or reading stored data in a plurality of memory cells, and includes a plurality of bit lines and a plurality of word lines, a circuit for selecting the bit lines and word lines, and Peripheral circuits such as a plurality of sense amplifiers;

The operation of a typical DRAM device will be briefly described.

First, an address signal input to a row address buffer is input while a ras (/ RAS) signal, which is a main signal for operating a DRAM device, is changed to an active state (low level). At this time, a row decoding operation of decoding one of the row address signals and selecting one of the word lines of the cell array is performed.

At this time, data of the cells connected to the selected word line is loaded on the bit line pair BL // BL consisting of the bit line and the complementary bit line. Then, the sense amplifier enable signal indicating the operation time of the sense amplifier is enabled to drive the sense amplifier driving circuit of the cell block selected by the row address.

The sense amplifier bias potential is shifted to the core potential Vcore and the ground potential Vss by the sense amplifier driving circuit to drive the sense amplifier. When the sense amplifier starts to operate, the bit line pairs BL and / BL, which have kept a small potential difference between them, transition to a large potential difference.

After that, the column decoder turns on the column transfer transistor that transfers the data of the bit line to the data bus line in response to the column address, thereby transferring the data transferred to the bit line pair BL // BL to the data bus. It is delivered to the line (DB, / DB) to be output to the outside of the device.

Here, the sense amplifier includes an equalization control unit for equalizing the bit line pairs, a precharge unit for precharging the bit line pairs, an output control unit for outputting the data of the bit line pairs to an external bus, and a bit line for amplifying the data carried on the bit line pairs. And a isolation transistor for separating the sense amplifier, the memory cell array, and the sense amplifier.

1 is a detailed circuit diagram of a general sense amplifier.

Typical sense amplifiers include cross-coupled PMOS transistors P1 and P2 and NMOS transistors N1 and N2.

Here, the PMOS transistor P1 and the NMOS transistor N1 are connected in series between the power supply voltage VDD and the ground voltage VSS, and the common gate terminal is connected to the bit line / BL. The PMOS transistor P2 and the NMOS transistor N2 are connected in series between a power supply voltage VDD and a ground voltage VSS, and a common gate terminal is connected to the bit line BL.

Typical semiconductor devices use a sense amplifier to amplify a fine signal (current or voltage). During the sensing process, the sense amplifier becomes high or low due to the voltage / current difference between the sensing target node (node A of the bit line BL) and the reference node (node B of the bit line / BL).

In addition, the sense amplifier passes through an unstable state of the PMOS transistors P1 and P2 and the NMOS transistors N1 and N2 until the sensing is completed. In this period, the operating current of the PMOS load transistor is an indicator of power consumption of the sense amplifier.

Therefore, in order to reduce the power consumption, the PMOS transistors P1 and P2 should be designed to increase the threshold voltage Vt or lower the operating current Iop.

However, if the threshold voltage Vt of the PMOS transistors P1 and P2 is increased or the operating current Iop is decreased, the operating sensitivity is lowered, thereby deteriorating the sensing margin.

Here, PMOS transistors P1, P2 or NMOS transistors N1, which are used in sense amplifiers to compare minute voltage / current differences between the sensing target node (node A of bit line BL) and the reference node (node B of bit line / BL), N2 should have the same characteristics as possible. At the same time, each pair of transistors must exhibit a different level of operating current (Iop) characteristic difference even at a low voltage / current difference.

Accordingly, when the threshold voltage Vt of the PMOS transistors P1 and P2 is increased or the operating current Iop is reduced, the operating characteristics of the sense amplifier are deteriorated.

That is, various methods for reducing power consumption in manufacturing a semiconductor device have been used. However, in the case of a sense amplifier circuit that amplifies a fine current or voltage, if the power consumption is designed in a direction of reducing power consumption, the sensing margin is reduced and power consumption is increased.

Embodiments of the present invention have the following features.

First, a resistor having a specific range of resistance value is added between the power supply voltage VDD and the PMOS load transistor, and the threshold voltage Vt and the operating current Iop of the PMOS load transistor are used to maintain the sensing sensitivity of the sense amplifier. By maintaining the characteristics as it is, it is possible to reduce the power consumption without deteriorating the sensing sensitivity.

Second, by adding a resistor having a specific range of resistance value between the power supply voltage VDD and the PMOS load transistor and replacing the PMOS load transistor with a variable resistor, power consumption can be reduced while maintaining the sense sensitivity of the sense amplifier. There is a characteristic to.

According to an embodiment of the present invention, a sense amplifier includes: an NMOS driver connected to a ground voltage terminal; A PMOS driver which is cross-coupled with the NMOS driver and selectively driven according to a voltage applied to the bit line; And a load resistor connected between the power supply voltage applying stage and the PMOS driver.

In addition, the sense amplifier according to another embodiment of the present invention, the first load resistor connected to the power supply voltage applying stage; A second rod resistor connected in parallel with the first rod resistor; A first PMOS transistor coupled between the first load resistor and the first bit line and selectively switched according to the voltage of the second bit line; A second PMOS transistor connected between the second load resistor and the second bit line and selectively switched according to the voltage of the first bit line; A first NMOS transistor coupled between the first PMOS transistor and the ground voltage applying terminal and selectively switched according to the voltage of the second bit line; And a second NMOS transistor connected between the second PMOS transistor and the ground voltage applying terminal and selectively switched according to the voltage of the first bit line.

An embodiment of the present invention has the following effects.

First, the threshold voltage (Vt) and the operating current (Iop) characteristics of the PMOS load transistor for maintaining the sensing sensitivity of the sense amplifier is maintained so that the power consumption can be reduced without deteriorating the sensing sensitivity.

Second, it provides an effect to minimize the power consumption of the sense amplifier.

Third, when applied to memory semiconductor products that use a lot of sense amplifier circuit, it can be effectively used for mobile or low power products.

It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. .

1 is a detailed circuit diagram of a general sense amplifier.
2 and 3 are circuit diagrams of a sense amplifier according to an embodiment of the present invention.
4 is a view for explaining the operation of the sense amplifier according to an embodiment of the present invention.
5 is a view for explaining the operating characteristics of the sense amplifier according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a detailed circuit diagram of a sense amplifier according to an embodiment of the present invention.

The sense amplifier according to the embodiment of the present invention includes a cross-coupled PMOS transistor P3, P4, NMOS transistors N3, N4 and load resistors R1, R2.

Here, the PMOS transistors P3 and P4 correspond to the PMOS driving units having a latch structure, and the NMOS transistors N3 and N4 correspond to the NMOS driving units having a latch structure.

The load resistor R1, the PMOS transistor P3 and the NMOS transistor N3 are connected in series between the supply voltage VDD and the ground voltage VSS.

In addition, the PMOS transistor P3 and the NMOS transistor N3 have a common gate terminal connected to the node D of the bit line / BL.

The load resistor R2, the PMOS transistor P4, and the NMOS transistor N4 are connected in series between a power supply voltage VDD and a ground voltage VSS.

The PMOS transistor P3 and the NMOS transistor N3 have a common gate terminal connected to the node C of the bit line BL.

In the sense amplifier according to the embodiment of the present invention having such a configuration, since the initial voltage between the load resistors R1 and R2 and the PMOS transistors P3 and P4 becomes relatively high during the initial operation, the PMOS transistors P3 and P4 operate normally. .

As the turn-on current of the PMOS transistors P3 and P4 increases, the resistance ratio between the load resistors R1 and R2 decreases, and the voltage between the load resistors R1 and R2 and the PMOS transistors P3 and P4 decreases, thereby reducing power consumption. do.

Therefore, during the initial operation of the sense amplifier, it is possible to perform a sensing operation similar to that of the prior art, and when the PMOS transistors P3 and P4 are turned on to increase the current, the current is increased by the load resistors R1 and R2. Will decrease.

In this case, the characteristics of the load resistors R1 and R2 are positioned within a predetermined range so that the characteristics of the sense amplifiers may not be deteriorated.

3 is a detailed circuit diagram of a sense amplifier according to another embodiment of the present invention.

According to another embodiment of the present invention, a sense amplifier includes cross-coupled PMOS transistors P5 and P6, NMOS transistors N5 and N6, and load resistors R3 and R4.

Here, the PMOS transistors P5 and P6 correspond to the PMOS driving parts of the latch structure, and the NMOS transistors N5 and N6 correspond to the NMOS driving parts of the latch structure.

The load resistor R3, the PMOS transistor P5 and the NMOS transistor N5 are connected in series between a supply voltage VDD and a ground voltage VSS.

The gate terminals of the PMOS transistor P5 and the NMOS transistor N5 are commonly connected to the node F of the bit line / BL.

The load resistor R4, the PMOS transistor P6, and the NMOS transistor N6 are connected in series between a power supply voltage VDD supply terminal and a ground voltage VSS application terminal.

The gate terminals of the PMOS transistor P6 and the NMOS transistor N6 are commonly connected to the node E of the bit line BL.

Here, the variable resistors Rp1 and Rp2 are shown as variable resistors Rp1 and Rp2 on the equivalent circuit, in which the PMOS transistors P5 and P6 have a characteristic of being turned on or off depending on the Vgs (gate-source voltage) condition.

An operation process of the present invention having such a configuration will now be described with reference to FIGS. 4 and 5.

First, a voltage having a minute difference is applied to a bit line BL as a sensing target node and a bit line / BL as a reference node during an initial operation of the sense amplifier.

Then, the difference between the minute voltages (or currents) applied to the bit lines BL and the bit lines / BL is represented by the PMOS transistors P5 and P6 (denoted by the variable resistors Rp1 and Rp2) and the NNMOS transistors N5 and N6 connected to the respective nodes E and F. Is applied to the pair.

At this time, the PMOS transistors P5 and P6 and the NNMOS transistors N5 and N6 pairs are different in the operating current (Iop) characteristics of the transistor due to different potential differences.

This difference proceeds in a direction in which the potential difference between the bit line BL node E and the bit line / BL node F is further increased.

It is assumed that the bit line BL is driven high among the cases where the sensing operation is performed in a direction in which the potential difference between the bit line BL and the bit line / BL is increased as described above.

Then, the PMOS transistor P6 is gradually turned off, and the PMOS transistor P5 exhibits characteristics according to Vgs (gate-source voltage) applied to the gate.

In addition, when the voltage applied to the bit line BL is greater than or equal to the Vgs voltage exceeding the sensing margin determination period, the PMOS transistor P5 may operate in a specific state according to a bias condition such as the power supply voltage VDD or the Vgs voltage. Iop) characteristic.

The PMOS transistor P5 may be represented by the value of the variable resistor Rp1 on the equivalent circuit. The load resistors R3 and R4 may be represented by resistance values of Rk. Here, the load resistors R3 and R4 preferably have the same resistance value Rk.

At this time, if the resistance value of the variable resistor Rp1 is Rl and the resistance value of the variable resistor Rp2 is Rh, the resistance value of Rk is set so as to satisfy the condition of Rl≤Rk≤Rh.

Here, the variable resistor Rp represents a current characteristic according to the turn-on or turn-off switching operating conditions of the PMOS transistors P5 and P6 as variable resistance values.

In addition, the resistance value Rl represents a current characteristic as an equivalent resistance when the PMOS transistor P5 is turned on. In addition, the resistance value Rh is a value representing current characteristics as an equivalent resistance when the PMOS transistor P6 is turned off.

Then, the voltage of the node G can be set so as to be a condition of the power supply voltage VDD-α (α> 0). Here, the value of α may be a value of the leakage current generated at the node G (or node H).

In this case, the overall power consumption of the sense amplifier is reduced as the operating current (Iop) decreases due to the bias downward in the source terminal of the PMOS transistor P5. In addition, it is possible to minimize the power consumption by appropriately adjusting the resistance value Rk.

In the initial operation of the sense amplifier, both the PMOS transistors P5 and P6 are weakly turned on and the resistance value Rp becomes relatively large.

In other words, during the initial operation of the sense amplifier, the equivalent resistance value Rh when the PMOS transistor P6 is turned off becomes Rh, so that Rk < Rp or Rk? Rp conditions are established.

According to the voltage distribution principle of the power supply voltage VDD, the node G and H maintain the power supply voltage VDD bias state for a predetermined period.

Therefore, in the initial operation for the sensing operation, the influence of the load resistance is relatively small, thereby minimizing the problem that the sensing margin is reduced.

As shown in FIG. 5, the sense amplifier according to the exemplary embodiment of the present invention performs an operation similar to that of the related art in the initial operation of determining the sensing margin. In addition, after the sensing margin determination period T in which the sensing operation is completed, the operating current Id is reduced to reduce power consumption.

Claims (10)

An NMOS driver connected to the ground voltage terminal;
A PMOS driver which is cross-coupled with the NMOS driver and selectively driven according to a voltage applied to a bit line; And
And a load resistor connected between a power supply voltage applying stage and the PMOS driver. The method of claim 1, wherein the PMOS driver
A first PMOS transistor selectively driven by the first bit line; And
And a second PMOS transistor selectively driven by a second bit line. The method of claim 2, wherein the load resistance is
A first load resistor connected between the power supply voltage supply terminal and the first PMOS transistor; And
And a second load resistor connected between the power supply voltage supply terminal and the second PMOS transistor. The sense amplifier of claim 3, wherein the first rod resistor and the second rod resistor have the same resistance value. 4. The sense amplifier of claim 3, wherein a voltage value lower than a power supply voltage is applied to a source terminal of the PMOS driver during an initial operation of turning off the first PMOS transistor and the second PMOS transistor. 4. The method of claim 3, wherein when the first PMOS transistor is turned on and has a first resistance value, and when the second PMOS transistor is turned off, the first rod resistance and the second resistor are the second resistance value. The resistance value of the load resistance is a sense amplifier, characterized in that it is set in a range larger than the first resistance value and less than the second resistance value. A first load resistor connected to a power supply voltage supply terminal;
A second rod resistor connected in parallel with the first rod resistor;
A first PMOS transistor connected between the first load resistor and the first bit line and selectively switched according to a voltage of a second bit line;
A second PMOS transistor connected between the second load resistor and the second bit line and selectively switched according to the voltage of the first bit line;
A first NMOS transistor connected between the first PMOS transistor and a ground voltage applying terminal and selectively switched according to the voltage of the second bit line; And
And a second NMOS transistor connected between the second PMOS transistor and the ground voltage applying terminal and selectively switched according to the voltage of the first bit line. 8. The sense amplifier of claim 7, wherein the first rod resistor and the second rod resistor have the same resistance value. 8. The sensor of claim 7, wherein a voltage value lower than a power supply voltage is applied to a source terminal of the first PMOS transistor and the second PMOS transistor during an initial operation of turning off the first PMOS transistor and the second PMOS transistor. Amplifier. 8. The method of claim 7, wherein the first rod resistor and the second resistor have a first resistance value when the first PMOS transistor is turned on, and has a second resistance value when the second PMOS transistor is turned off. The resistance value of the load resistance is a sense amplifier, characterized in that it is set in a range larger than the first resistance value and less than the second resistance value.
KR1020110036382A 2011-04-19 2011-04-19 Sense amplifier KR20120118783A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110036382A KR20120118783A (en) 2011-04-19 2011-04-19 Sense amplifier

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Application Number Priority Date Filing Date Title
KR1020110036382A KR20120118783A (en) 2011-04-19 2011-04-19 Sense amplifier

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