KR20120110452A - Three dimensional semiconductor memory devices and methods of fabricating the same - Google Patents

Abstract

PURPOSE: A 3D semiconductor memory device and manufacturing method thereof are provided to prevent the resistance of an electrode by minimizing the etching loss of the highest electrode. CONSTITUTION: An electrode structure includes stacked electrodes and an insulating pattern. A work electrode includes a first outer sidewall and a second outer sidewall facing each other. A vertical active pattern(120) passes through the electrode structure. An electrode dielectric layer(170) is interposed between each electrode. The electrode dielectric layer is located between the sidewalls of the vertical active pattern.

Description

THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a three-dimensional semiconductor memory device and a manufacturing method thereof.

Due to their small size, versatility and / or low manufacturing cost, semiconductor devices are becoming an important element in the electronics industry. As the electronics industry develops, there is an increasing demand for better performance and / or lower cost semiconductor devices. In order to meet these requirements, the trend toward higher integration of semiconductor devices is intensifying. In particular, high integration of semiconductor memory devices for storing logic data is further intensified.

The degree of integration of a conventional two-dimensional semiconductor memory device may act as a main determinant of the planar area occupied by the unit memory cells. As a result, the degree of integration of the two-dimensional semiconductor memory element can be greatly influenced by the level of the fine pattern formation technology. However, the technology of forming fine patterns is approaching the limit, and also, there are problems such as an increase in the manufacturing cost of semiconductor memory devices due to the need for expensive equipment.

In order to overcome these limitations, a three-dimensional semiconductor memory device including three-dimensionally arranged memory cells has been proposed. However, the three-dimensional semiconductor memory device may cause problems such as deterioration in reliability due to its structural shape.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a three-dimensional semiconductor memory device capable of improving reliability and a method of manufacturing the same.

Another object of the present invention is to provide a three-dimensional semiconductor memory device optimized for high integration and a method of manufacturing the same.

Provided are a three-dimensional semiconductor memory device for solving the above technical problems. According to an aspect of the present invention, a three-dimensional semiconductor memory device comprises an electrode structure comprising electrodes and insulating patterns alternately and repeatedly stacked on a substrate, wherein one electrode of the electrodes is opposed to each other; Having an outer wall and a second outer wall; A vertical active pattern penetrating the electrode structure; And an electrode-dielectric film interposed between the sidewalls of the vertical active pattern and the electrodes. At least a portion of the electrode-dielectric film positioned between the one electrode and the sidewall of the vertical active pattern may extend to cover the bottom surface, the top surface, and the first outer wall of the top electrode.

In an embodiment, the extension of the at least a portion of the electrode-dielectric film may not cover the second outer wall of the one electrode.

In an embodiment, the device may further include a pair of device isolation patterns disposed on substrates on both sides of the electrode structure. In this case, the second outer wall of the one electrode may be in contact with any one of the pair of device isolation patterns.

In example embodiments, the electrode structure may include another electrode having both outer walls contacting the pair of device isolation patterns, respectively.

According to one embodiment, the one electrode may correspond to the top electrode in the electrode structure.

According to an embodiment, the next uppermost electrode positioned directly below the top electrode among the electrodes may have a first outer wall and a second outer wall facing each other. The first outer wall and the second outer wall of the next higher electrode may be aligned with the first outer wall and the second outer wall of the uppermost electrode, respectively. At least a portion of the electrode-dielectric film positioned between the sidewall of the next upper electrode and the vertical active pattern may extend to cover the bottom surface, the top surface, and the first outer wall of the next upper electrode.

According to an embodiment, an electrode-dielectric film extension covering the first outer wall of the uppermost electrode extends downward along one outer wall of the insulating pattern between the uppermost and second upper electrodes to cover the first outer wall of the second upper electrode. It may be connected to the extension of the dielectric film.

In an embodiment, the top electrode may extend downward along one outer wall of the insulating pattern between the top and second top electrodes to be connected to the top top electrode.

In an embodiment, the extension of the electrode-dielectric film covering the first outer walls of the top electrode may be spaced apart from the extension of the electrode-dielectric film covering the first outer wall of the next upper electrode. The top electrode and the next upper electrode may also be spaced apart from each other. Can be separated from each other.

In example embodiments, the non-sacrificial pattern may be in contact with the one outer wall of the insulating pattern between the uppermost and second upper electrodes.

In an embodiment, the electrode structure may include one lowermost electrode, and the uppermost electrode may be provided in plurality over the lowermost electrode. The plurality of top electrodes may be spaced apart from each other and positioned at the same level from the upper surface of the substrate. The vertical active pattern may be provided in plurality. Each vertical active pattern may penetrate each top electrode and electrodes stacked below each top electrode.

According to another aspect of the present invention, a three-dimensional semiconductor memory device includes an electrode structure comprising electrodes and insulating patterns alternately and repeatedly stacked on a substrate, each electrode comprising a metal pattern and a barrier conductive pattern; A vertical active pattern penetrating the electrode structure; And an electrode-dielectric film interposed between the sidewalls of the vertical active pattern and the electrodes. Among the electrodes, the metal pattern in one electrode may have a first outer wall and a second outer wall facing each other. In this case, the barrier conductive pattern in the one electrode may contact the first outer wall of the metal pattern in the one electrode.

In example embodiments, the electrode-dielectric film may extend vertically and be interposed between the sidewall of the vertical active pattern and the insulating pattern.

In example embodiments, the second outer wall of the metal pattern in the one electrode may not contact the barrier conductive pattern in the one electrode.

According to one embodiment, the one electrode may correspond to the top electrode in the electrode structure.

According to one embodiment, the metal pattern in the next higher electrode located directly below the top electrode may have a first outer wall and a second outer wall facing each other. The barrier conductive pattern in the next upper electrode may contact the first outer wall of the metal pattern in the next upper electrode.

According to still another aspect of the present invention, a method of manufacturing a three-dimensional semiconductor memory device is provided. The method includes alternately and repeatedly stacking sacrificial films and insulating films on a substrate; Forming a cutting region penetrating a top sacrificial layer among the sacrificial layers; Forming a non-sacrificial film in the cutting region; Forming vertical active patterns penetrating the insulating layers and the sacrificial layers; Successively patterning the insulating layers and the sacrificial layers to form a mold pattern including insulating patterns, sacrificial patterns, and a non-sacrificial layer in the cutting region; Removing the sacrificial patterns to form empty regions; Forming electrodes in the empty areas, respectively; And forming an electrode-dielectric film between sidewalls of the vertical active pattern and the electrodes.

According to an embodiment, the method may further include forming a pair of sacrificial spacers on both inner walls of the cutting region, respectively, before forming the non-sacrificial layer. The forming of the empty regions may include removing the sacrificial patterns and at least portions of the sacrificial spacers to form the empty regions and the recess regions.

In example embodiments, the cutting region may be formed by successively patterning a topmost insulating layer among the insulating layers, the topmost sacrificial layer, a next higher insulating layer among the insulating layers, and a next top sacrificial layer among the sacrificial layers. Each recess area may be connected to a topmost bin area and a next upper bin area formed at each side of the cutting area.

According to one embodiment, forming the electrode-dielectric film may include conformally forming at least a portion of the electrode-dielectric film on a substrate having the empty and recessed regions before forming the electrodes. have. A portion of the recess region located next to the insulating pattern between the topmost and next uppermost empty regions that are sequentially stacked may be filled by the at least a portion of the electrode-dielectric film.

In example embodiments, a top electrode in the topmost blank area may extend into the recessed area and be connected to a next top electrode in the next top blank area. In this case, the method may further include forming sacrificial pads having a stepped structure by patterning the alternately stacked sacrificial layers and insulating layers. The sacrificial pads may be formed after forming the sacrificial spacers. When the sacrificial pads are formed, the connection portions of the sacrificial spacers positioned at the ends of the cutting region may be removed, and the sacrificial spacers may be separated from each other.

In example embodiments, the forming of the cutting region may include: forming a guide opening by patterning an uppermost insulating layer of the insulating layers; Conformally forming a spacer film on the substrate having the guide opening; And anisotropically etching the spacer layer and the top sacrificial layer to form sacrificial spacers on both inner walls of the cutting region and the guide opening.

In example embodiments, the forming of the cutting region may further include sequentially etching the next higher insulating layer among the insulating layers and the next higher sacrificial layer among the sacrificial layers using the sacrificial spacers as an etching mask.

According to the above-mentioned three-dimensional semiconductor memory element, the first outer wall of the top electrode can be covered by an extension of the electrode-dielectric film. As a result, the first outer wall of the uppermost electrode may be protected from an etching process or the like. As a result, the etching loss of the top electrode may be minimized to prevent the resistance of the top electrode from increasing. As a result, it is possible to realize a three-dimensional semiconductor memory device having excellent reliability and optimized for high integration.

1A is a plan view showing a three-dimensional semiconductor memory device according to the first embodiment of the present invention.
1B is a cross-sectional view taken along the line II ′ of FIG. 1A;
1C is a cross-sectional view taken along II-II 'of FIG. 1A;
FIG. 1D is an enlarged view of a portion A of FIG. 1B. FIG.
FIG. 1E is an enlarged view of a portion B of FIG. 1B; FIG.
Fig. 1F is a cross sectional view showing a modification of the three-dimensional semiconductor memory device according to the first embodiment of the present invention.
Fig. 2A is a plan view showing another modification of the three-dimensional semiconductor memory device according to the first embodiment of the present invention.
FIG. 2B is a sectional view taken along the line II ′ of FIG. 2A;
FIG. 3A is a cross-sectional view taken along the line II ′ of FIG. 1A to explain another modification of the three-dimensional semiconductor memory device according to the first embodiment of the present invention; FIG.
3B is an enlarged view of a portion C of FIG. 3A.
4 is a plan view showing still another modification of the three-dimensional semiconductor memory device according to the first embodiment of the present invention;
5A to 10A are plan views illustrating a method of manufacturing a three-dimensional semiconductor memory device according to the first embodiment of the present invention.
5B-10B are cross sectional views taken along the line II ′ of FIGS. 5A-10A, respectively.
5C-10C are cross-sectional views taken along II-II ′ of FIGS. 5A-10A, respectively.
11A and 12A are plan views illustrating a modification of the method of manufacturing the three-dimensional semiconductor memory device according to the first embodiment of the present invention.
11B and 12B are cross sectional views taken along the line II ′ of FIGS. 11A and 12A, respectively.
13 to 15 are cross-sectional views for explaining another modification of the method for manufacturing the three-dimensional semiconductor memory device according to the first embodiment of the present invention.
Fig. 16A is a plan view showing a three-dimensional semiconductor memory device according to the second embodiment of the present invention.
FIG. 16B is a sectional view taken along the line II ′ of FIG. 16A;
FIG. 16C is an enlarged view of a portion D of FIG. 16A; FIG.
FIG. 17 is a cross-sectional view taken along the line II ′ of FIG. 16A to illustrate one modification of the three-dimensional semiconductor memory device according to the second embodiment of the present invention; FIG.
FIG. 18A is a cross-sectional view taken along the line II ′ of FIG. 16A to illustrate another modification of the three-dimensional semiconductor memory device according to the second embodiment of the present invention; FIG.
FIG. 18B is an enlarged view of a portion E of FIG. 18A; FIG.
19A to 24A are plan views illustrating a method of manufacturing a three-dimensional semiconductor memory device according to the second embodiment of the present invention.
19B-24B are cross sectional views taken along the line II ′ of FIGS. 19A-24A, respectively.
Fig. 25 is a cross-sectional view for explaining a modification of the method for manufacturing the three-dimensional semiconductor memory device according to the second embodiment of the present invention.
Fig. 26 is a sectional view for explaining another modification of the method for manufacturing the three-dimensional semiconductor memory device according to the second embodiment of the present invention.
Fig. 27A is a plan view showing a three-dimensional semiconductor memory device according to the third embodiment of the present invention.
FIG. 27B is a sectional view taken along II ′ of FIG. 27A;
FIG. 27C is an enlarged view of a portion F in FIG. 27B. FIG.
Fig. 28A is a plan view showing one modification of the three-dimensional semiconductor memory device according to the third embodiment of the present invention.
FIG. 28B is a sectional view taken along II ′ of FIG. 28A;
FIG. 29 is a cross-sectional view taken along the line II ′ of FIG. 27A for explaining another modification of the three-dimensional semiconductor memory device according to the third embodiment of the present invention. FIG.
30A is a cross sectional view taken along the line II ′ of FIG. 27A in order to explain another modification of the three-dimensional semiconductor memory device according to the third embodiment of the present invention;
30B is an enlarged view of a portion G of FIG. 30A.
31A to 35B are plan views illustrating a method of manufacturing a three-dimensional semiconductor memory device according to the third embodiment of the present invention.
31B-35B are cross sectional views taken along the line II ′ of FIGS. 31A-35A, respectively.
36 and 37 are plan views illustrating a modification of the method of manufacturing the three-dimensional semiconductor memory device according to the third embodiment of the present invention.
38 is a cross-sectional view for explaining another modification of the method of manufacturing the three-dimensional semiconductor memory device according to the third embodiment of the present invention.
FIG. 39 is a block diagram schematically illustrating an example of an electronic system including a three-dimensional semiconductor memory device based on the technical idea of the present invention; FIG.
40 is a block diagram schematically showing an example of a memory card including a three-dimensional semiconductor memory device based on the technical idea of the present invention;

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more readily apparent from the following description of preferred embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the present specification, when it is mentioned that a film (or layer) is on another film (or layer) or substrate, it may be formed directly on another film (or layer) or substrate or a third film between them. In addition, in the drawings, sizes, thicknesses, etc. of components are exaggerated for clarity. It should also be understood that although the terms first, second, third, etc. have been used in various embodiments herein to describe various regions, films (or layers), etc., It should not be. These terms are merely used to distinguish any given region or film (or layer) from another region or film (or layer). Thus, the membrane referred to as the first membrane in one embodiment may be referred to as the second membrane in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. The expression 'and / or' is used herein to include at least one of the components listed before and after. Portions denoted by like reference numerals denote like elements throughout the specification.

(First embodiment)

FIG. 1A is a plan view illustrating a three-dimensional semiconductor memory device according to a first embodiment of the present invention, FIG. 1B is a cross-sectional view taken along the line II ′ of FIG. 1A, and FIG. 1C is along the line II-II ′ of FIG. 1A. It is a cross section taken.

1A, 1B, and 1C, an electrode structure may be disposed on the substrate 100. The electrode structure may include electrodes GSE1, GSE2, CE, SSE1, and SSE2 and insulating patterns 105a, 105nUa, and 105Ua that are alternately and repeatedly stacked. A plurality of the electrode structures may be arranged on the substrate 100. As disclosed in FIG. 1A, the electrode structures may extend side by side in a first direction. The first direction may correspond to the y-axis direction of FIG. 1A. The electrode structures may be laterally spaced apart from each other in a second direction perpendicular to the first direction. The second direction may correspond to the x-axis direction of FIG. 1A. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may include a well region doped with a dopant of a first conductivity type.

The electrodes GSE1, GSE2, CE, SSE2, and SSE1 in the electrode structure may include a plurality of cell electrodes CE that are sequentially stacked. In addition, the electrodes GSE1, GSE2, CE, SSE2, and SSE1 in the electrode structure may be grounded at least one floor interposed between a lowermost cell electrode and the substrate 100. The electrodes GSE1 and GSE2 may be included. In example embodiments, a plurality of layers of ground selection electrodes GSE1 and GSE2 may be disposed between the substrate 100 and the lowest cell electrode. For example, a first ground select electrode GSE1 may be disposed between the lowest cell electrode and the substrate 100, and a second ground select electrode GSE2 may be disposed at the lowest cell electrode and the first ground select electrode GSE1. It can be intervened in between. However, the present invention is not limited thereto. As illustrated in FIG. 1F, a layer of the ground selection electrode GSE may be interposed between the lowermost cell electrode and the substrate 100. Alternatively, three or more layers of ground selection electrodes may be interposed between the lowest cell electrode and the substrate 100.

1A, 1B, and 1C, the electrodes GSE1, GSE2, CE, SSE1, and SSE2 in the electrode structure may include a plurality of first string select electrodes SSE1. The plurality of first string select electrodes SSE1 are positioned at the same level from an upper surface of the substrate 100. The plurality of first string select electrodes SSE1 are laterally spaced apart. The plurality of first string select electrodes SSE1 may extend in parallel in the first direction. The first string selection electrodes SSE1 may be disposed over the uppermost cell electrode of the cell electrodes CE. More specifically, in the electrode structure, the plurality of first string selection electrodes SSE1 may be disposed on one topmost cell electrode CE. The first ground selection electrode SSE1 may also be one in the electrode structure. Accordingly, the plurality of first string select electrodes SSE1 may be disposed over one of the first ground select electrodes SSE1.

The electrode structure may include at least one layer of string selection electrode SSE1. In example embodiments, the electrode structure may include a plurality of string select electrodes SSE2 and SSE1 that are sequentially stacked and spaced apart from each other. For example, a second string select electrode SSE2 may be disposed between each of the first string select electrodes SSE1 and the uppermost cell electrode. The second string select electrodes SSE2 respectively disposed under the first string select electrodes SSE1 may be located at the same level from the upper surface of the substrate 100. In addition, the second string select electrodes SSE2 are laterally spaced apart. However, the present invention is not limited thereto. As disclosed in FIG. 1F, the electrode structure may include a single layer string select electrode SSE. Alternatively, the electrode structure may include string select electrodes stacked in three or more layers.

1A, 1B, and 1C, the first ground select electrode GSE1 corresponds to the lowest electrode among the electrodes GSE1, GSE2, CE, SSE2, and SSE1 stacked in the electrode structure. The first string selection electrode SSE1 corresponds to a top electrode among the electrodes GSE1, GSE2, CE, SSE2, and SSE1 stacked in the electrode structure. The second string selection electrode SSE2 corresponds to a next uppermost electrode among the electrodes GSE1, GSE2, CE, SSE2, and SSE1 stacked in the electrode structure.

The electrodes GSE1, GSE2, CE, SSE2, and SSE1 include a conductive material. For example, the electrodes GSE1, GSE2, CE, SSE2, and SSE1 may be formed of a doped semiconductor (ex, doped silicon, etc.), a metal (ex, tungsten, copper, aluminum, etc.), a conductive metal nitride (ex, nitride, etc.). Titanium, tantalum nitride, tungsten nitride, etc.), conductive metal-semiconductor compounds (ex, metal silicides, etc.), transition metals (ex, titanium, tantalum, etc.), and the like.

The insulating patterns 105a, 105nUa, and 105Ua may have a difference between the highest insulating pattern 105Ua and the first and second string select electrodes SSE1 and SSE2 disposed on the first string select electrode SSE1. It may include an insulation pattern 105nUa and insulation patterns 105a interposed between the cell electrodes CE and the ground select electrodes GSE1 and GSE2. The topmost insulating patterns 105Ua may be provided in plural and disposed on the plurality of first string select electrodes SSE1, respectively. The uppermost insulating patterns 105Ua may be located at the same level from the upper surface of the substrate 100. Similarly, a plurality of next higher insulating patterns 105nUa may be provided and disposed directly on the plurality of second string selection electrodes SSE2, respectively. The next higher insulating patterns 105nUa may also be positioned at the same level from the top surface of the substrate 100. The insulating patterns 105a, 105nUa, and 105Ua may include an oxide (eg, a high density plasma oxide and / or a high temperature oxide).

The electrode structure may further include a buffer dielectric pattern 103a interposed between the first string selection electrode SSE1 and the substrate 100. The buffer dielectric pattern 103a may be thinner than the insulating patterns 105a, 105nUa, and 105Ua. The insulating patterns 105a, 105nUa, and 105Ua may include an oxide or the like. The buffer dielectric pattern 103a may include an oxide or the like.

Vertical active patterns 120 may vertically penetrate the electrode structure. Each vertical active pattern 120 continuously penetrates the first string selection electrode SSE1 and the electrodes SSE2, CE, GSE1, and GSE2 stacked under each of the first string selection electrode SSE1. can do. The vertical active pattern 120 may be in the form of a hollow pipe or macaroni. In this case, a filling dielectric pattern 125 may fill a space surrounded by the vertical active pattern 120. Landing pads 130 may be disposed on the vertical active pattern 120 and the filling dielectric pattern 125. The landing pad 130 may be in contact with the vertical active pattern 120.

The vertical active pattern 120 may be in contact with the substrate 100. More specifically, the vertical active pattern 120 may be in contact with the well region formed in the substrate 100. The vertical active pattern 120 may be formed of the same semiconductor material as the substrate 100. For example, when the substrate 100 is a silicon substrate, the vertical active pattern 120 may be formed of silicon. The vertical active pattern 120 may be in a crystal state. The vertical active pattern 120 may be doped with the same type of dopant as the well region (ie, the dopant of the first conductivity type). Alternatively, the vertical active pattern 120 may be in an undoped state. The landing pad 130 may be formed of the same semiconductor material as the vertical active pattern 120. For example, the landing pad 130 may be formed of silicon. In example embodiments, a drain region doped with a dopant of a second conductivity type may be formed in at least the landing pad 130. The filling dielectric pattern 125 may include an oxide, nitride, and / or oxynitride.

As illustrated in FIGS. 1A and 1C, a plurality of the vertical active patterns 120 may include the first string selection electrode SSE1 and the electrodes SSE2, CE, GSE1, and GSE2 stacked thereunder. Can penetrate continuously. In a plan view, the vertical active patterns 120 penetrating the first string selection electrodes SSE1 may be arranged in the first direction to form one column. However, the present invention is not limited thereto. The vertical active patterns 120 penetrating each of the first string selection electrodes SSE1 may be arranged in a different form from a planar point of view.

An electrode-dielectric film 170 may be interposed between the sidewalls of the vertical active pattern 120 and the electrodes GSE1, GSE2, CE, SSE2, and SSE1. In an embodiment, at least a portion of the electrode-dielectric film 170 may extend to cover the top and bottom surfaces of the electrodes GSE1, GSE2, CE, SSE2, and SSE1. In this case, at least a portion of the electrode-dielectric film 170 between the vertical active pattern 120 and the first string selection electrode SSE1 is further extended to form a lower surface and an upper surface of the first string selection electrode SSE1. And one outer wall. According to an embodiment, as shown in FIG. 1B, an entirety of the electrode-dielectric film 170 between the vertical active pattern 120 and each of the electrodes GSE1, GSE2, CE, SSE2, and SSE1 may extend. .

Device isolation patterns 175 may be disposed on the substrate 100 adjacent to both sides of the electrode structure. That is, each device isolation pattern 175 may be disposed between adjacent electrode structures. As illustrated in FIG. 1A, the device isolation patterns 175 may extend side by side in the first direction in a plan view. The device isolation patterns 175 may include an oxide, nitride, and / or oxynitride.

The first string selection electrode SSE1 and the electrode-dielectric film 170 will be described in more detail with reference to FIG. 1D.

FIG. 1D is an enlarged view of a portion A of FIG. 1B.

1B and 1D, the first string select electrode SSE1 may have a first outer wall S1a and a second outer wall S1b facing each other. In this case, the electrode-dielectric film 170 between the vertical active pattern 120 and the first string selection electrode SSE1 extends to form a bottom surface, an upper surface, and the first outer wall of the first string selection electrode SSE1. (S1a) can be covered. An extension of the electrode-dielectric film 170 may contact the bottom surface, the top surface and the first outer wall S1a of the first string selection electrode SSE1. The second outer wall S1b of the first string selection electrode SSE1 may not be covered by an extension of the electrode-dielectric film 170. In example embodiments, the second outer sidewall S1b of the first string select electrode SSE1 may be in contact with the device isolation pattern 175.

The first string select electrode SSE1 may have an inner wall InS1 adjacent to a sidewall of the vertical active pattern 120. As illustrated in FIGS. 1A to 1D, an inner wall InS1 of the first string selection electrode SSE1 may have a hole shape surrounding a sidewall of the vertical active pattern 120. The electrode-dielectric film 170 between the vertical active pattern 120 and the first string selection electrode SSE1 may have a sidewall of the vertical active pattern 120 and an inner wall InS1 of the first string selection electrode SSE1. May be intervened).

Similarly, the second string select electrode SSE2 may have a first outer wall S2a and a second outer wall S2b facing each other. The first outer wall S2a and the second outer wall S2b of the second string select electrode SSE2 are aligned with the first outer wall S1a and the second outer wall S1b of the first string select electrode SSE1, respectively. Can be. The electrode-dielectric film 170 between the vertical active pattern 120 and the second string select electrode SSE2 extends to form a bottom surface, an upper surface, and a first outer wall S2a of the second string select electrode SSE2. Can cover. An extension portion of the electrode-dielectric film 17 between the vertical active pattern 120 and the second string select electrode SSE2 may be formed at a lower surface, an upper surface, and a first outer wall S2a of the second string select electrode SSE2. Can be contacted. An extension of the electrode-dielectric film 17 between the vertical active pattern 120 and the second string select electrode SSE2 may not cover the second outer wall S2b of the second string select electrode SSE2. In example embodiments, the second outer sidewall S2b of the second string select electrode SSE2 may be in contact with the device isolation pattern 175. The second string selection electrode SSE2 may also have an inner wall InS2 surrounding the vertical active pattern 120 and having a hole shape.

In example embodiments, the next higher insulation pattern 105 nUa may have a first outer wall and a second outer wall that face each other. First and second outer walls of the next higher insulating pattern 105nUa may be adjacent to the first and second outer walls S1a and S1b of the first string select electrode SSE1, respectively. An extension of the electrode-dielectric film 170 covering the first outer wall S1a of the first string selection electrode SSE1 extends downward along the first outer wall of the next higher insulating pattern 105nUa to form the second string. It may be connected to an extension of the electrode-dielectric film 170 covering the first outer wall S2a of the selection electrode SSE2.

The non-sacrificial pattern 150a may be disposed on one side of the first and second string select electrodes SSE1 and SSE2. In other words, the non-sacrificial pattern 150a is disposed between the uppermost insulating patterns 105Ua, between the first string select electrodes SSE1, between the next higher insulating patterns 105nUa, and the second string select electrodes. It may be disposed in the cutting area 140 defined between (SSE2). Can be placed in. The non-sacrificial pattern 150a may be disposed on the top cell electrode.

As illustrated in FIG. 1D, the horizontal distance HD between the non-sacrificial pattern 150a and the first outer wall of the next higher insulating pattern 105nUa is an electrode located on an upper surface of the first string selection electrode SSE1. It may be equal to or smaller than twice the thickness T of the dielectric film 170. Accordingly, the electrode-dielectric film 170 may fill a space between the next higher insulating pattern 105nUa and the non-sacrificial pattern 150a. The first string select electrode SSE1 may be separated from the second string select electrode SSE1 below.

The first string selection electrode SSE1 may be disposed in the uppermost empty region 160U defined between the uppermost insulating pattern 105Ua and the next upper insulating pattern 105nUa. The second string select electrode SSE1 may be disposed in the next higher blank area 160nU defined between the next higher insulating pattern 105nUa and the insulating pattern 105a immediately below it. In this case, a portion of the electrode-dielectric film 170 covering at least the first outer walls S1a and S2a of the first and second string selection electrodes SSE1 and SSE2 may be formed in the uppermost empty region 160U and the next higher bin. It may be disposed outside the region 160nU. As a result, widths of the first and second string select electrodes SSE1 and SSE2 may be increased, thereby lowering the resistance of the first and second string select electrodes SSE1 and SSE2.

A residual sacrificial spacer 145r may be disposed between the topmost insulating pattern 105Ua and the non-sacrificial pattern 150a on one outer wall of the topmost insulating pattern 105Ua. The remaining sacrificial spacer 145r may be disposed on an extension of the electrode-dielectric film 170 covering the first outer wall S1a of the first string select electrode SSE1. In example embodiments, the thickness of the remaining sacrificial spacer 145r may be substantially the same as the horizontal distance HD based on the one outer wall of the uppermost insulating pattern 105Ua.

The remaining sacrificial spacer 145r may include a dielectric material having an etch selectivity with respect to the insulating patterns 105a, 105nUa and 105Ua and the non-sacrificial pattern 150a. For example, when the insulating patterns 105a, 105nUa, 105Ua and the non-sacrificial pattern 150a are formed of high density plasma oxide and / or high temperature oxide, the remaining sacrificial spacers 145r may include nitride, oxide, PE— Oxide, and / or a low temperature oxide. The low temperature oxide means an oxide formed at a process temperature from room temperature to about 600 ° C. However, the present invention is not limited thereto. The insulating patterns 105a, 105nUa, 105Ua, the non-sacrificial pattern 150a, and the remaining sacrificial spacers 145r may be formed of other materials.

1A and 1B, a pair of remaining sacrificial spacers 145r may be disposed on both inner walls of the cutting region 140, respectively. As described above, each remaining sacrificial spacer 145r may be interposed between the non-sacrificial pattern 150a and each inner wall of the cutting region 140. As illustrated in FIG. 1A, the pair of remaining sacrificial spacers 145r may extend side by side in the first direction. According to an exemplary embodiment, ends of the pair of remaining sacrificial spacers 145r may extend from the end of the cutting region 140 and be connected to each other in a plan view.

As illustrated in FIG. 1B, in contrast to the first and second string selection electrodes SSE1 and SSE2, both outer walls CE_Sa and CE_Sb of the cell electrode CE are formed in the electrode. It may not be covered by the dielectric film 170. Similarly, both outer sidewalls GSE_Sa and GSE_Sb of each of the ground selection electrodes GSE1 and GSE2 may not be covered by the electrode-dielectric film 170. In example embodiments, the first and second outer walls CE_Sa and CE_Sb of each cell electrode CE may contact the pair of device isolation patterns 175 disposed on both sides of the electrode structure. have. In addition, the first non-second outer walls GSE_Sa and GSE_Sb of the ground selection electrodes GSE1 and GSE2 may also be in contact with the pair of device isolation patterns 175 disposed on both sides of the electrode structure. . Each cell electrode CE may include inner walls that respectively surround sidewalls of the vertical active patterns 120 penetrating through the plurality of first string selection electrodes SSE1 included in the electrode structure. Can be. Each of the ground selection electrodes GSE1 and GSE2 may also include inner walls that respectively surround sidewalls of the vertical active patterns 120 passing through the plurality of first string selection electrodes GSE1.

Next, the electrode-dielectric film 170 will be described in detail with reference to FIG. 1E.

FIG. 1E is an enlarged view of a portion B of FIG. 1B.

1B and 1E, the electrode-dielectric film 170 may include a tunnel dielectric film TDL, a charge storage layer SL, and a blocking dielectric film BDL. The tunnel dielectric layer TDL is adjacent to the vertical active pattern 120, and the blocking dielectric layer BDL is adjacent to each of the electrodes GSE1, GSE2, CE, SSE2, and SSE1, and the charge storage layer SL ) Is interposed between the tunnel dielectric layer TDL and the blocking dielectric layer BDL. The tunnel dielectric layer TDL may include an oxide layer and / or an oxynitride layer. The charge storage layer SL may include a dielectric layer having traps capable of storing charge. For example, the charge storage layer TDL may include a nitride layer and / or a metal oxide layer (eg, a hafnium oxide layer). The blocking dielectric layer BDL may include a high dielectric layer (eg, a metal oxide layer such as a hafnium oxide layer and / or an aluminum oxide layer) having a higher dielectric constant than the tunnel dielectric layer TDL. In addition, the blocking dielectric layer BDL may further include a barrier dielectric layer (eg, an oxide layer, etc.) having an energy band gap larger than the energy band gap of the high dielectric layer. The barrier dielectric layer may be interposed between the high dielectric layer and the charge storage layer SL. 1A to 1E, all of the tunnel dielectric layer TDL, the charge storage layer SL, and the blocking dielectric layer BDL in the electrode-dielectric layer 170 extend to each other. The lower and upper surfaces of the electrodes GSE1, GSE2, CE, SSE2 and SSE1 may be covered. In addition, extensions of the electrode-dielectric film 170 covering the first outer walls S1a and S2a of the string selection electrodes SSE1 and SSE2 may include the tunnel dielectric film TDL, the charge storage layer SL, and the blocking dielectric film. May include extensions of (BDL).

1A, 1B, and 1C, a common source region CS may be disposed in the substrate 100 between the electrode structures. The common source region CS may be doped with a dopant of the second conductivity type. The common source region CS may be formed in a well region of the substrate 100. Each device isolation pattern 175 may be disposed on each common source region CS.

As illustrated in FIGS. 1A and 1C, each of the electrodes GSE1, GSE2, CE, SSE2, and SSE1 stacked in the electrode structure may have an electrode pad EP. The electrode pads EP of the electrodes GSE1, GSE2, CE, SSE2, and SSE1 stacked in the electrode structure may be implemented in a stepped structure. The electrode pads EP of the stacked electrodes GSE1, GSE2, CE, SSE2, and SSE1 may have a downhill staircase structure in the first direction. Operating voltages may be provided to the electrodes GSE1, GSE2, CE, SSE2, and SSE1 through the electrode pads EP. For example, an operating voltage may be provided to the electrodes GSE, GSE1, CE, SSE2, and SSE1 through conductive plugs connected to the electrode pads EP.

One vertical cell string may be implemented in each of the vertical active patterns 120. The vertical cell string may include cell transistors connected in series. The vertical cell string further includes at least one ground select transistor connected in series to one end of the series connected cell transistors, and at least one string select transistor connected in series to the other end of the series connected cell transistors. can do. When the vertical cell string includes a plurality of the ground select transistors, the ground select transistors in the vertical cell string may be connected in series. Similarly, when the vertical cell string includes a plurality of string select transistors, string select transistors in the vertical cell string may also be connected in series.

Each cell transistor may be defined at an intersection point of the vertical active pattern 120 and each cell electrode CE, and the ground select transistors may be formed in the vertical active pattern 120 and the ground select electrodes. GSE1, GSE2) may be defined at the intersections of each. The string select transistors may be defined at intersections of the vertical active pattern 120 and the string select electrodes SSE1 and SSE2, respectively. The electrode-dielectric film 170 between each cell electrode CE and the vertical active pattern 120 may correspond to an information storage film of the cell transistor. The electrode-dielectric film 170 between each of the string select electrodes SSE1 and SSE2 and the vertical active pattern 120 may correspond to a gate dielectric layer of the string select transistor, and each of the ground select electrodes GSE1 and GSE2. And the electrode-dielectric layer 170 between the vertical active patterns 120 may correspond to the gate dielectric layer of the ground selection transistor. The ground, cell and string select transistors in the vertical cell string may be sequentially stacked, and the ground, cell and string select transistors in the vertical cell string may be vertically defined on sidewalls of the respective vertical active patterns 120. Each of the channel regions may be included. In operation of a three-dimensional semiconductor memory device, inversion layers are formed next to the insulating patterns 105a, 105nUa and 105Ua by the fringe field of the respective electrodes GSE1, GSE2, CE, SSE2 and SSE1. A portion of the sidewall of the vertical active pattern 120 located at may be generated. The inversion layers may correspond to sources / drains of the ground, cell, and string select transistors.

1A to 1C, a capping dielectric pattern 135a may be disposed on the electrode pads EP in the electrode structure. In addition, the capping dielectric pattern 135a may be disposed on the uppermost insulating patterns 105Ua in the electrode structure. In this case, the capping dielectric pattern 135a may have sidewalls aligned with both outer walls of the uppermost insulating patterns 105Ua. According to an embodiment, the remaining sacrificial spacers 145r may extend upward and be disposed on the sidewalls of the capping dielectric pattern 135a. The capping dielectric pattern 135a may include a dielectric material having an etch selectivity with respect to the remaining sacrificial spacers 145r. For example, the capping dielectric pattern 135a may include an oxide (eg, a high density plasma oxide and / or a high temperature oxide). The non-sacrificial pattern 150a may extend upward and may be disposed between sidewalls of the capping dielectric pattern 135a. In addition, the non-sacrificial pattern 150a may further extend to cover the top surface of the capping dielectric pattern 135a. In this case, the non-sacrificial pattern 150a may have sidewalls aligned with both outer walls of the uppermost cell electrode. However, the present invention is not limited thereto. The non-sacrificial pattern 150a may not cover the upper surface of the capping dielectric pattern 135a. The device isolation patterns 175 may extend upward. Thus, the capping dielectric pattern 135a and the non-sacrificial pattern 150a may be disposed between the pair of adjacent device isolation patterns 175.

The wires 190 may extend side by side in the second direction. The wiring 190 may be electrically connected to the vertical active pattern 120. For example, the wiring 190 may be electrically connected to the vertical active pattern 120 by a contact plug 180 passing through the non-sacrificial pattern 150a and the capping dielectric pattern 135a. The contact plug 180 may be connected to the landing pad 130. Each wire 190 may be electrically connected to a plurality of vertical active patterns 120 arranged in the second direction. The wires 190 may correspond to bit lines. The wires 190 may be formed of a metal (ex, tungsten, copper, aluminum, etc.), a conductive metal nitride (ex, titanium nitride, tantalum nitride, tungsten nitride, etc.), or a transition metal (ex, titanium, tantalum, etc.). It may include at least one. The contact plugs 180 may include a metal (ex, tungsten, copper, aluminum, etc.), a conductive metal nitride (ex, titanium nitride, tantalum nitride, tungsten nitride, etc.), or a transition metal (ex, titanium, tantalum, etc.). It may include at least one.

According to the three-dimensional semiconductor memory device described above, the first outer walls S1a and S2a of the string selection electrodes SSE1 and SSE2 are covered by the electrode-dielectric film 170. As a result, the first outer walls S1a and S2a of the string selection electrodes SSE1 and SSE2 may be protected from an etching process. In addition, at least a portion of the electrode-dielectric film 170 covering the first outer walls S1a and S2a is disposed outside the uppermost and next uppermost empty regions 160U and 160nU, thereby forming the string selection electrodes SSE1. , SSE2) can be increased. As a result, the resistances of the string selection electrodes SSE1 and SSE2 may be reduced. As a result, a three-dimensional semiconductor memory device having excellent reliability and optimized for high integration can be realized.

FIG. 2A is a plan view showing another modification of the three-dimensional semiconductor memory device according to the first embodiment of the present invention, and FIG. 2B is a sectional view taken along the line II ′ of FIG. 2A.

2A and 2B, an end portion of the cutting region 140 and a connection portion of the remaining sacrificial spacers 145r in the cutting region 140 of FIG. 1A may be removed. Thus, as disclosed in FIGS. 2A and 2B, the sacrificial spacers 145r ′ in the cutting region 140a may be separated from each other. In this case, the non-sacrificial pattern 150a 'may be disposed under the capping dielectric pattern 135a'. The capping dielectric pattern 135a ′ may be disposed outside the filling region 140a. As illustrated in FIG. 2A, the non-sacrificial pattern 150a ′ may be limitedly disposed on the first string selection electrodes SSE1 and SSE2 and the cutting region 140a. That is, the non-sacrificial pattern 150a ′ may not cover the electrode pads EP of the electrodes SSE2, CE, GSE2, and GSE1 disposed under the first string selection electrodes SSE1. The capping dielectric pattern 135a ′ may cover electrode pads EP of the first string select electrodes SSE1 and the electrodes SSE2, CE, GSE2, and GSE1 below.

According to one embodiment, as shown in FIG. 2B, the upper surface of the landing pad 130 on the vertical active pattern 120 may be coplanar with the upper surface of the non-sacrificial pattern 150a ′. However, the present invention is not limited thereto. An upper surface of the landing pad 130 may be coplanar with an upper surface of the uppermost insulating pattern 105Ua.

FIG. 3A is a cross-sectional view taken along line II ′ of FIG. 1A to illustrate another modified example of the three-dimensional semiconductor memory device according to the first embodiment of the present invention, and FIG. 3B is an enlarged view of portion C of FIG. 3A. Drawing.

3A and 3B illustrate an electrode-dielectric film 170a between the vertical active pattern 120 and each of the electrodes GSE1, GSE2, CE, SSE2, and SS1. The first portion 165a and the second portion 165b may be formed. It may include. In this case, the first portion 165a of the electrode-dielectric film 170a may extend vertically to be interposed between the vertical active pattern 120 and the insulating patterns 105a, 105nUa, and 105Ua. The second portion 165b of the electrode-dielectric film 170a may extend to cover top and bottom surfaces of the electrodes GSE1, GSE2, CE, SSE2, and SSE1. In this case, the second portion 165b of the electrode-dielectric film 170a between the vertical active pattern 120 and the first string select electrode SSE1 extends to form a first outer wall of the first string select electrode SSE1. Can cover. Similarly, the second portion 165b of the electrode-dielectric film 170a between the vertical active pattern 120 and the second string select electrode SSE2 is extended to extend the first portion of the second string select electrode SSE2. The outer walls can be covered. In this case, the horizontal distance HD between the non-sacrificial pattern 150a and the next upper insulating pattern 105nUa is equal to the thickness of the second portion 165b on the upper surface of the first string selection electrode SSE1. It may be equal to or less than twice T ').

The first portion 165a of the electrode-dielectric film 170a may include at least a portion of the tunnel dielectric film TDL described with reference to FIG. 1E. The second portion 165b of the electrode-dielectric film 170a may include at least a portion of the blocking dielectric film BDL described with reference to FIG. 1E. In this case, any one of the first portion 165a and the second portion 165b includes the charge storage layer SL described with reference to FIG. 1E. For example, the first portion 165a may include the tunnel dielectric layer TDL, the charge storage layer SL, and the barrier dielectric layer of the blocking dielectric layer BDL. It may include a high dielectric film of the blocking dielectric film (BDL). However, the present invention is not limited thereto. The first portion 165a and the second portion 165b of the electrode-dielectric film 170a may be configured in other forms.

4 is a plan view showing still another modification of the three-dimensional semiconductor memory device according to the first embodiment of the present invention.

Referring to FIG. 4, the odd-numbered landing pads 130 among the landing pads 130 on the vertical active patterns penetrating the first string select electrode SSE1 may be formed from the even-numbered landing pads 130. It may be offset in the second direction. The vertical active patterns may be aligned under the landing pads 130, respectively. As a result, the vertical active patterns penetrating the first string selection electrodes SSE1 may be arranged in a zigzag form along the first direction in a plan view.

5A to 10A are plan views illustrating a method of manufacturing a 3D semiconductor memory device according to a first embodiment of the present invention, and FIGS. 5B to 10B are taken along the line II ′ of FIGS. 5A to 10A, respectively. 5C to 10C are cross sectional views taken along II-II 'of FIGS. 5A to 10A, respectively.

5A, 5B, and 5C, a buffer dielectric layer 103 may be formed on the substrate 100. Sacrificial layers 110, 110nU and 110U and insulating layers 105, 105nU and 105U may be alternately and repeatedly stacked on the buffer dielectric layer 103. The sacrificial layers 110, 110nU, and 110U may be formed of a material having an etch selectivity with respect to the insulating layers 105, 105nU, and 105U. For example, each of the insulating films 105, 105 nU, and 105U may be formed of an oxide film (eg, a high density plasma oxide film and / or a high temperature oxide film), and each of the sacrificial films 110, 110 nU, and 110U may be a nitride film. It can be formed as.

The sacrificial pads 110P of the sacrificial layers 110, 110nU and 110U may be formed by patterning the insulating layers 105, 105nU and 105U and the sacrificial layers 110, 110nU and 110U. The insulating layers 105, 105 nU and 105U and the sacrificial layers 110, 110 nU and 110U may be etched using a mask pattern as a consumable etching mask. For example, a mask pattern defining a sacrificial pad 110P of the lowest sacrificial layer 110 is formed among the sacrificial layers 110, 110nU, and 110U, and the insulating layers 105, 105nU, and 105U are formed using the mask pattern as an etching mask. And the sacrificial layers 110, 110nU, and 110U may be etched. As a result, the sacrificial pad 110P of the lowest sacrificial layer may be formed. Subsequently, the mask pattern may be recessed to reduce the width of the mask pattern. The sacrificial layers 110, 110nU and 110U and the insulating layers 105, 105nU and 105U on the lowest sacrificial layer may be etched using the recessed mask pattern as an etching mask. As a result, the sacrificial pad 110P of the sacrificial layer 110 stacked second from the substrate 100 may be formed, and the sacrificial pad 110P of the lowest sacrificial layer may be exposed. The sacrificial pads 110P having a stepped structure may be repeatedly formed by repeatedly performing the recess process of the mask pattern and the etching process of the insulating layers 105, 105 nU and 105U and the sacrificial layers 110, 110 nU and 110U. Can be formed.

Holes 115 may be formed through the insulating layers 105, 105 nU and 105U, the sacrificial layers 110, 110 nU and 110U, and the buffer dielectric layer 103. Vertical active patterns 120, charging dielectric patterns 125, and landing pads 130 may be formed in the holes 115. Subsequently, a capping dielectric layer 135 may be formed to cover the entire surface of the substrate 100. The capping dielectric layer 135 may include a dielectric material having an etching selectivity with respect to the sacrificial layers 110, 110nU, and 110U. For example, the capping dielectric layer 135 may be formed of an oxide layer. 5A, 5B, and 5C, reference numeral 105U denotes the highest insulating film 105U among the insulating films, and reference numeral 105nU denotes the next higher insulating film 105nU. Reference numeral 110U denotes the uppermost insulating film 105U, and reference numeral 110nU denotes the next higher insulating film 110nU.

6A, 6B, and 6C, the capping dielectric layer 135, the uppermost insulating layer 105U, the uppermost sacrificial layer 110U, the next upper insulating layer 105nU, and the next upper sacrificial layer 110nU are patterned and cut. Region 140 may be formed. As illustrated in FIG. 6A, the cutting area 140 may have a groove shape extending in a first direction. The cutting region 140 may cross the sacrificial pads 110P of the top and next top sacrificial layers 110U and 110nU. However, the present invention is not limited thereto. The cutting region 140 may cross the sacrificial pads 110P of all of the stacked sacrificial layers 110, 110U, and 110nU.

The spacer layer 145 may be conformally formed on the substrate 100 having the cutting region 140. Thus, the spacer layer 145 may be formed on the inner surface of the cutting region 140 and the upper surface of the capping dielectric layer 135 to have a substantially uniform thickness. The spacer layer 145 may have a first thickness Td.

The spacer layer 145 may include a dielectric material having an etching rate greater than that of the insulating layers 105, 105nU, and 105U. In example embodiments, the spacer layer 145 is greater than or equal to 10% of the etching rate of the sacrificial layers 110, 110nU, and 110U, and 200 times the etching rate of the sacrificial layers 110, 110nU, and 110U. It may contain less than or equal to dielectric material. For example, the spacer layer 145 may be formed of a nitride film, an oxynitride film, an oxide film formed by PE-CVD, and / or a low temperature oxide film. The low temperature oxide film may be an oxide film formed at a process temperature of about room temperature to about 600 ℃.

7A, 7B, and 7C, the spacer layer 145 is etched by a front anisotropic etching process, so that a pair of sacrificial spacers 145a are formed on both inner walls of the cutting region 140. Can be formed. As illustrated in FIG. 7A, the pair of sacrificial spacers 145a may be connected to each other at the end of the cutting region 140.

Subsequently, a non-sacrificial film 150 may be formed on the entire surface of the substrate 100 to fill the cutting region 140. The non-sacrificial layer 150 may be formed of a dielectric material having an etching rate smaller than that of the sacrificial spacers 145a. In example embodiments, the non-sacrificial layer 150 may include a dielectric material having an etching rate smaller than 10% of an etching rate of the sacrificial layers 110, 110nU, and 110U. For example, the non-sacrificial film 150 may be formed of a high density plasma oxide film and / or a high temperature oxide film. According to an embodiment, the non-sacrificial layer 150 may be planarized. In this case, the planarized non-sacrificial film may be limitedly disposed in the cutting region 140. In the following description, the case where the planarization process of the non-sacrificial film 150 is omitted will be described.

According to the above description, after the hole 115 and the vertical active pattern 120 are formed, the cutting region 140, the sacrificial spacers 145a, and the non-sacrificial layer 150 may be formed. . However, the present invention is not limited thereto. After the cutting region 140, the sacrificial spacers 145a, and the non-sacrificial layer 150 are formed, the holes 115 and the vertical active pattern 120 may be formed.

8A, 8B, and 8C, the non-sacrificial film 150, the capping dielectric film 135, the insulating films 105U, 105nU, and 105, the sacrificial films 110U, 110nU, and 110, and the buffer dielectric film ( 103 may be continuously patterned to form trenches 155. The cutting region 140 may be disposed between a pair of adjacent trenches 155. A mold pattern may be formed between the adjacent pair of trenches 155. A plurality of mold patterns may be formed on the substrate 100 by being separated by the trenches 155. Each mold pattern may include sacrificial patterns 110a, 110nUa and 110Ua and alternating patterns 105a, 105nUa and 105Ua that are alternately stacked. In addition, each mold pattern may further include a capping dielectric pattern 135a, the cutting region 140, the sacrificial spacers 145a, and a non-sacrificial pattern 150a filling the cutting region 140. In addition, each mold pattern may further include a buffer dielectric pattern 103a interposed between the lowest sacrificial pattern and the substrate 100.

By forming the trenches 155 after the cutting region 140, each mold pattern may include a plurality of topmost insulating patterns 105Ua positioned at the same level. Similarly, each mold pattern may include a plurality of top sacrificial patterns 110Ua, a plurality of next higher insulating patterns 105nUa, and a plurality of next top sacrificial patterns 110nUa. One sacrificial pattern 110a may be disposed on each layer under the cutting area 140.

As disclosed in FIG. 8A, the trenches 155 may extend side by side in the first direction. The sacrificial pads 110P of the sacrificial patterns 110a, 110nUa and 110Ua in each mold pattern may be spaced apart from the sacrificial pads 110P of the sacrificial patterns 110a, 110nUa and 110Ua in the adjacent mold pattern. .

9A, 9B, and 9C, the sacrificial patterns 110a, 110nUa, and 110Ua exposed to the trenches 155 may be removed to form empty regions 160, 160nU, and 160U. . In this case, the sacrificial spacers 145a next to the top and next top sacrificial patterns 110Ua and 110nUa may also be removed. As a result, the recess regions 162 may be formed. By having an etch selectivity with respect to the sacrificial spacers 145a, the non-sacrificial pattern 150a remains.

The topmost empty regions 160U formed by removing the top sacrificial patterns 110Ua may be separated from each other by the non-sacrificial pattern 150a. Similarly, the next higher blank areas 160nU formed by removing the next higher sacrificial patterns 110nUa may be separated from each other by the non-sacrificial pattern 150a. Each recessed region 162 is connected to a topmost empty region 160U and a next higher empty region 160nU adjacent to each recessed region 162. That is, each topmost bin area 160U may be in communication with a next top bin area 160nU under each topmost bin area 160U by the recess area 162.

In example embodiments, remaining sacrificial spacers 145r may remain on the recess regions 162. However, the present invention is not limited thereto. When the recess regions 162 are formed, all of the sacrificial spacers 145a may be removed.

10A, 10B, and 10C, an electrode-dielectric film 170 is conformally formed on the substrate 100 having the empty regions 106, 106nU, and 106U and the recess region 162. Can be. Accordingly, the electrode-dielectric film 170 may be formed on the inner surfaces of the empty regions 106, 106nU, and 106U with a substantially uniform thickness. In addition, the electrode-dielectric film 170 may be formed in the recess region 162.

In example embodiments, the thickness Td of the spacer layer 145 disclosed in FIGS. 7A to 7C may be substantially equal to or smaller than twice the thickness of the electrode-dielectric layer 170. As a result, a portion of the recess region 162 positioned next to the next higher insulating pattern 105 nUa may be filled by the electrode-dielectric film 170. In addition, another portion of the recess region 162 next to the uppermost insulating pattern 105Ua may also be filled by the electrode-dielectric film 170.

Subsequently, a conductive film may be formed on the substrate 100 to fill the empty regions 106, 106 nU, and 106U. Subsequently, the conductive layer may be etched to form electrodes GSE1, GSE2, CE, SSE2, and SSE1 filling the empty regions 106, 106nU, and 106U, respectively. Subsequently, the electrode-dielectric film 170 disposed on the inner wall of the trench 155 may be removed. The recess region 162 next to the next higher insulating pattern 105 nUa is filled by the electrode-dielectric film 170, so that the second string select electrode SSE2 and the first string select electrode SSE1 stacked in turn are mutually stacked. Can be separated. In addition, by filling other portions of the recess region 162 next to the uppermost insulating pattern 105Ua, the first string select electrodes SSE1 disposed on both sides of the cutting region 140 may also be separated from each other. have. By forming the electrodes GSE1, GSE2, CE, SSE2, and SSE1, the electrode structure described with reference to FIGS. 1A through 1E may be formed.

The common source region CS may be formed by providing a second conductivity type dopant in the substrate 100 under the trench 155. The common source region CS may be formed after forming the electrodes GSE1, GSE2, CE, SSE2, and SSE1. Alternatively, the common source region CS may be formed after forming the mold pattern and before forming the empty regions 106, 106nU, and 106U. Alternatively, the common source region CS may be formed after forming the empty regions 106, 106nU, and 106U and before forming the electrodes GSE1, GSE2, CE, SSE2, and SSE1. have.

Subsequently, device isolation patterns 175, which are disclosed in FIGS. 1A to 1E, may be formed in the trenches 155, respectively. Subsequently, the contact plugs 180 and the wirings 190 disclosed in FIGS. 1A to 1E may be formed. As a result, the three-dimensional semiconductor memory device disclosed in FIGS. 1A to 1E can be implemented.

According to the method of manufacturing the 3D semiconductor memory device described above, the non-sacrificial film 150 is formed after patterning the top and next top sacrificial layers 110U and 110nU to form the cutting region 140. Afterwards, the trenches 155 are formed to form the sacrificial patterns 110a, 110nUa and 110Ua, and the sacrificial patterns 110a, 110nUa and 110Ua are removed to remove the empty regions 160, 160nU, 160U). As a result, the uppermost empty regions 160U separated by the non-sacrificial pattern 150a are formed. In addition, the second upper empty regions 160nU separated by the non-sacrificial pattern 150a may be formed. Accordingly, the first string select electrodes SSE1 and the second string select electrodes SSE2 separated from each other in the electrode structures may be formed of the cell electrodes CE and the ground select electrodes GSE1 and GSE2. And may be formed substantially simultaneously. As a result, the first outer walls (S1a and S2a of FIG. 1D) of the first and second string select electrodes SSE1 and SSE2 adjacent to the non-sacrificial pattern 150a may be protected from an etching process. As a result, the resistance of the first and second string select electrodes SSE1 and SSE2 may be reduced by minimizing the loss caused by the etching process of the first and second string select electrodes SSE1 and SSE2.

In addition, when the sacrificial spacers 145a are formed on both inner sidewalls of the cutting region 140, and the empty regions 106, 106nU, and 106U are formed, at least the sacrificial spacers 145a are formed. Portions may be removed to form the recess regions 162. As a result, the electrode-dielectric film 170 is formed in the recess regions 162, thereby increasing widths of the string selection electrodes SSE1 and SSE2. As a result, the resistance of the string selection electrodes SSE1 and SSE2 may be further lowered.

Meanwhile, according to the manufacturing method described above, after the sacrificial pads 110P are formed, the cutting regions 140 may be formed. Alternatively, the sacrificial pads may be formed after the cutting region is formed. This will be described with reference to the drawings.

11A and 12A are plan views illustrating a modification of the method of manufacturing the 3D semiconductor memory device according to the first embodiment of the present invention, and FIGS. 11B and 12B are I-I of FIGS. 11A and 12A, respectively. Are cross-sectional views taken along.

11A and 11B, the cutting region 140 may be formed by successively patterning the uppermost insulating film 105U, the uppermost sacrificial film 110U, the next higher insulating film 105nU, and the next higher sacrificial film 110nU. . Sacrificial spacers 145r may be formed on both inner walls of the cutting area 140. In this case, as shown in FIG. 11A, at the end of the cutting region 140, the ends of the sacrificial spacers 145r may be connected to each other. Subsequently, the non-sacrificial layer 150 may be formed to fill the cutting region 140.

Holes 115 may be formed through the non-sacrificial layer 150, the insulating layers 105U, 105nU, and 105, the sacrificial layers 110U, 110nU, and 110, and the buffer dielectric layer 103. Vertical active patterns 120, charging dielectric patterns 125, and landing pads 130 may be formed in the holes 115. According to an embodiment, the holes 115 and the vertical active pattern 120 may be formed first, and then the cutting region 140 and the non-sacrificial layer 150 may be formed. In this case, the non-sacrificial layer 150 may cover the landing pad 130 on the vertical active pattern 120.

12A and 12B, after the cutting region 140 and the non-sacrificial film 150 are formed, the non-sacrificial film 150, the insulating films 105U, 105nU, 105, and the sacrificial films 110U , 110nU, 110 may be patterned to form sacrificial pads 110P having a stepped structure. In this case, an end portion of the cutting region 140 and a connected portion of the sacrificial spacers 145a may be removed together. Accordingly, the sacrificial spacers 145a ′ on both inner walls of the cutting region 140a may be separated from each other. Immediately after forming the sacrificial pads 110P, the non-sacrificial film 150 'may not cover the sacrificial pads 110P of the sacrificial films 110nU and 110 positioned below the top sacrificial film 110U. have.

After forming the sacrificial pads 110P, a capping dielectric layer 135 ′ may be formed on the entire surface of the substrate 100. Subsequently, the process of forming the trenches 155 described with reference to FIGS. 8A through 8C, and the process of forming the empty regions 106U, 106nU and 106 and the recess regions 162 described with reference to FIGS. 9A through 9C. And the process of forming the electrode-dielectric film 170 and the electrodes GSE1, GSE2, CE, SSE2, and SSE1 described with reference to FIGS. 10A to 10C may be sequentially performed. Thus, the three-dimensional semiconductor memory device disclosed in FIGS. 2A and 2B can be implemented.

13 to 15 are cross-sectional views for explaining another modification of the method of manufacturing the 3D semiconductor memory device according to the first embodiment of the present invention.

Referring to FIG. 13, before forming the vertical active pattern 120, the first portion 165a of the electrode-dielectric film may be formed on the inner wall of the hole 115. The first portion 165a of the electrode-dielectric film formed on the bottom surface of the hole 115 may be removed. As a result, the vertical active pattern 120 formed after the formation of the first portion 165a may be in contact with the substrate 100. The capping dielectric layer 135 may be formed. The capping dielectric layer 135 may cover the landing pad 130. After the capping dielectric layer 135 is formed, the processes described with reference to FIGS. 6A to 6C, 7A to 7C, 8A to 8C, and 9A to 9C may be performed. Thus, 14 empty regions 106U, 106nU, 106 and recess regions 162 may be formed.

Referring to FIG. 14, the empty regions 106U, 106nU, and 106 may expose portions of the first portion 165a of the electrode-dielectric film disposed on the sidewall of the vertical active pattern 120, respectively. have.

Referring to FIG. 15, the second portion 165b of the electrode-dielectric film may be conformally formed on the substrate 100 having the empty regions 106U, 106nU, 106 and the recess regions 162. have. In this case, the thickness of the sacrificial spacer 145a ′ based on the inner wall of the cutting region 140 may be equal to or smaller than twice the thickness of the second portion 165b of the electrode-dielectric film.

Subsequently, a conductive film filling the empty regions 106U, 106nU, and 106 is formed, and the conductive layer is etched to form electrodes GSE1, GSE2, CE, SSE2, and SSE1 in the empty regions 106U, 106nU, and 106. ) Can be formed. The remaining processes may be the same as described with reference to FIGS. 10A to 10B. Thus, the three-dimensional semiconductor memory device disclosed in FIGS. 3A and 3B can be implemented.

(Second Embodiment)

In the present embodiment, the same components as the above-described first embodiment use the same reference numerals. In addition, in order to avoid the duplication of description, it demonstrates centering on the characteristic part of this embodiment.

FIG. 16A is a plan view illustrating a three-dimensional semiconductor memory device according to a second embodiment of the present invention, FIG. 16B is a cross-sectional view taken along line II ′ of FIG. 16A, and FIG. 16C is an enlarged view of a portion D of FIG. 16A. to be.

16A, 16B, and 16C, the first outer wall S1a ′ of the first string select electrode SSE1 may be the first uppermost insulating pattern 105Ua on the first string select electrode SSE1. It may protrude laterally than the outer wall. Similarly, the first outer wall S2a ′ of the second string select electrode SSE2 is greater than the first outer wall of the next higher insulating pattern 105 nUa between the first and second string select electrodes SSE1 and SSE2. It can protrude sideways. The electrode-dielectric film 170 disposed between the vertical active pattern 120 and the inner walls InS1 and InS2 of the first and second string selection electrodes SSE1 and SSE2, respectively, extends to form the first electrode. And first and second outer walls S1a ′ and S2a ′ of the second string select electrodes SSE1 and SSE2.

The first string select electrode SSE1 extends down along the first outer wall of the next higher insulating pattern 105nUa, so that the second string select electrode SSE2 is located below the first string select electrode SSE1. It can be connected with. The connection part 200 of the stacked second and first string selection electrodes SSE2 and SSE1 may be interposed between the first outer wall of the next higher insulating pattern 105nUa and the non-sacrificial pattern 150a '. In addition, the connection part 200 of the first and second string selection electrodes SSE2 and SSE1 may be disposed between the extension parts of the electrode-dielectric film 170.

According to the present exemplary embodiment, the horizontal distance Had between the non-sacrificial pattern 150a ′ and the next higher insulating pattern 105 nUa is a thickness of the electrode-dielectric film 170 on the upper surface of the first string selection electrode SSE1. May be greater than twice T). As a result, a space in which the connection part 200 may be disposed may be secured between the first outer wall of the next higher insulating pattern 105nUa and the non-sacrificial pattern 150a '.

As described above, the second and first string select electrodes SSE2 and SSE1 sequentially stacked may be connected to each other. As shown in FIGS. 16A and 16B, the first and second string select electrodes SSE1 and SSE2 connected to each other on one side of the non-sacrificial pattern 150a are located on the other side of the non-sacrificial pattern 150a. The first and second string select electrodes SSE1 and SSE2 are connected to each other.

In example embodiments, a portion of the first string selection electrode SSE1 adjacent to the first outer wall S1a ′ of the first string selection electrode SSE1 may protrude upward to form the topmost insulating pattern 175. It may be disposed on the first outer wall.

According to the above-described three-dimensional semiconductor memory device, the first outer walls (S1a ′, S2a ′) of the first and second string select electrodes SSE1 and SSE2 are respectively the top and next higher insulating patterns 105Ua and 105nUa. ) May protrude laterally than the first outer walls. As a result, widths of the first and second string select electrodes SSE1 and SSE2 may be increased, thereby reducing resistance of the first and second string select electrodes SSE1 and SSE2. In addition, since the stacked second and first string select electrodes SSE2 and SSE1 are connected to each other, the resistance of the first and second string select electrodes SSE1 and SSE2 may be further reduced. As a result, it is possible to realize a three-dimensional semiconductor memory device having excellent reliability and optimized for high integration.

FIG. 17 is a cross-sectional view taken along the line II ′ of FIG. 16A to describe one modification of the three-dimensional semiconductor memory device according to the second embodiment of the present invention.

Referring to FIG. 17, the electrode-dielectric film 170a between the vertical active pattern 120 and the electrodes GSE1, GSE2, CE, SSE2, and SSE1 may have a first portion 165a and a second portion 165b. It may include. The first portion 165a of the electrode-dielectric film 170a may extend vertically to be interposed between the sidewall of the vertical active pattern 120 and the insulating patterns 105a, 105nUa, and 105Ua. The second portion 165b of the electrode-dielectric film 170a extends to cover lower and upper surfaces of the electrodes GSE1, GSE2, CE, SSE2, and SSE1. In this case, the second portion 165b of the electrode-dielectric film 170a between the vertical active pattern 120 and the string select electrodes SSE1 and SSE2 is further extended to extend the string select electrodes SSE1 and SSE2. May cover the first outer walls. In this modification, the horizontal distance between the first outer wall of the non-sacrificial pattern 150a and the next higher insulating pattern 105nUa is formed of the electrode-dielectric film 170a positioned on the upper surface of the first string selection electrode SSE1. It may be greater than twice the thickness of the two portions 165a.

FIG. 18A is a cross-sectional view taken along the line II ′ of FIG. 16A to explain another modified example of the three-dimensional semiconductor memory device according to the second embodiment of the present invention, and FIG. 18B is an enlarged view of portion E of FIG. 18A. to be.

18A and 18B, according to the present modification, the electrode-dielectric film 170 ′ between the sidewall of the vertical active pattern 120 and each of the electrodes GSE1a, GSE2a, CEa, SSE2a, and SSE1a is vertically formed. It may extend to be interposed between the sidewall of the vertical active pattern 120 and the insulating patterns 105a, 105nUa, 105Ua. In this case, each electrode GSE1a, GSE2a, CEa, SSE2a, and SSE1a may include a metal pattern MP and a barrier conductive pattern BP. The barrier conductive pattern BP is disposed between the metal pattern MP and the insulating patterns 105a, 105nUa and / or 105Ua, and between the metal pattern MP and the electrode-dielectric film 170 ′. Can be.

As illustrated in FIG. 18B, the metal pattern MP in the first string selection electrode SSE1a may have a first outer wall MS1a and a second outer wall MS1b facing each other. The first outer wall MS1a may be adjacent to the non-sacrificial pattern 150a, and the second outer wall MS1b may be adjacent to the device isolation pattern 175a. The barrier conductive pattern BP in the first string select electrode SSE1a may be in contact with the first outer wall MS1a of the metal pattern MP in the first string select electrode SSE1a. In example embodiments, the second outer wall MS1b of the metal pattern MP in the first string select electrode SSE1a may not contact the barrier conductive pattern BP in the first string select electrode SSE1a. have.

Similarly, the metal pattern MP in the second string selection electrode SSE2a may have a first outer wall MS2a and a second outer wall MS2b facing each other. The first and second outer walls MS2a and MS2b of the metal pattern MP in the second string select electrode SSE2a are the first and second of the metal pattern MP in the first string select electrode SSE1a. It may be aligned with the outer walls MS1a and MS1b, respectively. The barrier conductive pattern BP in the second string select electrode SSE2a may be in contact with the first outer wall MS2a of the metal pattern MP in the second string select electrode SSE2a. In example embodiments, the second outer wall MS2b of the metal pattern MP in the second string select electrode SSE2a may not be in contact with the barrier conductive pattern BP in the second string select electrode SSE2a. have. In example embodiments, the second outer walls MS1b and MS2b of the metal patterns MP of the first and second string select electrodes SSE1a and SSE2a may be in contact with the device isolation pattern 175. . In this case, the device isolation pattern 175 may include a dielectric material (eg, nitride and / or oxynitride) having barrier properties.

The first outer wall MS1a of the metal pattern MP in the first string selection electrode SSE1a may protrude laterally than the first outer wall of the uppermost insulating pattern 105Ua. The first outer wall MS2a of the metal pattern MP in the second string select electrode SSE2a may protrude laterally than the first outer wall of the next higher insulating pattern 105nUa. The metal pattern MP in the first string select electrode SSE1a extends down along the first outer wall of the next higher insulating pattern 105nUa, and the metal pattern MP in the second string select electrode SSE2a Can be connected. The connection part MC of the metal patterns MP in the first and second string selection electrodes SSE1a and SSE2a may be interposed between the non-sacrificial pattern 150a 'and the next higher insulating pattern 105nUa. . Barrier conductive patterns BP in the first and second string select electrodes SSE1a and SSE2a also extend to extend between the connection part MC and the next higher insulating pattern 105nUa, and the connection part MC and the non-sacrificial layer. It may be disposed between the patterns 150a '.

As illustrated in FIG. 18A, both outer sidewalls of the metal pattern MP in each cell electrode CEa may not contact the barrier conductive pattern BP in the cell electrode CEa. Similarly, both outer walls of the metal pattern MP in each of the ground selection electrodes GSE1a and GSE2a may not be in contact with the barrier conductive pattern BP in each of the ground selection electrodes GSE1a and GSE2a.

The electrode-dielectric film 170 ′ may include the tunnel dielectric film TDL, the charge storage layer SL, and the blocking dielectric film BDL described with reference to FIG. 1D. The metal pattern MP may include tungsten, copper, aluminum, or the like. The barrier conductive pattern BP may include a conductive metal nitride (eg, titanium nitride, tantalum nitride, tungsten nitride, etc.) and / or a transition metal (ex, titanium, tantalum, etc.).

19A to 24A are plan views illustrating a method of manufacturing a 3D semiconductor memory device according to a second embodiment of the present invention, and FIGS. 19B to 24B are taken along the line II ′ of FIGS. 19A to 24A, respectively. Cross-sectional views.

19A and 19B, the sacrificial layers 110, 110nU, and 110U and the insulating layers 105, 105nU, and 105U may be alternately and repeatedly stacked on the substrate 100. The cutting region 140 may be formed by successively patterning the uppermost insulating film 105U, the uppermost sacrificial film 110U, the next higher insulating film 105nU, and the next higher sacrificial film 110nU.

The spacer layer 245 may be conformally formed on the substrate 100 having the cutting region 140. Reference numeral Tda in FIG. 19B denotes the thickness Tda of the spacer film 245. The spacer layer 245 may be formed of the same material as the spacer layer 145 of the first embodiment described above.

20A and 20B, sacrificial spacers 245a may be formed on both inner sidewalls of the cutting region 140 by etching the spacer layer 145 by a front anisotropic etching process. The sacrificial spacers 245a in the cutting region 140 may be spaced apart from each other. As shown in FIG. 20A, at end portions of the cutting region 140, end portions of the sacrificial spacers 245a may be connected to each other. Subsequently, a non-sacrificial film 150 filling the cutting region 140 may be formed on the substrate 100.

The non-sacrificial layer, the insulating layers 105U, 105nU, and 105 and the sacrificial layers 110U, 110nU, and 110 may be patterned to form sacrificial pads 110P having a stepped structure. In this case, the connecting portion of the end portion of the cutting region 140 and the end portions of the sacrificial spacers 245a may be removed. Accordingly, the sacrificial spacers 245b respectively disposed on both inner walls of the cutting region 140a may be separated from each other. After formation of the sacrificial pads 110P, the non-sacrificial film 150 'may not cover the sacrificial pads 110P disposed below the top sacrificial film 110U.

Holes 115 may be formed through the non-sacrificial layer 150, the insulating layers 105U, 105nU, and 105, the sacrificial layers 110U, 110nU, and 110, and the buffer dielectric layer 103. Vertical active patterns 120 may be formed in the holes 115. In addition, the filling dielectric pattern 125 and the landing pad 130 may be formed in each of the holes 115.

The hole 115 and the vertical active pattern 120 may be formed after the sacrificial pads 110P are formed. However, the present invention is not limited thereto. The hole 115 and the vertical active pattern 120 may be formed before forming the sacrificial pads 110P or before forming the cutting region 140.

The capping dielectric layer 135 ′ may be formed on the entire surface of the substrate 110 including the sacrificial pads 110P.

22A and 22B, the capping dielectric layer 135 ′, the non-sacrificial layer 150 ′, the insulating layers 105U, 105nU, 105, the sacrificial layers 110U, 110nU, 110, and the buffer dielectric layer 103 are described. May be continuously patterned to form trenches 155 defining mold patterns. Each mold pattern includes sacrificial patterns 110a, 110nUa, and 110Ua, insulating patterns 105a, 105nUa, and 105Ua, a cutting region 140, sacrificial spacers 245b, a non-sacrificial pattern 150a ′, and a capping dielectric. Pattern 135a '.

Referring to FIGS. 23A and 23B, the sacrificial patterns 110a, 110nUa, and 110Ua may be removed to form empty regions 160, 160nU, and 160U. In this case, the sacrificial spacers 245b may be etched to form recess regions 262. The sacrificial spacers 245b may be completely removed. Alternatively, portions of the sacrificial spacers 245b located at a level higher than the uppermost empty region 160U may remain.

Referring to FIGS. 24A and 24B, an electrode-dielectric film 170 may be conformally formed on the substrate 100 having the empty regions 160, 160nU, and 160U and the recess regions 262. . In this case, the thickness Tda of the spacer layer 245 may be greater than twice the thickness of the electrode-dielectric layer 170. Accordingly, the electrode-dielectric film 170 may be formed to have a substantially uniform thickness on inner surfaces of the empty regions 160, 160nU and 160U and the recess regions 262. In addition, portions of the recess regions 262 may be empty.

Subsequently, a conductive film may be formed on the substrate 100. The conductive layer may fill the empty regions 160, 160nU and 160U and the recess regions 262. Subsequently, the conductive layers may be etched to form electrodes GSE1, GSE2, CE, SSE2, and SSE1 in the empty regions 160, 160nU, and 160U, respectively. A portion of the conductive layer filling the recess region 262 may correspond to the connection portion 200 of FIG. 16C. In addition, since the thickness of the sacrificial spacer 245b is greater than twice the thickness of the electrode-dielectric film 170, the first outer walls of the first and second string selection electrodes SSE1 and SSE2 may be formed at the uppermost and It may protrude laterally than the first outer walls of the next higher insulating patterns 105Ua and 105nUa.

Before forming the recess region 262, the connection portions of the sacrificial spacers (FIGS. 20A and 20B) are removed, so that the first string select electrode SSE1 on one side of the cutting region 140 is formed in the cutting region ( It may be completely separated from the first string select electrode SSE1 located on the other side of the 140.

After forming the electrodes GSE1, GSE2, CE, SSE2, and SSE1, the electrode-dielectric film 170 positioned on the inner wall of the trench 155 may be removed. The common source region CS may be formed in the substrate 100 under the trench 155. Subsequently, the device isolation pattern 175, the contact plug 180, and the wiring 190 shown in FIGS. 16A to 16C may be formed. As a result, the three-dimensional semiconductor memory device disclosed in FIGS. 16A to 16C can be implemented.

According to the method of manufacturing the 3D semiconductor memory device described above, after the cutting region 140 and the non-sacrificial layer 150 are formed, the trenches 155 are formed, and the empty regions 160, 160nU, 160U). Thus, the effects described in the above-described first embodiment can be obtained. In addition, by making the thickness of the sacrificial spacer 245b larger than twice the thickness of the electrode-dielectric film 170, the widths of the first and second string select electrodes SSE1 and SSE2 may be further increased. In addition, the first and second string select electrodes SSE1 and SSE2 stacked in this order may be connected to each other. Accordingly, the resistance of the first and second string select electrodes SSE1 and SSE2 may be reduced, thereby realizing a three-dimensional semiconductor memory device having excellent reliability and optimized for high integration.

25 is a cross-sectional view for explaining a modification of the method for manufacturing the three-dimensional semiconductor memory device according to the second embodiment of the present invention.

Before forming the vertical active pattern 120 in FIGS. 21A and 21B, the first portion 165a of the electrode-dielectric film may be formed on the inner wall of each hole 115. Thereafter, the methods described with reference to FIGS. 22A and 22B and the methods described with reference to FIGS. 23A and 23B may be performed. Accordingly, the empty regions 160, 160nU, and 160U of FIG. 25 may be formed. In this case, the empty regions 160, 160nU, and 160U may expose the first portion 165a of the electrode-dielectric film positioned on the sidewall of the vertical active pattern 120. Subsequently, the second portion 165b of the electrode-dielectric film may be conformally formed on the substrate having the empty regions 160, 160nU and 160U and the recess regions 262. In this case, the thickness of the sacrificial spacer 245b may be greater than twice the thickness of the second portion 165b of the electrode-dielectric film. Subsequently, a conductive layer filling the empty regions 160, 160nU and 160U and the recess regions 262 is formed, and the conductive layer is etched to fill the empty regions 160, 160nU and 160U, respectively. , GSE2, CE, SSE2, SSE1). Subsequent processes may be the same as those described above. Thus, the three-dimensional semiconductor memory device shown in FIG. 17 can be implemented.

26 is a cross-sectional view for illustrating another modification of the method of manufacturing the three-dimensional semiconductor memory device according to the second embodiment of the present invention.

Before forming the vertical active pattern 120 in FIGS. 21A and 21B, an electrode-dielectric film 170 ′ may be formed on the inner wall of each hole 115. Thereafter, the methods described with reference to FIGS. 22A and 22B and the methods described with reference to FIGS. 23A and 23B may be performed. Accordingly, as shown in FIG. 26, empty regions 160, 160nU, and 160U exposing the electrode-dielectric film 170 ′ positioned on the sidewall of the vertical active pattern 120 may be formed. Subsequently, a conductive layer may be formed to fill the empty regions 160, 160nU and 160U and the recess region 262, and the conductive layer may be etched to form electrodes filling the empty regions 160, 160nU and 160U, respectively. Can be. In this case, after forming the electrodes, the electrode-dielectric film 170 ′ may not be formed in the empty regions 160, 160 nU and 160U and the recess region 262.

In example embodiments, the conductive layer may include a barrier conductive layer and a metal layer. For example, the barrier conductive film is conformally formed on the substrate 100 having the empty regions 160, 160 nU, 160U, and the recess regions 262 exposing the electrode-dielectric film 170 ′. A metal film may be formed on the barrier conductive layer to fill at least the empty regions 160, 160nU, and 160U. The metal layer and the barrier conductive layer may be etched to form electrodes (GSE1a, GSE2a, CEa, SSE2a, and SSE1a of FIGS. 18A and 18B) in the empty regions 160, 160nU, and 160U, respectively. Subsequent processes can be performed in the same manner as described above. As a result, the three-dimensional semiconductor memory device disclosed in FIGS. 18A and 18B can be implemented.

(Third Embodiment)

In the present embodiment, the same components as the above-described embodiments use the same reference numerals. In the following description, the characteristic parts of this embodiment will be described mainly.

FIG. 27A is a plan view illustrating a three-dimensional semiconductor memory device according to a third embodiment of the present invention, FIG. 27B is a cross-sectional view taken along the line II ′ of FIG. 27A, and FIG. 27C is an enlarged view of a portion F of FIG. 27B. to be.

27A, 27B, and 27C, the first outer walls S1a 'and S2a' of the first and second string select electrodes SSE1 and SSE2 adjacent to the non-sacrificial pattern 150a are non-sacrificial. It may protrude laterally than the first outer wall of the uppermost insulating pattern 105Ua adjacent to the pattern 150a. The first outer wall of the next higher insulating pattern 105nUa adjacent to the non-sacrificial pattern 150a may also protrude laterally than the first outer wall of the uppermost insulating pattern 105Ua. The electrode-dielectric film 170 between the vertical active pattern 120 and the first string select electrode SSE1 may extend to cover the first outer wall S1a ′ of the first string select electrode SSE1. The electrode-dielectric film 170 between the vertical active pattern 120 and the second string select electrode SSE2 may extend to cover the first outer wall S2a ′ of the second string select electrode SSE2. . In this case, the electrode-dielectric film 170 covering the first outer wall S1a ′ of the first string select electrode SSE1 is an electrode-dielectric film covering the first outer wall S2a ′ of the second string select electrode SSE2. And may be separated from 170. In addition, the second string select electrode SSE2 and the first string select electrode SSE1 that are sequentially stacked may also be separated from each other.

A portion adjacent to the first outer wall S1a ′ of the first string selection electrode SSE1 may extend upward and be disposed on the first outer wall of the uppermost insulating pattern 105Ua.

A guide opening 300 may be defined between the uppermost insulating patterns 105Ua adjacent to each other. A capping dielectric pattern 135a may be disposed on the uppermost insulating patterns 105Ua. The guide opening 300 may extend upward to penetrate the capping dielectric pattern 135a. The non-sacrificial pattern 150a may extend upward into the guide opening 300. As shown in FIG. 27A, a remaining sacrificial pattern 345R may be disposed at an end portion of the guide opening 300. The residual pattern 345R may be formed of the same material as the residual spacer 145r of the first embodiment described above. Due to the remaining sacrificial pattern 345R, the first string select electrode SSE1 disposed at one side of the guide opening 300 may be aligned with the first string select electrode SSE1 disposed at the other side of the guide opening 300. Can be separated.

According to the above-described three-dimensional semiconductor memory device, the first outer walls S1a 'and S2a' of the first and second string selection electrodes SSE1 and SSE2 are disposed more than the first outer wall of the uppermost insulating pattern 105a. It can protrude sideways. As a result, the resistance of the first and second string selection electrodes SSE1 and SSE2 may be reduced, thereby implementing a three-dimensional semiconductor memory device having excellent reliability.

Next, modifications according to the present embodiment will be described with reference to the drawings.

FIG. 28A is a plan view showing a modification of the three-dimensional semiconductor memory device according to the third embodiment of the present invention, and FIG. 28B is a sectional view taken along the line II ′ of FIG. 28A.

Referring to FIGS. 28A and 28B, in plan view, an end portion of the guide opening 300a may be removed. Accordingly, the remaining sacrificial pattern 345R disclosed in FIG. 27A may be removed. In this case, as illustrated in FIG. 28B, the guide opening 300a may be defined in a limited manner between the topmost insulating patterns 105Ua. The capping dielectric pattern 135a ′ may be disposed on the topmost insulating patterns 105Ua and the non-sacrificial pattern 150a ′.

FIG. 29 is a cross-sectional view taken along the line II ′ of FIG. 27A in order to explain another modification of the three-dimensional semiconductor memory device according to the third embodiment of the present invention.

Referring to FIG. 29, the electrode-dielectric film 170a between the vertical active pattern 120 and each of the electrodes GSE1, GSE2, CE, SSE2, and SSE1 may form a first portion 165a and a second portion 165b. It may include. A second portion 165b of the electrode-dielectric film 170a positioned between the vertical active pattern 120 and the first string select electrode SSE1 extends to form a bottom surface of the first string select electrode SSE1. The upper surface and the first outer wall may be covered. Similarly, the second portion 165b of the electrode-dielectric film 170a positioned between the vertical active pattern 120 and the second string select electrode SSE2 extends to form the second string select electrode SSE2. The lower surface, the upper surface and the first outer wall may be covered.

30A is a cross-sectional view taken along the line II ′ of FIG. 27A in order to explain another modification of the three-dimensional semiconductor memory device according to the third embodiment of the present invention, and FIG. 30B is an enlarged view of a portion G of FIG. 30A. Drawing.

30A and 30B, each of the first and second string select electrodes SSE1b and SSE2b may include a metal pattern MP ′ and a barrier conductive pattern BP ′. The metal pattern MP 'of the first string selection electrode SSE1b may have a first outer wall MS1a' and a second outer wall MS1b 'facing each other. The metal pattern MP 'of the second string selection electrode SSE2b may also have a first outer wall MS2a' and a second outer wall MS2b 'facing each other. The first and second outer walls MS2a 'and MS2b' of the metal pattern MP 'in the second string select electrode SSE2b are formed of the metal pattern MP' in the first string select electrode SSE2b. It may be aligned with the first and second outer walls MS1a 'and MS1b', respectively.

The barrier conductive pattern BP ′ in the first string select electrode SSE1b contacts the upper surface, the lower surface, and the first outer wall MS1a ′ of the metal pattern MP ′ in the first string select electrode SSE1b. Can be. The second outer wall MS1b 'of the metal pattern MP' in the first string select electrode SSE1b may not be in contact with the barrier conductive pattern BP ′ in the first string select electrode SSE1b. Similarly, the barrier conductive pattern BP ′ in the second string select electrode SSE2b may have an upper surface, a lower surface, and a first outer wall MS2a 'of the metal pattern MP' in the second string select electrode SSE2b. ) May be contacted. The second outer wall MS2b 'of the metal pattern MP' in the second string select electrode SSE2b may not contact the barrier conductive pattern BP 'in the second string select electrode SSE2b.

The metal pattern MP ′ in the first string select electrode SSE1b may be separated from the metal pattern MP ′ in the second string select electrode SSE2b. In addition, the barrier conductive pattern BP ′ in the first string select electrode SSE1b may also be separated from the barrier conductive pattern BP ′ in the second string select electrode SSE2b.

Each of the metal pattern MP ′ and the barrier conductive pattern BP ′ of the first and second string selection electrodes SSE1b and SSE2b is a metal pattern MP and a barrier conductive pattern BP of the cell electrode CEa. And each of the same material).

31A to 35B are plan views illustrating a method of manufacturing a 3D semiconductor memory device according to a third exemplary embodiment of the present invention, and FIGS. 31B to 35B are taken along the line II ′ of FIGS. 31A to 35A, respectively. Cross-sectional views.

31A and 31B, the insulating layers 105U, 105nU and 105 and the sacrificial layers 110U, 110nU and 110 may be patterned to form sacrificial pads 110P having a stepped structure. The capping dielectric layer 135 may be formed on the substrate 100 having the sacrificial pads 110P.

The capping dielectric layer 135 and the uppermost insulating layer 105U may be patterned to form a guide opening 300. The guide opening 300 may expose the top sacrificial layer 110U. As illustrated in FIG. 31A, the guide opening 300 may have a groove shape extending in the y-axis direction.

The holes 115 and the vertical active pattern 120 may be formed after the sacrificial pads 110P are formed. The holes 115 and the vertical active pattern 120 may be formed before the guide opening 300 is formed.

The spacer film 345 may be conformally formed on the substrate 100 having the guide opening 300. The spacer layer 345 may be formed of the same material as the spacer layer 145 of the first embodiment.

32A and 32B, in the anisotropic etching process, the spacer layer 345 and the top sacrificial layer 110U may be continuously etched to form the cutting region 340. In this case, sacrificial spacers 345a may be formed on both inner walls of the guide opening 300. The cutting region 340 may be formed between the sacrificial spacers 345a in the guide opening 300. During the etching of the uppermost sacrificial layer 110U, portions of the spacer layer 345 on both inner walls of the guide opening 300 may be etched. As a result, upper ends of the sacrificial spacers 345a may be located at a lower level than upper ends of the inner walls of the guide opening 300. The cutting region 340 cuts the uppermost sacrificial layer 110U.

As illustrated in FIG. 32A, end portions of the sacrificial spacers 345a may be connected to each other at the end portion of the guide opening 300. When the sacrificial spacers 345a are formed after the sacrificial pads 110P are formed, the connection portions of the sacrificial spacers 345a are replaced with electrode pads of cell electrodes and ground select electrodes. It is preferable to be disposed on the capping dielectric layer 135 on any one of the pads 110P.

33A and 33B, the sacrificial spacers 345a may be used as an etching mask to sequentially etch the next higher insulating layer 105 nU and the next upper sacrificial layer 110 nU under the cutting region 340. . As a result, a cutting region 340a may be formed to cut the top and next top sacrificial layers 110U and 110nU. In example embodiments, a portion of the sacrificial spacers 345a may be etched when the next higher sacrificial layer 110nU is etched. As such, the etched sacrificial spacers 345a ′ may be lower than the sacrificial spacers 345a of FIG. 32B.

34A and 34B, a non-sacrificial film may be formed on the entire surface of the substrate 100 to fill the cutting area 345a and the guide opening 300. The trenches 155 are formed by successively patterning the non-sacrificial layer, the capping dielectric layer 135, the insulating layers 105U, 105nU, and 105a, the sacrificial layers 110U, 110nU, and 110, and the buffer dielectric layer 103. . By the formation of the trenches 155, mold patterns are formed. Each mold pattern may form insulating patterns 105a, 105nUa and 105Ua, sacrificial patterns 110a, 110nUa and 110Ua, a capping dielectric pattern 135a, and a non-sacrificial pattern 150a.

The non-sacrificial pattern 150a may be in contact with the top and next top sacrificial patterns 110nUa and 110Ua forming both inner walls of the cutting area 345a.

35A and 35B, the sacrificial patterns 110a, 110nUa and 110Ua may be removed to form empty regions 160, 160nU and 160U. When the sacrificial patterns 110a, 110nUa and 110Ua are removed, the etched sacrificial spacers 345a ′ in contact with the top sacrificial pattern 110Ua may be removed. In this case, as shown in FIG. 35A, the connection portion 345R of the sacrificial spacers 345a 'positioned at the end of the guide opening 300 may remain. The connection part 345R is defined as a residual sacrificial pattern 345R. The remaining sacrificial pattern 345R may include a region where the sacrificial spacer 345a 'removed on one inner sidewall of the guide opening 300 is removed from the sacrificial spacer 345a' positioned on the other sidewall of the guide opening 300. Can be separated from the removed area.

Subsequently, an electrode-dielectric film 170 is conformally formed on the substrate 100 having the empty regions 160, 160 nU and 160U, and the empty regions 160 and 160 nU on the electrode dielectric layer 170. , 160U) can be formed. The conductive layer may be etched to form the electrodes GSE1, GSE2, CE, SSE2, and SSE1 of FIGS. 27A to 27C. Subsequent processes can be performed in the same manner as described above. As a result, the three-dimensional semiconductor memory device shown in FIGS. 27A to 27C can be implemented.

According to the above-described method for manufacturing a three-dimensional semiconductor memory device, the cutting region 345a and the non-sacrificial film 150 are formed before the trench 155 is formed so that the string selection electrodes SSE1 and SSE2 may be formed. The first outer walls S1a 'and S2a' may be protected from an etching process. As a result, the etching losses of the string select electrodes SSE1 and SSE2 may be minimized to reduce the resistance of the string select electrodes SSE1 and SSE2.

In addition, the cutting region 340a is formed using the sacrificial spacers 345a in the guide opening 300 as an etch mask, thereby reducing the width of the uppermost empty regions 160U and the next higher empty regions 160nU. Can be increased. As a result, widths of the string select electrodes SSE1 and SSE2 may be increased, thereby reducing resistance of the string select electrodes SSE1 and SSE2. As a result, a three-dimensional semiconductor memory device having excellent reliability and optimized for high integration can be realized.

According to the manufacturing method described above, after the sacrificial pads 110P are formed, the guide opening 300 may be formed. Alternatively, the sacrificial pads 110P may be formed after the guide opening 300 is formed. This will be described with reference to the drawings.

36 and 37 are plan views illustrating a modification of the method of manufacturing the 3D semiconductor memory device according to the third embodiment of the present invention.

Referring to FIG. 36, before forming the sacrificial pads 110P, the uppermost insulating layer 105U may be patterned to form the guide opening 300. Subsequently, the methods described with reference to FIGS. 31A to 33A and 31B to 33B may be performed. As a result, sacrificial spacers 345a 'are formed on both inner walls of the guide opening 300, and a cutting region 340a is formed between the sacrificial spacers 345a in the guide opening 300. Can be.

Referring to FIG. 37, a non-sacrificial layer filling the cutting region 340a may be formed, and the non-sacrificial layer, insulating layers, and sacrificial layers may be patterned to form stepped sacrificial pads 110P. In this case, an end portion of the guide opening 300 and a connection portion of the sacrificial spacers 345a 'may be removed together. As a result, the sacrificial spacers 345b formed on both inner walls of the guide opening 300a may be separated from each other. Subsequent processes may be performed in the same manner as described with reference to FIGS. 34A and 34B and FIGS. 35A and 35B. As a result, the three-dimensional semiconductor memory device shown in FIGS. 28A and 28B can be implemented.

38 is a cross-sectional view for illustrating another modification of the method of manufacturing the three-dimensional semiconductor memory device according to the third embodiment of the present invention.

Before forming the vertical active pattern 120 described with reference to FIGS. 31A and 31B, the first portion 165a of the electrode dielectric layer may be formed on the inner wall of the hole 115. As a result, empty regions 160, 160nU, and 106U exposing the first portion 165a of the electrode dielectric layer illustrated in FIG. 38 may be formed. Subsequently, the second portion 165b of the electrode dielectric layer is conformally formed on the substrate 100 having the empty regions 160, 160 nU and 160U, and the electrode filling the empty regions 160, 160 nU and 160U. And GSE1, GSE2, CE, SSE2, and SSE1. Thus, the three-dimensional semiconductor memory device shown in FIG. 29 can be implemented.

Meanwhile, before forming the vertical active pattern 120, the entire electrode-dielectric film 170 ′ may be formed on the inner wall of the hole 115. In this case, the empty regions 160, 160nU, and 160U may expose the electrode-dielectric film 170 ′ positioned on the sidewall of the vertical active pattern 120. A conductive layer may be formed to fill the empty regions 160, 160nU, and 160U exposing the electrode-dielectric film 170 ′, and electrodes may be formed by etching the conductive layer to fill the empty regions 160, 160nU, and 160U, respectively. can do. In example embodiments, the conductive layer may include a barrier conductive layer and a metal layer. In this case, the three-dimensional semiconductor memory element shown in Figs. 30A and 30B can be implemented.

The 3D semiconductor memory devices disclosed in the above-described embodiments may be implemented in various types of semiconductor package. For example, three-dimensional semiconductor memory devices according to embodiments of the present invention may be packaged on packages (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC), plastic dual in Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) The package may be packaged in a Wafer-Level Processed Stack Package (WSP).

The package in which the 3D semiconductor memory device is mounted in the embodiments of the present invention may further include a controller and / or a logic device for controlling the 3D semiconductor memory device.

39 is a block diagram schematically illustrating an example of an electronic system including a 3D semiconductor memory device based on the technical spirit of the present invention.

Referring to FIG. 39, an electronic system 1100 according to an embodiment of the present invention may include a controller 1110, an input / output device 1120, an I / O, a memory device 1130, an interface 1140, and a bus. (1150, bus). The controller 1110, the input / output device 1120, the memory device 1130, and / or the interface 1140 may be coupled to each other through the bus 1150. The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing functions similar thereto. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The memory device 1130 may include at least one of the three-dimensional semiconductor memory devices disclosed in the above-described embodiments. The memory device 1130 may further include other types of semiconductor memory devices (eg, DRAM devices, SRAM devices, magnetic memory devices, and / or phase change memory devices). The interface 1140 may perform a function of transmitting data to or receiving data from a communication network. The interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1100 may further include a high-speed DRAM device and / or an SLAM device as an operation memory device for improving the operation of the controller 1110. [

The electronic system 1100 may be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a digital music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

40 is a block diagram schematically illustrating an example of a memory card including a 3D semiconductor memory device based on the inventive concept.

Referring to FIG. 40, a memory card 1200 according to an embodiment of the present invention includes a memory device 1210. The memory device 1210 may include at least one of three-dimensional semiconductor memory devices in the above-described embodiments. In addition, the memory device 1210 may further include other types of semiconductor memory devices (eg, DRAM devices, SRAM devices, magnetic memory devices, and / or phase change memory devices). The memory card 1200 may include a memory controller 1220 that controls the exchange of data between the host and the storage device 1210.

The memory controller 1220 may include a processing unit 1222 for controlling the overall operation of the memory card. In addition, the memory controller 1220 may include an SRAM 1221, which is used as an operation memory of the processing unit 1222. In addition, the memory controller 1220 may further include a host interface 1223 and a memory interface 1225. The host interface 1223 may include a data exchange protocol between the memory card 1200 and a host. The memory interface 1225 can connect the memory controller 1220 and the storage device 1210. Further, the memory controller 1220 may further include an error correction block 1224 (Ecc). The error correction block 1224 can detect and correct errors in data read from the storage device 1210. [ Although not shown, the memory card 1200 may further include a ROM device for storing code data for interfacing with a host. The memory card 1200 may be used as a portable data storage card. Alternatively, the memory card 1200 may be implemented as a solid state disk (SSD) capable of replacing a hard disk of a computer system.

As mentioned above, although embodiments of the present invention have been described with reference to the accompanying drawings, the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (38)

An electrode structure comprising electrodes and insulating patterns alternately and repeatedly stacked on a substrate, wherein one of the electrodes has a first outer wall and a second outer wall facing each other;
A vertical active pattern penetrating the electrode structure; And
An electrode-dielectric film interposed between the sidewalls of the vertical active pattern and each of the electrodes, wherein at least a portion of the electrode-dielectric film positioned between the one electrode and the sidewall of the vertical active pattern extends to form the top electrode; A three-dimensional semiconductor memory element covering the lower surface, the upper surface and the first outer wall. The method according to claim 1,
An extension of the at least a portion of the electrode-dielectric film does not cover the second outer wall of the one electrode. The method according to claim 1,
Further comprising a pair of device isolation patterns disposed on the substrate on both sides of the electrode structure,
And the second outer wall of the one electrode is in contact with any one of the pair of device isolation patterns. The method according to claim 3,
And the electrode structure includes another electrode having both outer walls contacting the pair of device isolation patterns, respectively. The method according to claim 1,
And the one electrode is a top electrode in the electrode structure. The method according to claim 5,
Among the electrodes, the next higher electrode located directly below the uppermost electrode has a first outer wall and a second outer wall facing each other,
The first outer wall and the second outer wall of the next higher electrode are aligned with the first outer wall and the second outer wall of the uppermost electrode, respectively.
And at least a portion of an electrode-dielectric film positioned between the sidewall of the next upper electrode and the vertical active pattern to extend to cover the bottom surface, the top surface, and the first outer wall of the next upper electrode. The method of claim 6,
An extension of the electrode-dielectric film covering the first outer wall of the uppermost electrode extends downward along one outer wall of the insulating pattern between the uppermost and second upper electrodes, and is connected to an extension of the electrode-dielectric film covering the first outer wall of the upper electrode. 3D semiconductor memory device. The method of claim 7,
And the top electrode and the next upper electrode are separated from each other. The method of claim 7, wherein
Further comprising a non-sacrificial pattern disposed next to the one outer wall of the insulating pattern between the uppermost and second upper electrodes and the first outer walls of the uppermost and second upper electrodes,
A three-dimensional semiconductor memory in which a horizontal distance between the one outer wall of the insulating pattern and the non-sacrificial pattern between the uppermost and second upper electrodes is equal to or less than twice the thickness of an extension of the electrode-dielectric film positioned on an upper surface of the uppermost electrode; device. The method of claim 6,
And the top electrode extends downward along one outer wall of the insulating pattern between the top and next top electrodes and is connected to the next top electrode. The method of claim 10,
Further comprising a non-sacrificial pattern disposed next to the one outer wall of the insulating pattern between the uppermost and second upper electrodes and the first outer walls of the uppermost and second upper electrodes,
And a horizontal distance between the one outer wall of the insulating pattern and the non-sacrificial pattern between the uppermost and second upper electrodes is greater than twice the thickness of an extension of the electrode-dielectric film located on an upper surface of the uppermost electrode. The method of claim 6,
An extension of the electrode-dielectric film covering the first outer walls of the top electrode is spaced apart from an extension of the electrode-dielectric film covering the first outer wall of the next higher electrode,
And the top electrode and the next top electrode are also separated from each other. The method of claim 12,
Further comprising a non-sacrificial pattern disposed next to one outer wall of the insulating pattern between the uppermost and second upper electrodes, and the first outer walls of the uppermost and second upper electrodes,
And the non-sacrificial pattern is in contact with the one outer wall of the insulating pattern between the uppermost and next upper electrodes. The method according to claim 5,
The electrode structure comprises one lowermost electrode,
The top electrode is provided in plurality over the bottom electrode, wherein the plurality of top electrodes are spaced apart laterally and located at the same level from the top surface of the substrate,
And a plurality of the vertical active patterns, wherein each of the vertical active patterns penetrates the top electrode and the electrodes stacked below the top electrode. The method according to claim 5,
Further comprising a remaining sacrificial spacer disposed on one outer wall of the topmost insulating pattern on the top electrode,
The remaining sacrificial spacer includes a dielectric material having an etch selectivity with respect to the insulating patterns and the non-sacrificial pattern. The method according to claim 1,
And the first outer wall of the uppermost electrode protrudes laterally than one outer wall of the uppermost insulating pattern disposed on the uppermost electrode. The method according to claim 1,
The electrode-dielectric film includes a tunnel dielectric film, a charge storage layer, and a blocking dielectric film,
An extension portion of the electrode-dielectric film covering the first outer wall of the one electrode includes at least a portion of the blocking dielectric film. An electrode structure comprising electrodes and insulating patterns alternately and repeatedly stacked on a substrate, each electrode comprising a metal pattern and a barrier conductive pattern;
A vertical active pattern penetrating the electrode structure; And
An electrode-dielectric film interposed between the sidewalls of the vertical active pattern and the electrodes,
Among the electrodes, the metal pattern in one electrode has a first outer wall and a second outer wall facing each other,
And the barrier conductive pattern in the one electrode is in contact with the first outer wall of the metal pattern in the one electrode. 19. The method of claim 18,
And the electrode-dielectric film extends vertically and is interposed between the sidewall of the vertical active pattern and the insulating pattern. 19. The method of claim 18,
And a second outer wall of the metal pattern in the one electrode is not in contact with the barrier conductive pattern in the one electrode. 19. The method of claim 18,
And the one electrode is a top electrode in the electrode structure. 23. The method of claim 21,
The metal pattern in the next higher electrode located directly below the top electrode has a first outer wall and a second outer wall facing each other,
And the barrier conductive pattern in the next upper electrode is in contact with a first outer wall of the metal pattern in the next upper electrode. 23. The method of claim 22,
The metal pattern in the top electrode extends along one outer wall of the insulating pattern between the top and second top electrodes and is connected to the metal pattern in the next top electrode. Alternately and repeatedly stacking sacrificial films and insulating films on the substrate;
Forming a cutting region penetrating a top sacrificial layer among the sacrificial layers;
Forming a non-sacrificial film in the cutting region;
Forming vertical active patterns penetrating the insulating layers and the sacrificial layers;
Successively patterning the insulating layers and the sacrificial layers to form a mold pattern including insulating patterns, sacrificial patterns, and a non-sacrificial layer in the cutting region;
Removing the sacrificial patterns to form empty regions;
Forming electrodes in the empty areas, respectively; And
And forming an electrode-dielectric film between the sidewalls of the vertical active pattern and the respective electrodes. 27. The method of claim 24,
Before forming the non-sacrificial layer, further comprising forming a pair of sacrificial spacers on both inner walls of the cutting region, respectively,
Forming the empty regions comprises removing the sacrificial patterns and at least portions of the sacrificial spacers to form the empty regions and recess regions. 26. The method of claim 25,
The sacrificial spacers may include a dielectric material having a etch rate that is equal to or greater than 10% of the etch rate of the sacrificial patterns and is 200% or less of the etch rate of the sacrificial patterns. 26. The method of claim 25,
The cutting region is formed by successively patterning a top insulating film of the insulating films, the top sacrificial film, a second top insulating film of the insulating films, and a next top sacrificial film of the sacrificial films,
And each recess area is connected to a topmost bin area and a next top bin area formed on each side of the cutting area. The method of claim 27,
Forming the electrode-dielectric film includes conformally forming at least a portion of the electrode-dielectric film on a substrate having the empty and recessed regions prior to forming the electrodes,
And a portion of the recess region located next to the insulating pattern between the topmost and next topmost regions that are sequentially stacked is filled by the at least a portion of the electrode-dielectric film. 29. The method of claim 28,
And a thickness of the sacrificial spacer relative to the inner wall of the cutting region is equal to or less than twice the thickness of the at least a portion of the electrode-dielectric film formed on the inner surface of the empty region. 29. The method of claim 28,
And a top electrode in the topmost blank area separated from a next top electrode in the next top blank area. The method of claim 27,
And a top electrode in the topmost blank area extending into the recessed area and connected to a next top electrode in the next topmost blank area. 32. The method of claim 31,
Forming the electrode-dielectric film includes conformally forming at least a portion of the electrode-dielectric film on a substrate having the empty and recessed regions prior to forming the electrodes,
And the thickness of the sacrificial spacer relative to the inner wall of the cutting region is greater than twice the thickness of the at least a portion of the electrode-dielectric film formed on the inner surface of the empty region. 32. The method of claim 31,
Patterning the alternately stacked sacrificial layers and insulating layers to form sacrificial pads having a stepped structure;
The sacrificial pads are formed after forming the sacrificial spacers,
When the sacrificial pads are formed, a connection portion of the sacrificial spacers at the end of the cutting region is removed so that the sacrificial spacers are separated from each other. 32. The method of claim 31,
The electrode-dielectric film is formed on the inner wall of the hole which continuously passes through the insulating films and the sacrificial films before forming the vertical active pattern,
And the vertical active pattern is formed in the hole. 27. The method of claim 24,
Forming the cutting area,
Patterning an uppermost insulating film among the insulating films to form a guide opening;
Conformally forming a spacer film on the substrate having the guide opening; And
And anisotropically etching the spacer layer and the uppermost sacrificial layer to form sacrificial spacers on both inner walls of the cutting region and the guide opening. 36. The method of claim 35,
Forming the cutting area,
Using the sacrificial spacers as an etch mask, continuously etching a next higher insulating film among the insulating films and a next higher sacrificial film among the sacrificial films. 36. The method of claim 35,
The sacrificial spacers may include a dielectric material having a etch rate that is equal to or greater than 10% of the etch rate of the sacrificial patterns and is 200% or less of the etch rate of the sacrificial patterns. 27. The method of claim 24,
The non-sacrifice film includes a dielectric material having an etching rate less than 10% of the etching rate of the sacrificial patterns.

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