KR20120098304A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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Publication number
KR20120098304A
KR20120098304A KR1020110018170A KR20110018170A KR20120098304A KR 20120098304 A KR20120098304 A KR 20120098304A KR 1020110018170 A KR1020110018170 A KR 1020110018170A KR 20110018170 A KR20110018170 A KR 20110018170A KR 20120098304 A KR20120098304 A KR 20120098304A
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KR
South Korea
Prior art keywords
reference voltage
voltage
semiconductor integrated
integrated circuit
unit
Prior art date
Application number
KR1020110018170A
Other languages
Korean (ko)
Inventor
강태진
Original Assignee
에스케이하이닉스 주식회사
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Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110018170A priority Critical patent/KR20120098304A/en
Publication of KR20120098304A publication Critical patent/KR20120098304A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018557—Coupling arrangements; Impedance matching circuits

Abstract

PURPOSE: A semiconductor integrated circuit is provided to accurately control an ODT(On Die Termination) resistance by sensing a reference voltage inputted to an impedance control circuit and including a test mode to control the level of the reference voltage. CONSTITUTION: A reference voltage control unit(1) outputs an input reference voltage by an initial signal and controls the level of the input reference voltage by a first test signal and a second test signal. An impedance control circuit(3) controls an ODT resistance by receiving the input reference voltage. A voltage distribution unit outputs first to third voltages by distributing a power voltage. A selection output unit selectively one of the first to third voltages as a reference voltage in response to an initial signal, the first test signal, and the second test signal. [Reference numerals] (1) Reference voltage control unit; (32) First counter; (33) First pull-up unit; (34) Second pull-up unit; (36) Second counter; (37) Pull-down unit

Description

Semiconductor Integrated Circuits {SEMICONDUCTOR INTEGRATED CIRCUIT}

The present invention relates to a semiconductor integrated circuit including an impedance control circuit.

Synchronous memory devices capable of operating in synchronization with a clock have been introduced to improve operation speed in semiconductor integrated circuits. The first synchronous memory device was a so-called single data rate (SDR) synchronous memory device that inputs and outputs one data over one cycle of a clock at one data pin in synchronization with a rising edge of the clock. However, since the SDR synchronous memory device is also insufficient to satisfy the speed of a system requiring high speed operation, a double data rate (DDR) synchronous memory device, which processes two data in a clock cycle, has been proposed.

Each data entry / exit pin of the digital synchronous memory device inputs and outputs two data in synchronization with a rising edge and a falling edge of an externally input clock. At least twice as much bandwidth as the SDR synchronous memory device can realize high speed operation.

As the semiconductor integrated circuit operates at a high speed, the swing width of a signal interfaced between the semiconductor integrated circuits or between the semiconductor integrated circuit and the memory controller is gradually decreasing. As the swing width of the interface signal decreases, the influence on external noise increases, and the reflection of the signal due to impedance mismatching in the interface stage becomes more severe. When impedance mismatching occurs, high-speed transmission of signals becomes difficult and data output from an output terminal of the semiconductor memory device may be distorted.

Therefore, an impedance matching circuit called On Die Termination (ODT) is provided inside the semiconductor integrated circuit which operates at a high speed. In general, in the ODT, source termination is performed by an output circuit at a transmitting end, and parallel termination is performed at a receiving end by a termination circuit connected in parallel with respect to a receiving circuit connected to an input pad.

The resistance value of ODT changes according to PVT (Process, Voltage, Temperature) conditions. Therefore, the semiconductor integrated circuit is provided with an impedance control circuit for performing a ZQ calibration operation using an external resistor to adjust the resistance value of the changed ODT.

The impedance control circuit receives the reference voltage and generates code signals for adjusting the resistance value of the ODT. When the level of the reference voltage changes, the accuracy of the impedance control circuit is reduced, so the reference voltage must be maintained at a constant level.

However, the reference voltage input to the impedance control circuit may change due to PVT conditions. That is, in general, the reference voltage is set to the half level of the power supply voltage VDD and is input to the impedance control circuit. As the PVT condition changes, the reference voltage may be changed to be larger or smaller than the half level of the power supply voltage VDD. As such, the impedance control circuit that receives the reference voltage having the changed level cannot accurately adjust the resistance value of the ODT.

The present invention discloses a semiconductor integrated circuit which senses a reference voltage input to an impedance control circuit through a pad and has a test mode for adjusting the level of the reference voltage so that the ODT resistance can be accurately adjusted.

To this end, the present invention outputs an input reference voltage by an initial signal, a reference voltage control unit for adjusting the level of the input reference voltage by the first and second test signals, a pad for outputting the input reference voltage, and It provides a semiconductor integrated circuit including an impedance control circuit for receiving the input reference voltage to adjust the resistance value of the ODT.

1 is a diagram illustrating a configuration of a semiconductor integrated circuit according to an exemplary embodiment of the present invention.
FIG. 2 is a circuit diagram of a reference voltage controller included in the semiconductor integrated circuit shown in FIG. 1.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

1 is a diagram illustrating a configuration of a semiconductor integrated circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the semiconductor integrated circuit of the present exemplary embodiment outputs an input reference voltage VREFIN by an initial signal INT, but is input by a first test signal TM1 and a second test signal TM2. Resistor of ODT (not shown) receiving the reference voltage control unit 1 for adjusting the level of the reference voltage VREFIN, the pad 2 for outputting the input reference voltage VREFIN, and the input reference voltage VREFIN. Impedance control circuit 3 for adjusting the value and ZQ pad 4 is connected to the external resistor (R).

The impedance adjusting circuit 3 includes a first comparator 31, a first counter 32, a first pull-up unit 33, a second pull-up unit 34, a second comparator 35, and a second counter 36. And a pull-down section 37. The first comparator 31 compares the voltage ZQ of the ZQ pad 4 with the input reference voltage VREFIN to drive the first counter 32 to count the pull-up codes PCODE <1: N>. The resistance values of the first pull-up part 33 and the second pull-up part 34 are adjusted to be the same as the resistance values of the external resistor R. The second comparator 35 compares the voltage of the node nd30 with the input reference voltage VREFIN to drive the second counter 36 to count the pulldown codes NCODE <1: N>, thereby pulling down the pulldown unit 37. ) Is adjusted to be equal to the resistance of the second pull-up unit 34. The pull-up code PCODE <1: N> and the pull-down code NCODE <1: N> are input to an ODT (not shown) and used to adjust the resistance value.

FIG. 2 is a circuit diagram of a reference voltage controller included in the semiconductor integrated circuit shown in FIG. 1.

As shown in FIG. 2, the reference voltage controller 1 includes a voltage divider 11, a selection output unit 12, and an amplifier 13.

The voltage divider 11 is composed of resistor elements R11 to R14, and outputs the first voltage V1 at the node nd11, and outputs the second voltage V2 at the node nd12. The third voltage V3 is output at (nd13). In the present embodiment, it is preferable that the second voltage V2 is set to half the level of the power supply voltage VDD, the first voltage V1 is higher than the second voltage V2, and the third voltage V3. Is a level lower than the second voltage V2.

When the first test signal TM1 is enabled at the logic high level, the selection output unit 12 selects the transfer gate T11 that selects the first voltage V1 and outputs it to the reference voltage VREF, and the initial signal. When INT is enabled at the logic high level, the transfer gate T12 that selects and outputs the second voltage V2 to the reference voltage VREF and the second test signal TM2 are enabled at the logic high level. In this case, the transfer gate T13 selects the third voltage V3 and outputs the voltage to the reference voltage VREF. The initial signal INT is a signal that is enabled at a logic high level while the input reference voltage VREFIN is set to half the level of the power supply voltage VDD. When the input reference voltage VREFIN sensed by the pad 2 is not half the level of the power supply voltage VDD, one of the first test signal TM1 or the second test signal TM2 is brought to the logic high level. It is enabled and the initial signal INT is disabled to a logic low level.

 The amplifier 13 amplifies the reference voltage VREF and outputs it as the input reference voltage VREFIN.

The integrated circuit of the present embodiment described above detects the input reference voltage VREFIN through the pad 2, and when the input reference voltage VREFIN is not half the level of the power supply voltage VDD, the reference voltage controller 1 is applied. Adjust the level of the input reference voltage (VREFIN). For example, when the input reference voltage VREFIN is lower than the half level of the power supply voltage VDD, the first test signal TM1 is applied at a logic high level to increase the level of the input reference voltage VREFIN. When the input reference voltage VREFIN is higher than the half level of the power supply voltage VDD, the second test signal TM2 is applied at a logic high level to reduce the level of the input reference voltage VREFIN.

1: Reference voltage controller 11: Voltage divider
12: Selective output section 13: Amplifier section
2: pad 3: impedance control circuit
31: first comparator 32: first counter
33: first pull-up part 34: second pull-up part
35: second comparator 36: second counter
37: pull-down section 4: ZQ pad

Claims (6)

A reference voltage adjusting unit for outputting an input reference voltage by an initial signal, and adjusting a level of the input reference voltage by first and second test signals;
A pad for outputting the input reference voltage; And
And an impedance control circuit for receiving the input reference voltage and adjusting a resistance value of the ODT.
The semiconductor integrated circuit of claim 1, wherein the initialization signal is disabled in a test mode in which the first and second test signals are selectively applied.
The method of claim 1, wherein the reference voltage control unit
A voltage divider configured to divide the power supply voltage and output first to third voltages; And
And a selection output unit configured to selectively output one of the first to third voltages as a reference voltage in response to the initial signal and the first and second test signals.
The semiconductor integrated circuit of claim 3, wherein the first voltage is higher than the second voltage, and the third voltage is lower than the second voltage.
4. The display device of claim 3, wherein the selection output unit outputs the first voltage when the first test signal is enabled, and outputs the third voltage when the second test signal is enabled. And outputting the second voltage when all of the second test signals are disabled.
The semiconductor integrated circuit of claim 3, further comprising an amplifier configured to amplify the reference voltage and output the amplified reference voltage.

KR1020110018170A 2011-02-28 2011-02-28 Semiconductor integrated circuit KR20120098304A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110018170A KR20120098304A (en) 2011-02-28 2011-02-28 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110018170A KR20120098304A (en) 2011-02-28 2011-02-28 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
KR20120098304A true KR20120098304A (en) 2012-09-05

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KR1020110018170A KR20120098304A (en) 2011-02-28 2011-02-28 Semiconductor integrated circuit

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