KR20120097982A - Refresh control circuit - Google Patents

Refresh control circuit Download PDF

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Publication number
KR20120097982A
KR20120097982A KR1020110017616A KR20110017616A KR20120097982A KR 20120097982 A KR20120097982 A KR 20120097982A KR 1020110017616 A KR1020110017616 A KR 1020110017616A KR 20110017616 A KR20110017616 A KR 20110017616A KR 20120097982 A KR20120097982 A KR 20120097982A
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KR
South Korea
Prior art keywords
control circuit
refresh control
signal
refresh
low voltage
Prior art date
Application number
KR1020110017616A
Other languages
Korean (ko)
Inventor
강용구
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110017616A priority Critical patent/KR20120097982A/en
Publication of KR20120097982A publication Critical patent/KR20120097982A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4067—Refresh in standby or low power modes

Abstract

The refresh control circuit is disclosed. The refresh control circuit generates an oscillation signal using a plurality of delay elements, but in a low voltage mode, the oscillator generates the oscillation signal by blocking a path to some delay elements of the plurality of delay elements and uses the oscillation signal. And a periodic signal generator for generating a refresh periodic signal that is activated every predetermined period.

Description

Refresh control circuit {REFRESH CONTROL CIRCUIT}

The present invention relates to a refresh control circuit of a semiconductor memory device.

In the case of dynamic random access memory (DRAM) among semiconductor memory devices, unlike the random random access memory (SRAM) or the nonvolatile memory (NONvolatile memory), information stored in a memory cell may be lost over time. This is because a memory cell of a DRAM is composed of one transistor and one capacitor, so that natural leakage of data stored in the capacitor occurs. Therefore, in order to prevent such data loss, the memory cells need to be recharged at regular intervals, which is called refresh.

The refresh is performed by amplifying data by activating a word line in an active state at least once within a retention time of each memory cell. The retention time herein refers to a time when data can be maintained without refreshing after writing some data in the memory cell.

The refresh operation includes auto refresh mode and self refresh mode. The auto refresh operation is performed by a command applied from a system including DRAM, and the self refresh operation is performed for a predetermined time. If not, it means the way DRAM performs itself.

1 is a configuration diagram of a conventional refresh control circuit.

As shown in FIG. 1, the conventional refresh control circuit includes an oscillator 100 and a periodic signal generator 110. The oscillator 100 includes a NAND gate 101 and a plurality of inverters 102, 103, and 104. , 105 may be implemented in the form of a ring oscillator connected thereto. Each of the inverters 102, 103, 104, and 105 operates by receiving a power supply voltage VDD.

When the self refresh command SREF is activated as 'high', the oscillator 100 generates an oscillation signal OSC that toggles at a predetermined cycle, and the periodic signal generator 110 generates an oscillation signal ( The refresh cycle signal PSRF is generated by dividing the OSC at a predetermined ratio. The refresh cycle signal PSRF is a signal that determines the refresh operation cycle of the DRAM and is generally activated every 7.8 ms.

Recently, many systems use dynamic voltage and frequency scaling (DVFS) techniques for efficient management of power consumption. This method adjusts the voltage and operating frequency according to the workload of the system. When the workload of the system is low, the method reduces power consumption by lowering the power supply voltage (VDD) and lowering the clock frequency of the system. When using the DVFS technique, the operating mode of the system is divided into normal mode and low voltage mode.

FIG. 2 is a timing diagram of a DVFS operation of the refresh control circuit of FIG. 1.

In normal mode, the refresh cycle signal (PSRF) is normally activated 'high' with a period of 7.8 ms.

However, in the low voltage mode operation, since the level of the power supply voltage VDD is lowered, the delay amount of each of the inverters 102, 103, 104, and 105 of the oscillator 100 of FIG. 1 increases. Therefore, the activation period of the refresh cycle signal PSRF is also greater than 7.8 ms, which causes a time interval during which the self refresh operation is performed to be larger than the data retention time, resulting in loss of data stored in the memory device.

An object of the present invention is to provide a refresh control circuit capable of generating a refresh cycle signal in the same period as a normal mode even in a low voltage mode according to dynamic voltage and frequency scaling (DVFS).

The refresh control circuit according to the present invention for generating the above object generates an oscillation signal using a plurality of delay elements, but in the low voltage mode to block the path to some delay elements of the plurality of delay elements to generate the oscillation signal. And a periodic signal generator for generating a refresh periodic signal that is activated every predetermined period using the oscillator.

The oscillation signal has the same oscillation period in the normal mode and the low voltage mode.

The oscillator may include a plurality of inverters connected in a ring shape, a resistor connected in series between the plurality of inverters, and a switching unit connected in parallel to the resistors. The switching unit may be turned off in a normal mode operation and turned on in the low voltage mode operation to form a bypass path for the resistor.

Alternatively, the oscillator may include a plurality of inverters connected in a ring form and a switching unit and a capacitor connected in series between a node and a ground voltage terminal between the plurality of inverters. The switching unit may be turned on in the normal mode operation and turned off in the low voltage mode operation to block the inflow of charge to the capacitor.

According to the present invention, the refresh cycle signal can be generated at the same cycle as the normal mode even when the level of the power supply voltage is lowered in the low voltage mode according to the dynamic voltage and the frequency scaling (DVFS). Therefore, the refresh operation can be stably performed even in the low voltage mode.

1 is a block diagram of a conventional refresh control circuit.
2 is a DVFS operation timing diagram of the refresh control circuit of FIG.
3 is a configuration diagram of an embodiment of a refresh control circuit according to the present invention;
4 is a configuration diagram of another embodiment of the oscillator 300 of FIG. 3.
FIG. 5 is a diagram illustrating an embodiment of the periodic signal generator 310 of FIG. 3.
6 is a timing diagram of a DVFS operation of a refresh control circuit according to the present invention;

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

3 is a configuration diagram of an embodiment of a refresh control circuit according to the present invention.

Referring to FIG. 3, the refresh control circuit generates an oscillation signal OSC using a plurality of delay elements, but in a low voltage mode, blocks the paths to some delay elements of the plurality of delay elements to generate the oscillation signal OSC. And a periodic signal generator 310 for generating a refresh cycle signal PSRF which is activated at a predetermined cycle using the generated oscillator 300 and the generated oscillation signal OSC.

The oscillator 300 generates the oscillation signal OSC when the self-refresh command SREF is 'high', and as shown in FIG. 3, the NAND gate 301 and a plurality of inverters connected in a ring form are illustrated. 302, 303, 304, and 305, and a resistor R connected in series between the first and second inverters 302 and 303, and an NMOS transistor NM1 connected in parallel to the resistor R to serve as a switching function. Can be. The NMOS transistor NM1 is driven by receiving a gate signal of the mode signal DVFS_EN. In this case, the mode signal DVFS_EN is a low signal in the normal mode and a high signal in the low voltage mode by the DVFS.

The NMOS transistor NM1 is turned off in the normal mode DVFS_EN = 'Low' and turned on in the low voltage mode DVFS_EN = 'High' to form a bypass path for the resistor R. That is, in the low voltage mode, the level of the power supply voltage VDD is lowered so that the delay amount of each inverter 302, 303, 304, 305 is increased than in the normal mode, thereby bypassing the resistor R on the delay path of the oscillator. By eliminating the delay amount caused by the resistor R, the increase in the delay amount of the inverters 302, 303, 304, and 305 is offset. As a result, the oscillation signal OSC generated by the oscillator 300 may have the same oscillation period in the normal mode and the low voltage mode.

Meanwhile, in the present exemplary embodiment, the resistor R and the NMOS transistor NM1 are connected only between the first and second inverters 302 and 303, but the second and third inverters 303 and 304 may be changed according to the delay amount adjusted. Obviously, the same configuration can be connected between or between the third and fourth inverters 304 and 305.

4 is a configuration diagram of another embodiment of the oscillator 300 of FIG. 3.

As shown in FIG. 4, the oscillator 300 includes a node between a NAND gate 301 connected in a ring form, a plurality of inverters 302, 303, 304, and 305, and third and fourth inverters 304 and 305. And a PMOS capacitor PM1 and a capacitor C connected in series between the ground voltage terminal VSS and a switching role.

The PMOS transistor PM1 receives a gate signal of the mode signal DVFS_EN and is turned on in the normal mode DVFS_EN = 'Low', and turned off in the low voltage mode DVFS_EN = 'High' to block the inflow of charge to the capacitor C. do. That is, the oscillation signal OSC can be generated at the same period as in the normal mode by eliminating the delay amount required in the charging or discharging process of the capacitor C in consideration of the increase in the delay amount of the inverters 302 to 305 during the low voltage mode operation. Can be.

In addition, the same configuration may be connected between the first and second inverters 302 and 303 or between the second and third inverters 303 and 304 according to the delay amount adjusted as described above. Of course, the oscillation unit 300 may be implemented together.

FIG. 5 is a diagram illustrating an embodiment of the periodic signal generator 310 of FIG. 3.

As shown in FIG. 5, the periodic signal generator 310 divides the oscillation signal OSC to generate a divided signal OSCDE having a predetermined period (7.8 ms), and a divided signal ( The pulse generator 603 may generate a refresh cycle signal PSRF using OSCDE. Since this is a well known configuration, a detailed description thereof will be omitted.

6 is a DVFS operation timing diagram of the refresh control circuit according to the present invention.

3 and 4, the delay amount of the oscillator 300 is adjusted by using the mode signal DVFS_EN that is activated as 'high' in the low voltage mode according to the DVFS.

As a result, as shown in FIG. 6, even when the power supply voltage VDD applied to the circuit is low in the low voltage mode, the toggling period of the oscillation signal OSC generated by the oscillator 300 is maintained in the same manner as in the normal mode. In addition, the activation cycle of the refresh cycle signal PSRF may also be maintained at 7.8 kHz, which is the same as that of the normal mode.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

Claims (7)

An oscillation unit for generating an oscillation signal using a plurality of delay elements, and in the low voltage mode, generating an oscillation signal by blocking a path to some delay elements of the plurality of delay elements;
A periodic signal generator for generating a refresh periodic signal that is activated every predetermined period using the oscillation signal.
Refresh control circuit comprising a.
The method of claim 1,
The oscillation signal is
Having the same oscillation period in the normal mode and the low voltage mode
Refresh control circuit.
The method of claim 1,
The oscillating portion
A plurality of inverters connected in a ring form;
A resistor connected in series between the plurality of inverters; And
It includes a switching unit connected in parallel to the resistor
Refresh control circuit.
The method of claim 3, wherein
The switching unit
Turned off during normal mode operation,
Is turned on during the low voltage mode operation to form a bypass path for the resistor
Refresh control circuit.
The method of claim 1,
The oscillating portion
A plurality of inverters connected in a ring form; And
And a switching unit and a capacitor connected in series between a node between the plurality of inverters and a ground voltage terminal.
Refresh control circuit.

6. The method of claim 5,
The switching unit
Turned on during normal mode operation,
Is turned off during the low voltage mode operation to block charge flow into the capacitor
Refresh control circuit.
The method of claim 1,
The periodic signal generator
A division unit for dividing the oscillation signal to generate a division signal having the predetermined period; And
A pulse generator configured to generate the refresh cycle signal using the division signal;
Refresh control circuit.
KR1020110017616A 2011-02-28 2011-02-28 Refresh control circuit KR20120097982A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110017616A KR20120097982A (en) 2011-02-28 2011-02-28 Refresh control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110017616A KR20120097982A (en) 2011-02-28 2011-02-28 Refresh control circuit

Publications (1)

Publication Number Publication Date
KR20120097982A true KR20120097982A (en) 2012-09-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110017616A KR20120097982A (en) 2011-02-28 2011-02-28 Refresh control circuit

Country Status (1)

Country Link
KR (1) KR20120097982A (en)

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