KR20120097768A - Harmonic rejection mixer - Google Patents

Abstract

PURPOSE: A harmonic rejection mixer is provided to improve a harmonic rejection ratio by accurately forming a current ratio using a current mirror gain circuit. CONSTITUTION: A voltage to current conversion part(310) changes an inputted voltage signal into a current signal. A current mirror gain part(320) distributes the current signal to the N number of current signals by mirroring the current signals received from the voltage to current conversion part. A switching part(330) mixes the N number of the current signals received from the current mirror gain part and the N number of local oscillation signal pairs inputted from the outside by frequency. The switching part generates the N number of differential baseband signals and the N number of differential intermediate frequency signals. An output part(340) outputs differential output signals by adding up the N number of the differential baseband signals and the N number of the differential intermediate frequency signals received from the switching part.

Description

Harmonic Removal Mixer {HARMONIC REJECTION MIXER}

The present invention relates to a wireless communication system, and more particularly to a harmonic rejection mixer for removing harmonic components generated at the receiving end of the wireless communication system.

Recently, the use of digital wireless communication systems is increasing. For example, Wireless Local Area Networks (LANs), Digital Video Broadcasting-Terrestrial (DVB-T), Code Division Multiple Access (CDMA), and Wideband Code Division Multiple Access (Wideband). Systems such as Code Division Multiple Access (WCDMA) are getting more and more attention.

One of the requirements in such a wireless communication system is a receiver with high reception performance. The receiver used in such a wireless communication system is a mixer for down-converting a high frequency Radio Frequency (RF) signal into a low frequency Intermediate Frequency (IF) or baseband signal for signal processing. It includes (mixer).

The mixer 10 uses local oscillation signals LOs generated by a local oscillator LO to downconvert the RF input signal RF _IN . As illustrated in FIG. 1, a local oscillation signal When a square wave is used, harmonic components (3LOs, 5LOs, 7LOs) occur at frequencies that are odd multiples of the fundamental frequency of the local oscillation signal, which affects the performance of the receiver.

In order to improve the performance of the receiver, an attempt has been made to remove such harmonic components, and as a result, a double balanced mixer type using a Gilbert cell structure is now widely used. This will be described with reference to FIG. 2.

FIG. 2A is a conceptual diagram for explaining a conventional harmonic elimination mixer, and FIG. 2B is a circuit diagram for explaining a conventional harmonic elimination mixer. 2 (a) and 2 (b) show a harmonic elimination mixer using three Gilbert cell structures as an example. Since the Gilbert cell structure is a well known structure, a detailed description thereof will be omitted.

Referring to FIGS. 2A and 2B, a conventional harmonic elimination mixer includes a transconductor 110, a switching unit 120, and an output unit 130.

가 되도록 한다. 이는 이러한 전류 비를 이용하면 3차 및 5차 하모닉 성분이 효과적으로 제거되기 때문이다. The transconductor 110 receives an RF voltage signal (RF _{IN +} , RF _{IN −} ) in a differential mode and converts it into a current signal. RF _{IN +} and RF _{IN -} refer to signals with opposite phases. The transconductor 110 adjusts the converted current signal to have a set current ratio when converting the RF voltage signal into a current signal. In general, when using three Gilbert cell structures, the current ratio between the current signals output from the transconductor 110 is

To be This is because using this current ratio effectively removes the third and fifth harmonic components.

To this end, the transconductor 110 includes three transconductance (gm) stages 111, 112, and 113 for converting an input RF voltage signal (RF _{IN +} , RF _{IN −} ) into a current signal.

가 되도록 하기 위하여는

의 전류 비로 전류를 공급하는 전류원(141, 142, 143)을 각각의 트랜스 컨덕턴스(111, 112, 113)에 연결한다. 이 때, 트랜스 컨덕턴스단(111, 112, 113) 간의 사이즈의 비는

가 되도록 한다. In order to obtain a set current ratio between the current signals output from each of the transconductance stages 111, 112, and 113, a current source 141, 142, 143 having a set current ratio in each of the transconductance stages 111, 112, 113. ) Is connected. For example, the current ratio between the current signals output from the transconductor 110

In order to become

The current sources 141, 142, and 143, which supply current at a current ratio of, are connected to the transconductances 111, 112, and 113, respectively. At this time, the ratio of the size between the transconductance stages (111, 112, 113)

To be

The switching unit 120 receives a plurality of local oscillation signal pairs LO1 +, LO1-; LO2 +, LO2-; and LO3 +, which receive current signals received from the transconductor 110 from an external local oscillator (LO). , LO3-), respectively. To this end, the switching unit 120 may mix three current signals received from the transconductor 110 and each of a plurality of local oscillation signal pairs LO1 +, LO1-; LO2 +, LO2-; LO3 +, and LO3-. And switching stages 121, 122, and 123.

The output unit 130 sums the intermediate frequency signals received from the switching unit 120 and outputs the output V _{OUT +} and V _{OUT −} .

The conventional harmonic rejection mixer as described above with reference to FIGS. 2A and 2B uses three transconductance stages 111, 112, and 113 for gain adjustment to obtain a set current ratio. Therefore, the linearity of the entire harmonic rejection mixer is lowered by the nonlinear components generated at the transconductance stages 111, 112, and 113, respectively.

In addition, the conventionally used harmonic rejection mixer as described above uses three current sources 141, 142, and 143 for obtaining the current ratio set in each of the transconductance stages 111, 112, and 113. It is difficult to obtain an accurate current ratio between these current sources 141, 142, 143.

Accordingly, the present invention provides a harmonic rejection mixer with improved linearity using one voltage current conversion stage.

In addition, the present invention provides a harmonic rejection mixer having an improved harmonic rejection ratio by implementing an accurate current ratio.

Other objects of the present invention are to be inferred from the following examples and detailed description.

To this end, the harmonic rejection mixer according to an embodiment of the present invention, a voltage current converter for converting an input voltage signal into a current signal; A current mirror gain unit for mirroring current signals received from the voltage current converter and distributing them into N current signals having current ratios set therebetween; N differential baseband signals or N differentials are obtained by frequency mixing each of the N current signals received from the current mirror gain unit and the N local oscillator (LO) signal pairs input from the outside. A switching unit generating an intermediate frequency (IF) signal; And an output unit for outputting a differential output signal by summing N differential baseband signals or N differential intermediate frequency signals received from the switching unit.

The present invention as described above has the advantage that the linearity is improved as compared with the conventional harmonic rejection mixer, because one voltage and current conversion stage is used.

In addition, the present invention has an advantage of improving the harmonic rejection rate by implementing an accurate current ratio using a current mirror gain circuit.

1 is a conceptual diagram illustrating a harmonic component affecting the performance of a receiver;
2A is a conceptual diagram for explaining a harmonic elimination mixer conventionally used;
2 (b) is a circuit diagram for explaining a harmonic rejection mixer conventionally used;
3 (a) is a conceptual diagram for explaining a harmonic removal mixer according to an embodiment of the present invention,
3 (b) is a circuit diagram for explaining a harmonic removal mixer according to an embodiment of the present invention,
4 is a circuit diagram illustrating a voltage current converter according to another embodiment of the present invention;
5 is a circuit diagram illustrating a current source added to a current mirror gain unit according to an embodiment of the present invention;
6 is a circuit diagram illustrating an output unit according to another exemplary embodiment of the present disclosure;
7 is a circuit diagram illustrating a harmonic rejection mixer according to another embodiment of the present invention.

In the following description of the present invention, detailed descriptions of well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users and operators. Therefore, the definition should be made based on the contents throughout the specification.

As described above, in a receiver used in a wireless communication system, when converting a high frequency radio frequency signal into an intermediate frequency signal or a baseband signal for processing a received signal, when using a square wave as a local oscillation signal, The harmonic component is generated at a frequency that is an odd multiple of the fundamental frequency of the oscillation signal, which affects the performance of the receiver. In particular, the linearity is significantly impaired by the third and fifth harmonic components.

의 전류 비를 갖도록 분배하고, 분배된 전류 신호들을 국부 발진 신호와 주파수 혼합한 후, 혼합된 신호들을 더하는 것이다. One effective way to remove these tertiary and fifth harmonic components is to use a current signal output from the transconductor.

Distribution to have a current ratio of < RTI ID = 0.0 > and then < / RTI >

To this end, conventionally, the RF voltage signal is converted into a current signal by using three transconductance stages, but as described above, linearity is largely impaired when three transconductance stages are used.

Therefore, in the present invention, in order to improve linearity and harmonic rejection rate, the RF voltage signal is converted into one current signal using one transconductance stage, and the current ratio set by using the current mirror gain circuit is converted into a current signal. The present invention proposes a method of distributing three current signals.

In the following description of embodiments of the present invention, a current signal converted from an RF voltage signal is divided into three current signals having a current ratio set by using a current mirror gain circuit, and a harmonic component using the distributed current signal. A mixer for eliminating the circuit diagram will be illustrated and described. However, the present invention is not limited thereto, and the present invention may be applied to a circuit for distributing to less than three or four or more current signals using a current mirror gain circuit.

라고 가정하여 기술할 것이나, 본 발명이 이에 한정되는 것은 아니며, 설계자의 의도에 따라 그 비율을 달리할 수 있다. In addition, in the following description of embodiments of the present invention, the current ratio between the current signals converted using the current mirror gain circuit is

Although the description will be made on the assumption that the present invention is not limited thereto, the ratio may be varied according to the intention of the designer.

For convenience of explanation, hereinafter, the transconductor is referred to as a voltage current converter, and the transconductance end is referred to as a voltage current converter.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A is a conceptual diagram illustrating a harmonic removal mixer according to an embodiment of the present invention. The harmonic rejection mixer according to an embodiment of the present invention illustrated in FIG. 3A uses a differential mode. Hereinafter, a concept of a harmonic elimination mixer according to an embodiment of the present invention will be briefly described with reference to FIG. 3A.

Referring to FIG. 3A, a harmonic rejection mixer according to an embodiment of the present invention includes a voltage current converter 310, a current mirror gain 320, a switch 330, and an output. The unit 340 is included.

The voltage current converter 310 converts an input RF voltage signal into a current signal. That is, the voltage current converter 310 receives the RF voltage signals RF _{IN +} and RF _{IN − in the} differential mode, and converts the input RF voltage signals RF _{IN +} and RF _{IN −} into current signals. . Here, 'RF _{IN +} ' and 'RF _IN- ' mean signals with opposite phases. In the embodiments of the present invention, the voltage current converter 310 is composed of one voltage current converter stage, and thus, the voltage current converter and the voltage current are described below for proper representation of the reference numeral '310'. It is mixed and described in a conversion stage.

The current mirror gain unit 320 divides and outputs a current signal received from the voltage current converter 310 into a set number of current signals, and adjusts the gain to have a set current ratio between the output current signals. That is, the current signal received from the voltage current converter 310 is mirrored according to the set mirror ratio. To this end, sizes of a plurality of transistors (not shown) included in the current mirror gain unit 320 are predetermined for gain adjustment. That is, the gain of the current signal received by the current mirror gain unit 320 is adjusted by each of the transistors. The size of the transistor may mean 'Width / Length' (hereinafter, referred to as W / L) of a gate.

The switching unit 330 may include gain-controlled current signals received from the current mirror gain unit 320 and a plurality of local oscillation signal pairs LO1 +, LO1-; LO2 +, which are received from an external local oscillator (not shown). Frequency conversion of LO2-; LO3 +, LO3-) down-converts to produce an intermediate frequency signal or baseband signal. To this end, the switching unit 330 includes a plurality of switching stages 331, 332, 333, and each switching stage 331, 332, 333 has a gain-controlled current signal for each local oscillation signal pair. Performs an operation of switching to (LO1 +, LO1-; LO2 +, LO2-; LO3 +, LO3-).

Each of the local oscillation signals LO1 +, LO1-, LO2 +, LO2-, LO3 +, LO3- has equally spaced phase differences set to each other to produce multiple switching currents. Meanwhile, '+' and '-' mean that the phase is reversed.

The output unit 340 sums the intermediate frequency signals or the baseband signals received from the respective switching stages 331, 332, and 333 and outputs them (V _{OUT +} , V _{OUT −} ). The intermediate frequency signal or the baseband signal output from the output unit 340 is a signal from which the harmonic component is removed by the operation of the above components.

Since the harmonic rejection mixer according to the exemplary embodiment of the present invention described with reference to FIG. 3A performs gain adjustment in the current mirror gain unit 320 using the current mirror, the voltage-current converter 310 is used. Can be configured as a voltage-current conversion stage.

As mentioned, the harmonic rejection mixer according to the prior art described with reference to Fig. 2A uses three voltage current conversion stages 111, 112, and 113, so that each voltage current conversion stage 111 is used. , The linearity of the entire harmonic rejection mixer is degraded by the nonlinear characteristics occurring at (112, 113).

However, since the harmonic rejection mixer according to an embodiment of the present invention described with reference to FIG. 3 (a) uses one voltage and current conversion stage 310, linearity is improved compared to the conventional harmonic rejection mixer. have.

In addition, the harmonic rejection mixer according to the related art described with reference to FIG. 2A uses separate current sources 141, 142, and 143 for current ratio adjustment, and the current sources 141, 142, and 143 in a manufacturing process. It is difficult to keep the current ratio between) constant.

However, in the harmonic rejection mixer according to the embodiment of the present invention described with reference to FIG. 3A, the current ratio is kept constant because the current mirror gain unit 320 adjusts the current ratio, thereby improving the harmonic rejection ratio. There is an advantage.

Because the current mirror gain 320 may be designed on one wafer in the design process, process variation occurs equally for all devices on the same wafer, and the current mirror gain Since the current ratio to be implemented in the unit 320 is a relative parameter, the ratio is always kept constant so that the desired current ratio can be obtained.

In the above, the principle of the harmonic removal mixer according to an embodiment of the present invention has been described. Hereinafter, specific circuits and operations of the harmonic elimination mixer according to embodiments of the present invention will be described with reference to the accompanying drawings.

3B is a circuit diagram illustrating a harmonic rejection mixer according to an embodiment of the present invention. The harmonic rejection mixer according to an embodiment of the present invention illustrated in FIG. 3B uses a differential mode. Hereinafter, the harmonic rejection mixer according to an embodiment of the present invention will be described with reference to FIG. 3B. And operation.

Referring to FIG. 3B, the harmonic rejection mixer according to an embodiment of the present invention includes a voltage current converter 310a and 310b, a current mirror gain unit 320, a switching unit 330, and an output unit ( 340).

The voltage current converters 310a and 310b include a first voltage current converter 310a and a second voltage current converter 310b, and input RF voltage signals RF _{IN +} and RF _{IN −} in a differential mode. ) Is converted into a current signal.

Meanwhile, although the voltage and current converters 310a and 310b are separately illustrated in the drawing, each of the voltage and current converters 310a and 310b receives and inputs the RF voltage signals RF _{IN +} and RF _{IN −} in a differential mode. It is obvious to those skilled in the art that each of these is converted into a current signal, and substantially one voltage current conversion stage is used.

Hereinafter, specific configurations of the voltage current converters 310a and 310b will be described.

The first voltage current converter 310a includes a first N-type transistor N1 and a second N-type transistor N2 having a cascode structure.

The source of the first N-type transistor N1 is connected to the drain of the second N-type transistor N2, the drain is connected to one end of the current mirror gain 320, and the gate has a bias voltage V _b1 . Is approved. The bias voltage V _b1 input to the first N-type transistor N1 is a DC bias in which the first N-type transistor N1 can operate in a saturation region, and its value is changed according to design intention. Can vary. Meanwhile, the first N-type transistor N1 separates the input and the output of the second N-type transistor N2 from each other.

The source of the second N-type transistor N2 is grounded, and an RF voltage signal RF IN + is input to the gate by being loaded on the voltage V _{IN +} . The voltage V _{IN +} is a DC bias for driving the second N-type transistor N2.

The second voltage current converter 310 includes a third N-type transistor N3 and a fourth N-type transistor N4 having a cascode structure.

The source of the third N-type transistor N3 is connected to the drain of the fourth N-type transistor N4, the drain is connected to one end of the current mirror gain unit 320, and the gate has a bias voltage V _b1 . Is approved. The bias voltage V _b1 input to the third N-type transistor N3 is a DC bias in which the third N-type transistor N3 can operate in a saturation region, and its value is changed according to design intention. Can vary. Meanwhile, the third N-type transistor N3 separates the input and the output of the fourth N-type transistor N4 from each other.

The source of the fourth N-type transistor N4 is grounded, and an RF voltage signal RF _{IN −} is input to the gate by being loaded on the voltage V _{IN −} . The voltage V _{IN −} is a DC bias for driving the fourth N-type transistor N4.

Meanwhile, the first and second capacitors C1 and C2 which remove an alternating current (AC) signal component between the gate and the ground of the first N-type transistor N1 and between the gate and the ground of the third N-type transistor N3. ) May be further included.

The current mirror gain unit 320 is driven by the voltage source V _DD , and distributes the current signal received from the voltage current converters 310a and 310b to three switching stages 331, 332, and 333. The gain is adjusted to have a set current ratio between the current signals being distributed. That is, the current signal is distributed to three switching stages 331, 332, and 333 according to the set mirror ratio.

Hereinafter, the specific structure of the current mirror gain part 320 is demonstrated.

The current mirror gain unit 320 includes first to eighth P-type transistors P1, P2, P3, P4, P5, P6, P7, and P8, each of which is connected to a voltage source V _DD .

The drain of the first P-type transistor P1 and the drain of the eighth P-type transistor P8 are connected to the first voltage current converter 310a and the second voltage current converter 310b, respectively. Specifically, the drain of the first P-type transistor P1 is connected to the drain of the first N-type transistor N1 of the first voltage current converter 310a, and the drain of the eighth P-type transistor P8 is formed of the first P-type transistor P8. It is connected to the drain of the third N-type transistor (N3) of the two voltage current converter 310.

The gate and the drain of the first P-type transistor P1 are connected to each other, and the gates of the second P-type transistor P2, the fourth P-type transistor P4, and the sixth P-type transistor P6 are the first P-type transistor. It is connected to the gate of the transistor P1.

The gate and the drain of the eighth P-type transistor P8 are connected to each other, and the gates of the third P-type transistor P3, the fifth P-type transistor P5, and the seventh P-type transistor P7 are the eighth P-type. It is connected to the gate of transistor P8.

Drains of the second to seventh P-type transistors P2, P3, P4, P5, P6, and P7 are connected to the switching unit 330.

로 하고자 하는 경우, 제 31 내지 제 34 P형 트랜지스터(P31, P32, P33, P34)의 사이즈의 비를

로 결정할 수 있다. 이 때, 각 트랜지스터들(P31, P32, P33, P34)의 사이즈는 게이트의 W/L 일 수 있다. 한편, 각 트랜지스터들(P31, P32, P33, P34)의 사이즈 비는

의 전류 비를 만드는 범위 내에서 각 트랜지스터들(P31, P32, P33, P34)의 드레인-소스에 걸리는 전압(V_DS)에 따라 결정될 수 있다.
The sizes of the transistors P31, P32, P33, and P34 are determined in advance in order to have a current ratio set between the current signals distributed by the current mirror gain unit 320 having the above configuration. For example, the current ratio of the current signal distributed to the switching stages 331, 332, 333 may be determined.

In this case, the ratio of the size of the 31st to 34th P-type transistors (P31, P32, P33, P34)

Can be determined. In this case, the sizes of the transistors P31, P32, P33, and P34 may be W / L of gates. On the other hand, the size ratio of each transistor (P31, P32, P33, P34) is

The voltage V _DS applied to the drain-source of each of the transistors P31, P32, P33, and P34 may be determined within a range to create a current ratio of.

The switching unit 330 is a plurality of local oscillation signal pairs (LO1 +, LO1-; LO2 +, LO2-; LO3 +, LO3-) received from an external local oscillator and a current signal received from the current mirror gain unit 320. These frequencies are mixed to output an intermediate frequency signal or a baseband signal.

The switching unit 330 includes a first switching stage 331, a second switching stage 332, and a third switching stage 333. Each of the switching stages 331, 332, 333 is input with a pair of local oscillation signals having opposite phases.

Hereinafter, the specific configuration of the switching unit 330 will be described.

The first switching stage 331 includes ninth through twelfth P-type transistors P9, P10, P11, and P12. The ninth and tenth transistors P9 and P10 and the eleventh and twelfth transistors P11 and P12 each form a differential transistor pair.

Sources of the ninth through twelfth P-type transistors P9, P10, P11, and P12 are connected to the current mirror gain unit 320. Specifically, sources of the ninth P-type transistor P9 and the tenth P-type transistor P10 are connected to the drains of the second P-type transistor P2 of the current mirror gain 320 and the eleventh P-type transistor. A source of the P11 and the twelfth P-type transistor P12 is connected to the drain of the third P-type transistor P3 of the current mirror gain unit 320.

The drains of the ninth P-type transistor P9 and the tenth P-type transistor P10 are connected to each other, and the drains of the eleventh P-type transistor P11 and the twelfth P-type transistor P12 are connected to each other.

The local oscillation signal LO1 + is input to the gates of the ninth P-type transistor P9 and the twelfth P-type transistor P12, and to the gates of the tenth P-type transistor P10 and the eleventh P-type transistor P11. The local oscillation signal LO1- is input, and the gates of the tenth P-type transistor P10 and the eleventh P-type transistor P11 are connected to each other. The local oscillation signal LO1 + and the local oscillation signal LO1- mean signals in which phases are opposite to each other.

The second switching stage 332 includes thirteenth to sixteenth P-type transistors P13, P14, P15, and P16. The thirteenth and fourteenth transistors P13 and P14 and the fifteenth and sixteenth transistors P15 and P16 form a differential transistor pair, respectively.

Sources of the thirteenth to sixteenth P-type transistors P13, P14, P15, and P16 are connected to the current mirror gain unit 320. Specifically, the sources of the thirteenth P-type transistor P13 and the fourteenth P-type transistor P14 are connected to the drains of the fourth P-type transistor P4 of the current mirror gain 320 and the fifteenth P-type transistor. A source of P15 and a sixteenth P-type transistor P16 is connected to a drain of the fifth P-type transistor P5 of the current mirror gain unit 320.

The drains of the thirteenth P-type transistor P13 and the fourteenth P-type transistor P14 are connected to each other, and the drains of the fifteenth P-type transistor P15 and the sixteenth P-type transistor P16 are connected to each other.

The local oscillation signal LO2 + is input to the gates of the thirteenth P-type transistor P13 and the sixteenth P-type transistor P16, and to the gates of the fourteenth P-type transistor P14 and the fifteenth P-type transistor P15. The local oscillation signal LO2- is input, and the gates of the fourteenth P-type transistor P14 and the fifteenth P-type transistor P15 are connected to each other. The local oscillation signal LO2 + and the local oscillation signal LO2- mean signals in which phases are opposite to each other.

The third switching stage 333 includes the seventeenth to twentieth P-type transistors P17, P18, P19, and P20. The seventeenth and eighteenth transistors P17 and P18 and the nineteenth and twentieth transistors P19 and P120 each form a differential transistor pair.

Sources of the seventeenth through twentieth P-type transistors P17, P18, P19, and P20 are connected to the current mirror gain unit 320. Specifically, the sources of the seventeenth P-type transistor P17 and the eighteenth P-type transistor P18 are connected to the drains of the sixth P-type transistor P6 of the current mirror gain 320 and the nineteenth P-type transistor. A source of P19 and a twentieth P-type transistor P20 is connected to the drain of the seventh P-type transistor P7 of the current mirror gain unit 320.

Drains of the seventeenth P-type transistor P17 and the eighteenth P-type transistor P18 are connected to each other, and drains of the nineteenth P-type transistor P19 and the twentieth P-type transistor 20P are connected to each other.

The local oscillation signal LO3 + is input to the gates of the seventeenth P-type transistor P17 and the twentieth P-type transistor P20, and the gates of the eighteenth P-type transistor P18 and the nineteenth P-type transistor P19. The local oscillation signal LO3- is input, and gates of the eighteenth P-type transistor P18 and the nineteenth P-type transistor P19 are connected to each other. The local oscillation signal LO3 + and the local oscillation signal LO3- mean signals whose phases are opposite to each other.

The intermediate frequency signal or the baseband signal generated by frequency mixing at each switching stage 331, 332, and 333 is output to the output unit 340. Specifically, the ninth P-type transistor P9, the tenth P-type transistor P10, the thirteenth P-type transistor P13, the fourteenth P-type transistor P14, the seventeenth P-type transistor P17, and the eighteenth The drain of the P-type transistor P18 is connected to the output unit 340 through the first node n1, and includes the eleventh P-type transistor P11, the twelfth P-type transistor P12, and the fifteenth P-type transistor ( The drain of P15 and the sixteenth P-type transistor P16 are connected to the output unit 340 through the second node n2.

The output unit 340 sums the intermediate frequency signals or the baseband signals received from the switching unit 330 and outputs them (V _{OUT +} , V _{OUT −} ).

Hereinafter, the specific structure of the output part 340 is demonstrated.

The output unit 340 includes a fifth N-type transistor N5, a sixth N-type transistor N6, a first resistor R1, and a second resistor R2.

The source of the fifth N-type transistor N5 is grounded, and the drain thereof is connected to the first node n1. The source of the sixth N-type transistor N6 is grounded, the drain is connected to the second node n2, and the gate is connected to the gate of the fifth N-type transistor N5 through the fourth node n4.

One end of the first resistor R1 is connected between the first node n1 and the fifth N-type transistor N5, and the other end thereof is connected to the second resistor R2 through the third node n3. .

One end of the second resistor R2 is connected between the second node n2 and the sixth N-type transistor N6, and the other end thereof is connected to the first resistor R1 through the third node n3. .

The third node n3 and the fourth node n4 are connected to each other.

The output V _{OUT +} terminal is connected between one end of the first resistor R1 and the drain of the fifth N-type transistor N5, and the output V _{OUT −} terminal is connected to one end of the second resistor R2. It is connected between the drain of the 6 N-type transistor (N6).

In FIG. 3B, an example in which the output unit 340 is configured as an active load is described. As described above, when the output unit 340 is configured as an active load stage, there is an advantage of easily increasing the output gain. Meanwhile, the configuration of the output unit 340 may be changed according to design intent, which will be described later with reference to the accompanying drawings.

As described with reference to FIG. 3, the harmonic rejection mixer according to an embodiment of the present invention uses one voltage current conversion stage to convert an RF voltage signal into a current signal. The linearity is improved compared to the harmonic rejection mixer using the same three voltage current conversion stages.

In addition, as described above, the harmonic rejection mixer according to an embodiment of the present invention distributes the current signal output from the voltage-current conversion stage to have a current ratio set by using a current mirror gain circuit. Compared to the harmonic rejection mixer using three current sources for obtaining the set current ratio as described above, the harmonic rejection ratio is improved.

Meanwhile, in order to improve linearity, the voltage-current converters 310a and 310b may be configured by adding a transistor that operates in a triode region, which is illustrated in FIG. 4. In FIG. 4, only the voltage current converters 310a and 310b are separately shown among the components illustrated in FIG. 3B.

Hereinafter, the voltage-current converters 310a and 310b according to another embodiment of the present invention will be described in detail with reference to FIG. 4, and the description of the same components as those shown in FIG. 3B will be omitted. do.

Referring to FIG. 4A, in addition to the components shown in FIG. 3B, the first voltage current converter 310a according to another embodiment of the present invention may have a seventh N-type structure having a cascode structure. The transistor N7 includes an eighth N-type transistor N8, a third resistor R3, a fourth resistor R4, and a third capacitor C3.

The source of the seventh N-type transistor N7 is connected to the drain of the eighth N-type transistor N8, and the drain is connected to the drain of the first N-type transistor N1 to mirror the current through the fifth node n5. It is connected to the gain unit 320.

The source of the eighth N-type transistor N8 is grounded through the sixth node n6.

One end of the third resistor R3 is connected to the gate of the first N-type transistor N1, and the other end thereof is connected to the gate of the seventh N-type transistor N7.

One end of the third capacitor C3 is connected to the gate of the eighth N-type transistor N8, and the other end thereof is connected to the gate of the second N-type transistor N2.

One end of the fourth resistor R4 is connected between the third capacitor C3 and the eighth N-type transistor N8, and a voltage V _{IN +} −V _aux is input to the other end thereof. Here, V _{IN +} is a DC bias for driving the second N-type transistor N2, and V _aux means a voltage (bias) shifted from the DC bias of the second N-type transistor N2.

On the other hand, referring to Figure 4 (b), the second voltage current converter 310b according to another embodiment of the present invention, in addition to the components shown in Figure 3 (b), the ninth of the cascode structure An N-type transistor N9, a tenth N-type transistor N10, a fifth resistor R6, a fourth resistor R6, and a fourth capacitor C4 are included.

The source of the ninth N-type transistor N9 is connected to the drain of the tenth N-type transistor N10, and the drain is connected to the drain of the third N-type transistor N3 so as to provide current through the seventh node n7d. It is connected to the mirror gain unit 320.

The source of the tenth N-type transistor N10 is grounded through the eighth node n8.

One end of the fifth resistor R5 is connected to the gate of the third N-type transistor N3, and the other end thereof is connected to the gate of the ninth N-type transistor N9.

One end of the fourth capacitor C4 is connected to the gate of the tenth N-type transistor N10, and the other end thereof is connected to the gate of the fourth N-type transistor N4.

One end of the sixth resistor R6 is connected between the fourth capacitor C4 and the tenth N-type transistor N10, and a voltage V _{IN --} V _aux is input to the other end. Here, V _{IN −} is a DC bias for driving the fourth N-type transistor N4, and V _aux means a voltage (bias) shifted from the DC bias of the fourth N-type transistor N4.

As described with reference to FIGS. 4A and 4B, transistors N7, N8, N9, and N10 operating in the triode region are added to the voltage current conversion stages 310a and 310b operating in the saturation region. This has the advantage of improving linearity.

On the other hand, for high voltage-to-current conversion gain, the transconductance of the voltage-current conversion stage must be large. Since the transconductance is proportional to the amount of current, the transconductance can be increased by increasing V _IN or increasing the size of the voltage current converter stage. However, in this case, a large amount of current flows through the switching unit 330, thereby degrading performance. This problem can be solved by adding a current source connected to the current mirror gain unit 320. In other words, some current can be solved by distributing some current to the current source before the current is supplied from the current mirror gain unit 320 to the switching unit.

The equivalent circuit of such a current source may be represented by a transistor and a voltage source input to the transistor. This is illustrated in FIG. 5. In FIG. 5, only relevant parts are separately shown.

Referring to FIG. 5A, the source of the twenty-first P-type transistor P21 is connected to the current mirror gain unit 320 through the ninth node n9, and the drain thereof is connected to the fifth node n5. It is connected to the current mirror gain unit 320, and the voltage V _b2 is input to the gate.

Referring to FIG. 5B, the source of the twenty-second P-type transistor P22 is connected to the current mirror gain unit 320 through the tenth node n10, and the drain thereof is connected to the seventh node n7. It is connected to the current mirror gain unit 320, and the voltage V _b2 is input to the gate. In FIGS. 5A and 5B, the voltage V _b2 is determined according to the amount of current distributed by the twenty-first P-type transistor P21 and the twenty-second P-type transistor P22.

As described above, when the transistors P21 and P22 that receive the voltage V _b2 are added to both ends of the current mirror gain unit 320, even if the current flowing through the transconductance stage is increased, it causes a problem of switching operation. There is an advantage to increase the voltage-current conversion gain without.

On the other hand, the output unit 340 may be configured using only a resistance, which is shown in Figure 6 (a). In FIG. 6A, only the output unit 340 of the components illustrated in FIG. 3B is illustrated.

Referring to FIG. 6A, the output unit 340 according to another embodiment of the present invention includes a seventh resistor R7 and an eighth resistor R8.

One end of the seventh resistor R7 is connected to the switching unit 330 through the first node n1, and the other end thereof is grounded.

One end of the eighth resistor R8 is connected to the switching unit 330 through the second node n2, and the other end thereof is grounded.

The first node (n1) and a seventh resistor (R7) between the output (V _{OUT +)} and the contact is closed, the second node (n2) and an eighth resistor (R8) in the output between the (V _{OUT -)} terminal is connected do.

On the other hand, in order to improve the linearity, the output unit 340 may be configured by using a LC (Leactance-Capacitance) tank (tank), which is shown in Figure 6 (b). In FIG. 6B, only the output unit 340 of the components illustrated in FIG. 3B is illustrated.

Referring to FIG. 6B, the output unit 340 according to another embodiment of the present invention includes a first LC tank 341 and a second LC tank 342.

The first LC tank 341 includes a first coil L1 and a fifth capacitor C5 connected in parallel with each other. One end of the first coil L1 and the fifth capacitor C5 is connected to each other and connected to the switching unit 330 through the first node n1, and the other end is grounded.

The second LC tank 342 includes a second coil L2 and a sixth capacitor C6 connected in parallel with each other. One end of the second coil L2 and the sixth capacitor C6 is connected to each other and connected to the switching unit 330 through the second node n2, and the other is grounded.

Since the noise problem does not occur when the output unit 340 is configured using the LC tank, the output unit 340 may exhibit high performance at the resonance frequency. That is, improved linearity can be guaranteed.

In the above, embodiments of the present invention using the differential mode have been described. Hereinafter, an embodiment using a common mode will be described with reference to FIG. 7.

7 is a circuit diagram illustrating a harmonic rejection mixer using a common mode according to another embodiment of the present invention.

Referring to FIG. 7, the harmonic rejection mixer according to another embodiment of the present invention includes a voltage current converter 310, a current mirror gain unit 320, a switching unit 330, and an output unit 340.

The voltage current converter 310 converts an input RF voltage signal into a current signal.

Hereinafter, the specific configuration of the voltage current converter 310 will be described.

The voltage current converter 310 includes an eleventh N-type transistor N11 and a twelfth N-type transistor N12 having a cascode structure.

The source of the eleventh N-type transistor N11 is connected to the drain of the twelfth N-type transistor N12, and the drain is connected to one end of the current mirror gain unit 320, and the gate has a bias voltage V _b1 . Is approved.

The source of the twelfth N-type transistor N12 is grounded, and an RF voltage signal RF _IN is loaded on the voltage V _{IN at a} gate thereof.

An eleventh capacitor C11 may be further included between the gate and the ground of the first N-type transistor N11 to remove an AC signal component.

The current mirror gain unit 320 is driven by the voltage source V _DD and supplies a current to the switching unit 330. In addition, the current mirror gain unit 320 distributes the current signal received from the voltage current converter 310 to the three switching stages 331, 332, 333, and gains to have a current ratio set between the distributed current signals. Adjust.

Hereinafter, the specific structure of the current mirror gain part 320 is demonstrated.

The current mirror gain unit 320 includes thirty-first to thirty-fourth P-type transistors P31, P32, P33, and P34, each source connected to a voltage source V _DD .

A drain of the 31 st P-type transistor P1 is connected to the voltage current converter 310. Specifically, the drain of the 31 st P-type transistor P31 is connected to the drain of the eleventh N-type transistor N11 of the voltage current converter 310.

The gate and the drain of the thirty-first P-type transistor P31 are connected to each other, and the gates of the thirty-second to thirty-fourth P-type transistors P32, P33, and P34 are connected to the gate of the thirty-first P-type transistor P31.

Drains of the thirty-second to thirty-fourth P-type transistors P32, P33, and P34 are connected to the switching unit 330.

로 하고자 하는 경우, 제 31 내지 제 34 P형 트랜지스터(P31, P32, P33, P34)의 사이즈의 비를

로 결정할 수 있다. 이 때, 각 트랜지스터들(P31, P32, P33, P34)의 사이즈는 게이트의 W/L 일 수 있다. 한편, 각 트랜지스터들(P31, P32, P33, P34)의 사이즈 비는

의 전류 비를 만드는 범위 내에서 각 트랜지스터들(P31, P32, P33, P34)의 드레인-소스에 걸리는 전압(V_DS)에 따라 결정될 수 있다.
The sizes of the transistors P31, P32, P33, and P34 are determined in advance in order to have a current ratio set between the current signals distributed by the current mirror gain unit 320 having the above configuration. For example, the current ratio of the current signal distributed to the switching stages 331, 332, 333 may be determined.

In this case, the ratio of the size of the 31st to 34th P-type transistors (P31, P32, P33, P34)

Can be determined. In this case, the sizes of the transistors P31, P32, P33, and P34 may be W / L of gates. On the other hand, the size ratio of each transistor (P31, P32, P33, P34) is

The voltage V _DS applied to the drain-source of each of the transistors P31, P32, P33, and P34 may be determined within a range to create a current ratio of.

The switching unit 330 is a plurality of local oscillation signal pairs (LO1 +, LO1-; LO2 +, LO2-; LO3 +, LO3-) received from an external local oscillator and a current signal received from the current mirror gain unit 320. These frequencies are mixed to output an intermediate frequency signal or a baseband signal.

Hereinafter, the specific configuration of the switching unit 330 will be described.

The switching unit 330 includes a first switching stage 331, a second switching stage 332, and a third switching stage 333. Each of the switching stages 331, 332, 333 is input with a pair of local oscillation signals having opposite phases.

The first switching stage 331 includes a 35 th P-type transistor P35 and a 36 th P-type transistor P36.

Sources of the 35 th P-type transistor P35 and the 36 th P-type transistor P36 are connected to the drain of the 32nd P-type transistor P32 of the current mirror gain unit 320. The local oscillation signal LO1 + is input to the gate of the 35 th P-type transistor P35, and the local oscillation signal LO1-is input to the gate of the 36 th P-type transistor P36.

The second switching stage 332 includes a 37th P-type transistor P37 and a 38th P-type transistor P38.

Sources of the 37th P-type transistor P37 and the 38th P-type transistor P38 are connected to the drain of the 33rd P-type transistor P33 of the current mirror gain unit 320. The local oscillation signal LO2 + is input to the gate of the 37th P-type transistor P37, and the local oscillation signal LO2- is input to the gate of the 38th P-type transistor P38.

The third switching stage 333 includes a 39th P-type transistor P39 and a 40th P-type transistor P40.

Sources of the 39th P-type transistor P39 and the 40th P-type transistor P40 are connected to the drain of the 34th P-type transistor P34 of the current mirror gain unit 320. The local oscillation signal LO3 + is input to the gate of the 39th P-type transistor P39, and the local oscillation signal LO3- is input to the gate of the 40th P-type transistor P40.

The intermediate frequency signal or the baseband signal generated by frequency mixing at each switching stage 331, 332, and 333 is output to the output unit 340. Specifically, drains of the 35 th P-type transistor P35, the 37 th P-type transistor P37, and the 39 th P-type transistor P39 are connected to the output unit 340 through the eleventh node n11, and Drains of the 36 P-type transistor P36, the 38 th P-type transistor P38, and the 40 th P-type transistor P40 are connected to the output unit 340 through the twelfth node n12.

The output unit 340 sums the intermediate frequency signals or the baseband signals received from the switching unit 330 and outputs them (V _{OUT +} , V _{OUT −} ).

Hereinafter, the specific structure of the output part 340 is demonstrated.

The output unit 340 includes a thirteenth N-type transistor N13, a fourteenth N-type transistor N14, an eleventh resistor R11, and a twelfth resistor R12.

The source of the thirteenth N-type transistor N13 is grounded, and the drain thereof is connected to the eleventh node n11. A source of the fourteenth N-type transistor N14 is grounded, a drain is connected to the twelfth node n12, and a gate is connected to the gate of the thirteenth N-type transistor N13 through the fourteenth node n14.

One end of the eleventh resistor R11 is connected between the eleventh node n11 and the thirteenth N-type transistor N13, and the other end thereof is connected to the twelfth resistor R12 through the thirteenth node n13. .

One end of the twelfth resistor R12 is connected between the twelfth node n12 and the fourteenth N-type transistor N14, and the other end thereof is connected to the thirteenth resistor R13 through the thirteenth node n13. .

The thirteenth node n13 and the fourteenth node n14 are connected to each other.

The output V _{OUT +} terminal is connected between one end of the eleventh resistor R11 and the drain of the thirteenth N-type transistor N13, and the output V _{OUT −} terminal is connected to one end of the twelfth resistor R12. It is connected between the drain of the 14 N-type transistor (N14).

Meanwhile, in the embodiment described with reference to FIG. 7, the voltage / current converter 310 may be configured by adding a transistor that operates in the triode region. That is, the voltage current converter 310 may be configured as shown in FIG. At this time, the fifth node n5 and the sixth node n6 illustrated in FIG. 4A correspond to the fifteenth node n15 and the sixteenth node 16 illustrated in FIG. 7, respectively.

Since the configuration of the replaced voltage-current converter 310 is as described with reference to FIG. 4A, detailed description thereof will be omitted herein. However, since the embodiment illustrated in FIG. 7 relates to a common mode, 'V _{IN +} ' illustrated in (a) of FIG. 4 is represented by 'V _IN ', and 'V _{IN +} -V _aux ' is represented by 'V. _It is represented by _IN -V _aux '.

In addition, in the embodiment described with reference to FIG. 7, a current source as shown in FIG. 5A may be added to one side of the current gain unit 320 in advance. At this time, the fifth node n5 and the ninth node n9 illustrated in FIG. 5A correspond to the fifteenth node n15 and the nineteenth node n19 illustrated in FIG. 7, respectively.

Additional components are as described with reference to Fig. 5 (a), the detailed description thereof will be omitted here.

Also, in the embodiment described with reference to FIG. 7, the output unit 340 may be configured using only a resistor as shown in FIG. 6A, or an LC tank as shown in FIG. 6B is used. It can be configured using. At this time, the first node n1, the second node n2, and the sixth node n6 shown in FIGS. 6A and 6B are the eleventh node n11 shown in FIG. It corresponds to the twelfth node n12 and the sixteenth node n16.

Since the configuration of the output unit 340 is the same as described with reference to Figure 6, the detailed description thereof will be omitted here.

In the drawings for describing embodiments of the present invention, a circuit using a metal oxide semiconductor field effect transistor (MOSFET) is illustrated, but the present invention is not limited thereto and may be applied to a circuit using a bipolar junction transistor (BJT). The present invention can also be applied to a circuit by interchange between an N-type transistor and a P-type transistor.

On the other hand, while the above has been shown and described with respect to the preferred embodiments of the present invention, the present invention is not limited to the specific embodiments described above, the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims Of course, various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

10: mixer
110: transconductor 111, 112, 113: transconductance stage
120: switching unit 121, 122, 123: switching stage
130: output unit 141, 142, 143: current source
310, 310a, 310b: voltage current converter
320: current mirror gain
330: switching unit 331, 332, 333: switching stage
340: output section 341, 342: LC tank

Claims (12)

A voltage current converter for converting an input voltage signal into a current signal;
A current mirror gain unit for mirroring current signals received from the voltage current converter and distributing them into N current signals having current ratios set therebetween;
N differential baseband signals or N differentials are obtained by frequency mixing each of the N current signals received from the current mirror gain unit and the N local oscillator (LO) signal pairs input from the outside. A switching unit generating an intermediate frequency (IF) signal; And
An output unit for outputting a differential output signal by summing N differential baseband signals or N differential intermediate frequency signals received from the switching unit
Harmonic removal mixer comprising.
The method of claim 1, wherein the voltage current converter,
To convert the input differential voltage signal into a differential current signal
Harmonic Removal Mixer.
The method of claim 2, wherein the current mirror gain unit,
First to Nth current mirror stages for mirroring the current signal received from the voltage current converter according to a set mirror ratio
Harmonic removal mixer comprising.
The method of claim 3, wherein each of the first to Nth current mirror stages,
Mirroring the first differential current signal and the second differential current signal received from the voltage current converter with the same mirror ratio
Harmonic Removal Mixer.
The method of claim 4, wherein the switching unit,
First to Nth to generate an Nth differential baseband signal or an Nth differential intermediate frequency signal by frequency mixing the Nth current signal received from the first to Nth current mirror stages and the input Nth local oscillation signal pair Switching stage
Harmonic removal mixer comprising.
The method of claim 5, wherein each of the first to Nth switching stages,
A first differential transistor pair for frequency mixing the input first differential current signal and the Nth local oscillation signal pair; And
A second differential transistor pair for frequency mixing the input second differential current signal and the Nth local oscillation signal pair
Harmonic removal mixer comprising.
The method of claim 6, wherein the output unit,
A first output terminal coupled to an output node of the first differential transistor pairs; And
A second output terminal connected to the output node of the second differential transistor pairs
Harmonic removal mixer comprising.
The method of claim 1, wherein the current mirror gain unit,
Current source to receive the current signal received from the voltage current converter
Harmonic removal mixer containing more.
The method of claim 1, wherein the current ratio is,

sign
Harmonic Removal Mixer.
The method of claim 1, wherein the N local oscillation signal pairs,
Having phase differences set to each other
Harmonic Removal Mixer.
The method of claim 10, wherein each of the N local oscillation signal pairs,
Containing two local oscillating signals that are out of phase with each other
Harmonic Removal Mixer.
The method of claim 4, wherein the first differential current signal and the second differential current signal,
Out of phase
Harmonic Removal Mixer.

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