KR20120088134A - Semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device is provided to maximize the use of a semiconductor area by arranging a reservoir capacitor in a chip guard ring area. CONSTITUTION: A second well area(102) is separately formed from a first well area(101). One or more first transistors(Tr1) are formed on the first well area. One or more second transistors(Tr2) are formed on the second well area. A reservoir capacitor(RC1) is arranged on the overlapped area of the first and the second well areas. The reservoir capacitor includes a first power source terminal(120), a second power source terminal(140) and high-capacity capacitors(160,180).

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to layouts relating to leisure bar capacitor arrangements.

The semiconductor device includes a plurality of power supply voltages therein, and includes a reservoir capacitor capacitor to remove noise of the power supply voltage. Such a leisure bar capacitor is generally disposed in a peripheral circuit area, which is a sub word line driver, a sense amplifer, or the like for controlling a memory cell or supplying power or the like. A number of peripheral circuits, such as a power circuit, are arranged. The conventional arrangement of the leisure bar capacitor has been arranged by utilizing the remaining space in which the peripheral circuits are arranged in the peripheral circuit area. However, as the semiconductor device is highly integrated, a spare space in which the leisure bar capacitor can be arranged is also provided. It's getting smaller.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and an object thereof is to provide a leisure bar capacitor layout for efficiently placing a leisure bar capacitor in a semiconductor device.

In order to achieve the above object, the semiconductor device of the present invention comprises: a first well region of a substrate; A second well region of the substrate spaced apart from the first well region; One or more first transistors formed in the first well region; At least one second transistor formed in the second well region; And at least one leisure bar capacitor disposed in an area in which the first well region and the second well region overlap each other, and formed on the first transistor and the second transistor.

The present invention can be an efficient arrangement scheme for the area of the reduced leisure bar capacitor. The leisure bar capacitor structure of the present invention can provide a large capacitance without increasing the chip area.

1A to 1B are views for explaining a layout method of a leisure bar capacitor according to a first embodiment of the present invention;
2a to 2d are views for explaining the structure of the leisure bar capacitor
3 is a view for explaining a leisure bar capacitor arrangement according to a second embodiment of the present invention;
4 is a view for explaining the arrangement of the leisure bar capacitor according to the third embodiment of the present invention;

In the following, the most preferred embodiment of the present invention is described. In the drawings, the thickness and spacing are expressed for convenience of description and may be exaggerated compared to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. In adding reference numerals to the components of each drawing, it should be noted that the same components as possible have the same number, even if displayed on different drawings.

1A to 1B are views for explaining a layout method of a leisure bar capacitor according to a first embodiment of the present invention. FIG. 1A is a layout diagram, and FIG. 1B is a cross-sectional view taken along line XX 'of FIG. 1A.

1A and 1B, a first MOS transistor group Tr1 and a second MOS transistor group Tr2 constituting a logic circuit of a peripheral circuit region are illustrated. Although only one Tr1 and Tr2 is shown in the figure, a group may be formed of a plurality of transistors. The gates G1 and G2 of the gates Tr1 and Tr2 may extend in a line shape.

Tr1 and Tr2 are formed on the wells 101 and 102, and the wells 101 and 102 have well guard rings 103 and 104, respectively.

The well 101 and the well 102 may have different conductivity types. Accordingly, when well 101 is doped to P type, Tr1 becomes an NMOS transistor, and when well 102 is doped to N type, Tr2 becomes a PMOS transistor.

If well 101 and well 102 have different conductivity types, in terms of implant margin, well 101 and well 102 require a minimum margin W1 to be spaced apart from each other.

In the related art, since a leisure bar capacitor is formed of a MOS capacitor, and the MOS capacitor is formed by forming a MOS transistor on a substrate, a MOS capacitor is disposed between W1 which is a margin between the wells 101 and the wells 102.

However, in the present invention, since the leisure bar capacitor RC1 is configured as a stack capacitor, the stack capacitor may be disposed on the MOS transistor, and thus it is not necessarily disposed between 'W1'.

The leisure bar capacitor RC1 according to an exemplary embodiment of the present invention may be disposed on the upper portions of Tr1 and Tr2. Reference numeral 110 denotes a leisure bar capacitor arrangement area in which the leisure bar capacitor RC1 may be disposed, and in consideration of process issues, for example, misalignment or punch throw phenomenon when forming an upper metal contact, It may be disposed between the gate electrode G1 of Tr1 and the gate electrode G2 of Tr2.

Here, the structure of the stacked capacitor according to an embodiment of the present invention is as follows.

The leisure bar capacitor RC1 includes the first power supply terminal 120 and the second power supply terminal 140 and at least two large capacity capacitors 160 and 180 connected in series therebetween.

Here, the large capacitors 160 and 180 may be formed in the same structure as the cell capacitor formed in the cell region. That is, it is formed of a stacked capacitor.

2A to 2D are views for explaining the structure of the leisure bar capacitor.

2A is an equivalent circuit of the first example of the leisure bar capacitor.

Referring to FIG. 2A, the leisure bar capacitor includes a first power supply 220 and a second power supply 240, and includes at least two large capacity capacitors 260 and 280 connected in series between the first power supply 220 and the second power supply 240. Include. The large capacity capacitors 260 and 280 have a capacitance of uF class.

The capacitors 260 and 280 are stacked in order of stacking a first electrode (storage node), a dielectric, and a second electrode (plate), and the first electrode and the second electrode of each of the capacitors are made of polysilicon or a metal thin film. In addition, the dielectric may use high dielectric constant and ferroelectric.

As described above, the leisure bar capacitors use large-capacity capacitors 260 and 280 to remove low frequency noise. In addition, since the large-capacitors 260 and 280 may have a problem in that leakage current increases when a high voltage is applied, at least two large-capacity capacitors are connected in series.

2B is an equivalent circuit of a second example of a leisure bar capacitor.

Referring to FIG. 2B, the leisure bar capacitor includes a first power supply unit 220 and a second power supply 240, and includes a first capacitor group 260 ′ having a plurality of large capacity capacitors connected in parallel and a plurality of large capacity capacitors connected in parallel. Having a second capacitor group 280 '.

Here, the first capacitor group 260 ′ and the second capacitor group 280 ′ are connected in series between the first and second power supply units 220 and 240.

Each unit large capacity capacitor belonging to the first and second capacitor groups has a capacitance of uF class. In the present exemplary embodiment, two capacitor groups 260 'and 280' are connected in series, but three or more capacitor groups connected in series may be used.

In addition, the large-capacity capacitors belonging to each capacitor group have a structure in which a first electrode (storage node), a dielectric, and a second electrode (plate) are sequentially stacked, as described in the embodiment of FIG. 2A. The second electrode may be polysilicon, a metal thin film, or the like, and the dielectric may be a high dielectric material and a ferroelectric material.

Here, the unit large capacity capacitors belonging to the first and second capacitor groups may be represented by one equivalent capacitor, and in this case, may be represented by the equivalent circuit as in the first embodiment.

FIG. 2C is a layout diagram of capacitor groups 260 'and 280' shown in FIG. 2B. When connected in series with a capacitor group as in the second embodiment, patterning of the second electrode (plate) of the large capacity capacitor becomes easy.

Referring to FIG. 2C, a first power line 220 receiving first power and a second power line 240 receiving second power are provided. The first power line 220 contacts the first electrodes 263a, 263b, 263c, and 263d of each of the capacitors belonging to the first capacitor group 260, and the second power line 240 contacts the first capacitors of the capacitors belonging to the second capacitor group 280. Electrodes 283a, 283b, 283c, and 283d are contacted. The second electrode (plate) 265 of each of the large capacitors of the first capacitor group 260 and the second capacitor group 280 is formed as a common electrode by a single conductive layer pattern.

The leisure bar capacitor according to the first example illustrated in FIG. 2A has a layout as illustrated in FIG. 2C, in which only the number of large capacity capacitors is different.

FIG. 2D is a cross-sectional view taken along the line A-B of FIG. 2C.

Referring to FIG. 2D, the first power line 220 and the second power line 240 are provided on the peripheral circuit region. The first and second power lines 220 and 240 are patterned with a conductive layer such as metal or polysilicon. First electrodes 263a, 263b, 283a, and 283b of the capacitors penetrate through the insulating layer 10 and contact the first and second power lines 220 and 240. A dielectric 264 is formed on the entire substrate structure including the first electrodes 263a, 263b, 283a, and 283b, and a second electrode 265 is formed on the dielectric 264. The dielectrics 264 and the second electrode 265 are not commonly separated for each of the large-capacity capacitors but are commonly formed by the same thin film. However, the dielectrics 264 and the second electrode 265 may be formed separately.

3 is a view for explaining the arrangement of the leisure bar capacitor according to the second embodiment of the present invention. In particular, FIG. 3 illustrates that a leisure bar capacitor is disposed in a pad (PAD) area of a peripheral circuit area, and shows how a memory cell having a cell capacitor and a leisure bar capacitor are configured.

In general, a pad metal 330 is formed at the top of the pad region to connect with the outside. In addition, a dummy metal 340 is formed under the pad metal 330, and serves to support the pad metal 330. Then, the pin capacitor 350 is formed on the lower substrate.

The leisure bar capacitor RC2 according to the second embodiment of the present invention may be disposed in an excess space under the pad metal 301.

More specifically, the layer between the pad metal 301 and the pin capacitor 303 is a space in which a cell capacitor and a bit line are formed in the cell region, and forms a cell capacitor and a bit line of the cell region, while the leisure bar capacitor RC2 is formed. ) Can be formed together.

Referring to FIG. 3, a memory cell including a cell capacitor 320A is formed in a cell region, and a pad including a leisure bar capacitor is formed in a pad region.

The leisure bar capacitor RC2 includes first and second large capacity capacitors 320B and 320C connected in series between the first power line 310B and the second power line. Although only two large capacitors are shown in the figure, more than this can be configured. Also, although not shown in FIG. 3, the leisure bar capacitor may be configured in various ways as shown in FIGS. 2A and 2B.

The first and second large capacity capacitors 320B and 320C constituting the leisure bar capacitor RC2 have substantially the same capacitance as the cell capacitor 320A.

The cell capacitor 320A is a stack capacitor having a capacitor on bitline (COB) structure formed on the bit line 310A on the substrate. The cell capacitor 320A includes a storage node 322A, a dielectric 324A formed on the storage node 322A, and a plate electrode 326A formed on the dielectric 324A.

The first large capacity capacitor 320B is formed on the first electrode 322B having the same material and surface area as the storage node 322A, the first electrode 322A, the dielectric 324B formed of the same material as the dielectric capacitor 324A of the cell capacitor, and the plate electrode 324B. A second electrode 326B is formed of the same material as 326A. Thus, the cell capacitor 320A and the first high capacity capacitor 720B have substantially the same capacitance. The first electrode 322C, the dielectric 324C, and the second electrode 326C of the second high capacity capacitor 320C are also formed in the same manner as those of the first high capacity capacitor 320B, respectively.

The first electrode 322B of the first large capacity capacitor 320B is contacted and connected to the first power supply line 310B, and the first electrode 722C of the second large capacity capacitor 320C is contacted and connected to the second power supply line 310C. The first electrode 322B of the first high capacity capacitor 320B and the first electrode 322C of the second high capacity capacitor 320C are formed by patterning the same conductive layer.

The second electrode 326B of the first large capacity capacitor 320B and the second electrode 326C of the second large capacity capacitor 320C are commonly configured by a single conductive layer pattern.

The first power line 310B and the second power line 310C are the same conductive layers as the bit line 310A in the cell region and are patterned and separated. The first power line 310B and the second power line 310C may use other conductive layers in addition to the bit line conductive layer.

Each dielectric layer of the first and second high capacity capacitors 320B and 320C may be a high dielectric thin film or a ferroelectric thin film.

In FIG. 3, reference numeral '302' denotes a silicon substrate, '303' denotes a gate electrode of a cell transistor, and '304', '305', and '306' denote contact plugs.

As described above, the leisure bar capacitor arrangement example according to the second embodiment of the present invention has an advantage of providing a leisure bar capacitor having a large capacitance while utilizing an existing area.

4 is a view for explaining the arrangement of the leisure bar capacitor according to the third embodiment of the present invention.

Referring to FIG. 4, a semiconductor chip is divided into a cell region 401 in which a cell is formed and a peripheral circuit region 402 in which a peripheral circuit is disposed in a space between the cell region 401. In addition, a chip guard ring 404 for protecting the chip is formed for each unit semiconductor chip. The chip guard ring 404 is formed to prevent moisture absorption and crack expansion for cracks generated during sawing of the wafer. The chip guard ring 404 is formed to secure reliability of a semiconductor memory device. The chip guard ring 404 is not provided with a separate circuit.

The leisure bar capacitor arrangement according to the third embodiment of the present invention arranges the leisure bar capacitor in the chip guard ring 404. The structure of the leisure bar capacitor disposed on the chip guard ring 404 is the same as the structure of the leisure bar capacitor described in the first and second embodiments of the present invention.

As such, by arranging the leisure bar capacitor in an area of the chip guard ring 404 in which a separate semiconductor device is not formed, the utilization of the semiconductor area can be maximized and the leisure bar capacitor formation space reduced by the integration of semiconductor devices can be secured. have.

The present invention is not limited to the above-described embodiments, but can be implemented in various forms, and the above-described embodiments make the disclosure of the present invention complete so that those skilled in the art can fully understand the scope of the invention. It is provided to give. Therefore, it should be noted that the scope of the present invention should be understood by the claims of the present application.

101, 102: substrate 103, 104: well guard ring
120, 220. 310B: first power supply 140, 240, 310C: second power supply
160, 180, 320B, 320C: large capacity capacitor
110: leisure bar capacitor placement area

Claims (7)

A first well region of the substrate;
A second well region of the substrate spaced apart from the first well region;
One or more first transistors formed in the first well region;
At least one second transistor formed in the second well region; And
At least one leisure bar capacitor disposed on the first well region and the second well region, wherein the at least one leisure bar capacitor is formed on the first transistor and the second transistor;
Semiconductor device.
The method of claim 1,
The first well and the second well are of different conductivity types
Semiconductor devices
The method of claim 1,
The overlapping area is an area between the gate of the first transistor and the gate of the second transistor.
Semiconductor device.
Board;
A first layer having a pin capacitor formed on the substrate;
A second layer having a pad metal formed on the first layer; And
And a leisure bar capacitor formed in a layer between the first layer and the second layer.
Semiconductor device.
Board;
A first region in which a chip guard ring is formed to protect the substrate; And
Overlapping the first region, including a leisure bar capacitor formed in the region of the upper portion of the chip guard ring
Semiconductor device.
The method according to any one of claims 1 to 4 or 5,
The leisure bar capacitor may include a first power supply means and a second power supply means; And
And at least two large capacity capacitors connected in series between the first power supply means and the second power supply means.
Semiconductor devices
The method of claim 6,
The leisure bar capacitor is a stacked capacitor in which a lower electrode conductive layer, a dielectric layer, and an upper electrode conductive layer are sequentially stacked.
Semiconductor device.

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